[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281
HplAtm128UartP.nc, 1.1, 1.2
Janos Sallai
sallai at users.sourceforge.net
Fri Dec 14 12:30:15 PST 2007
Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/atm1281
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv5740
Modified Files:
HplAtm128UartP.nc
Log Message:
merge changes from atm128 UART
Index: HplAtm128UartP.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/atm1281/HplAtm128UartP.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** HplAtm128UartP.nc 5 Nov 2007 20:36:40 -0000 1.1
--- HplAtm128UartP.nc 14 Dec 2007 20:30:13 -0000 1.2
***************
*** 129,133 ****
command error_t Uart0TxControl.start() {
- SET_BIT(UCSR0B, TXCIE0);
SET_BIT(UCSR0B, TXEN0);
call McuPowerState.update();
--- 129,132 ----
***************
*** 136,140 ****
command error_t Uart0TxControl.stop() {
- CLR_BIT(UCSR0B, TXCIE0);
CLR_BIT(UCSR0B, TXEN0);
call McuPowerState.update();
--- 135,138 ----
***************
*** 143,147 ****
command error_t Uart0RxControl.start() {
- SET_BIT(UCSR0B, RXCIE0);
SET_BIT(UCSR0B, RXEN0);
call McuPowerState.update();
--- 141,144 ----
***************
*** 150,154 ****
command error_t Uart0RxControl.stop() {
- CLR_BIT(UCSR0B, RXCIE0);
CLR_BIT(UCSR0B, RXEN0);
call McuPowerState.update();
--- 147,150 ----
***************
*** 157,176 ****
async command error_t HplUart0.enableTxIntr() {
! SET_BIT(UCSR0B, TXEN0);
return SUCCESS;
}
async command error_t HplUart0.disableTxIntr(){
! CLR_BIT(UCSR0B, TXEN0);
return SUCCESS;
}
async command error_t HplUart0.enableRxIntr(){
! SET_BIT(UCSR0B, RXEN0);
return SUCCESS;
}
async command error_t HplUart0.disableRxIntr(){
! CLR_BIT(UCSR0B, RXEN0);
return SUCCESS;
}
--- 153,173 ----
async command error_t HplUart0.enableTxIntr() {
! SET_BIT(UCSR0A, TXC0);
! SET_BIT(UCSR0B, TXCIE0);
return SUCCESS;
}
async command error_t HplUart0.disableTxIntr(){
! CLR_BIT(UCSR0B, TXCIE0);
return SUCCESS;
}
async command error_t HplUart0.enableRxIntr(){
! SET_BIT(UCSR0B, RXCIE0);
return SUCCESS;
}
async command error_t HplUart0.disableRxIntr(){
! CLR_BIT(UCSR0B, RXCIE0);
return SUCCESS;
}
***************
*** 226,230 ****
command error_t Uart1TxControl.start() {
- SET_BIT(UCSR1B, TXCIE1);
SET_BIT(UCSR1B, TXEN1);
call McuPowerState.update();
--- 223,226 ----
***************
*** 233,237 ****
command error_t Uart1TxControl.stop() {
- CLR_BIT(UCSR1B, TXCIE1);
CLR_BIT(UCSR1B, TXEN1);
call McuPowerState.update();
--- 229,232 ----
***************
*** 240,244 ****
command error_t Uart1RxControl.start() {
- SET_BIT(UCSR1B, RXCIE1);
SET_BIT(UCSR1B, RXEN1);
call McuPowerState.update();
--- 235,238 ----
***************
*** 247,251 ****
command error_t Uart1RxControl.stop() {
- CLR_BIT(UCSR1B, RXCIE1);
CLR_BIT(UCSR1B, RXEN1);
call McuPowerState.update();
--- 241,244 ----
***************
*** 254,273 ****
async command error_t HplUart1.enableTxIntr() {
! SET_BIT(UCSR1B, TXEN1);
return SUCCESS;
}
async command error_t HplUart1.disableTxIntr(){
! CLR_BIT(UCSR1B, TXEN1);
return SUCCESS;
}
async command error_t HplUart1.enableRxIntr(){
! SET_BIT(UCSR1B, RXEN1);
return SUCCESS;
}
async command error_t HplUart1.disableRxIntr(){
! CLR_BIT(UCSR1B, RXEN1);
return SUCCESS;
}
--- 247,267 ----
async command error_t HplUart1.enableTxIntr() {
! SET_BIT(UCSR1A, TXC1);
! SET_BIT(UCSR1B, TXCIE1);
return SUCCESS;
}
async command error_t HplUart1.disableTxIntr(){
! CLR_BIT(UCSR1B, TXCIE1);
return SUCCESS;
}
async command error_t HplUart1.enableRxIntr(){
! SET_BIT(UCSR1B, RXCIE1);
return SUCCESS;
}
async command error_t HplUart1.disableRxIntr(){
! CLR_BIT(UCSR1B, RXCIE1);
return SUCCESS;
}
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