[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281
HplAtm128UartP.nc, NONE, 1.1 McuSleepC.nc, NONE,
1.1 atm128hardware.h, NONE, 1.1
Janos Sallai
sallai at users.sourceforge.net
Mon Nov 5 12:36:43 PST 2007
Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/atm1281
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv27101/atm1281
Added Files:
HplAtm128UartP.nc McuSleepC.nc atm128hardware.h
Log Message:
platform support for the IRIS mote (atm1218 MCU and rf230 radio)
--- NEW FILE: HplAtm128UartP.nc ---
/*
* Copyright (c) 2006 Arch Rock Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the
* distribution.
* - Neither the name of the Arch Rock Corporation nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* ARCH ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
* OF THE POSSIBILITY OF SUCH DAMAGE
*/
/**
* @author Alec Woo <awoo at archrock.com>
* @author Jonathan Hui <jhui at archrock.com>
* @version $Revision: 1.1 $ $Date: 2007/11/05 20:36:40 $
*/
/*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
* ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
* IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
* OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
* MODIFICATIONS.
*/
/*
* Copyright (c) 2007, Vanderbilt University
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*
*/
/**
* Private component of the Atmega1281 serial port HPL.
*
* @author Martin Turon <mturon at xbow.com>
* @author David Gay
* @author Janos Sallai <janos.sallai at vanderbilt.edu>
*/
#include <Atm128Uart.h>
module HplAtm128UartP {
provides interface Init as Uart0Init;
provides interface StdControl as Uart0TxControl;
provides interface StdControl as Uart0RxControl;
provides interface HplAtm128Uart as HplUart0;
provides interface Init as Uart1Init;
provides interface StdControl as Uart1TxControl;
provides interface StdControl as Uart1RxControl;
provides interface HplAtm128Uart as HplUart1;
uses interface Atm128Calibrate;
uses interface McuPowerState;
}
implementation {
//=== Uart Init Commands. ====================================
command error_t Uart0Init.init() {
Atm128UartMode_t mode;
Atm128UartStatus_t stts;
Atm128UartControl_t ctrl;
uint16_t ubrr0;
ctrl.bits = (struct Atm128_UCSRB_t) {rxcie:0, txcie:0, rxen:0, txen:0};
stts.bits = (struct Atm128_UCSRA_t) {u2x:1};
mode.bits = (struct Atm128_UCSRC_t) {ucsz:ATM128_UART_DATA_SIZE_8_BITS};
ubrr0 = call Atm128Calibrate.baudrateRegister(PLATFORM_BAUDRATE);
UBRR0L = ubrr0;
UBRR0H = ubrr0 >> 8;
UCSR0A = stts.flat;
UCSR0C = mode.flat;
UCSR0B = ctrl.flat;
return SUCCESS;
}
command error_t Uart0TxControl.start() {
SET_BIT(UCSR0B, TXCIE0);
SET_BIT(UCSR0B, TXEN0);
call McuPowerState.update();
return SUCCESS;
}
command error_t Uart0TxControl.stop() {
CLR_BIT(UCSR0B, TXCIE0);
CLR_BIT(UCSR0B, TXEN0);
call McuPowerState.update();
return SUCCESS;
}
command error_t Uart0RxControl.start() {
SET_BIT(UCSR0B, RXCIE0);
SET_BIT(UCSR0B, RXEN0);
call McuPowerState.update();
return SUCCESS;
}
command error_t Uart0RxControl.stop() {
CLR_BIT(UCSR0B, RXCIE0);
CLR_BIT(UCSR0B, RXEN0);
call McuPowerState.update();
return SUCCESS;
}
async command error_t HplUart0.enableTxIntr() {
SET_BIT(UCSR0B, TXEN0);
return SUCCESS;
}
async command error_t HplUart0.disableTxIntr(){
CLR_BIT(UCSR0B, TXEN0);
return SUCCESS;
}
async command error_t HplUart0.enableRxIntr(){
SET_BIT(UCSR0B, RXEN0);
return SUCCESS;
}
async command error_t HplUart0.disableRxIntr(){
CLR_BIT(UCSR0B, RXEN0);
return SUCCESS;
}
async command bool HplUart0.isTxEmpty(){
return READ_BIT(UCSR0A, TXC0);
}
async command bool HplUart0.isRxEmpty(){
return !READ_BIT(UCSR0A, RXC0);
}
async command uint8_t HplUart0.rx(){
return UDR0;
}
async command void HplUart0.tx(uint8_t data) {
atomic{
UDR0 = data;
SET_BIT(UCSR0A, TXC0);
}
}
AVR_ATOMIC_HANDLER(SIG_USART0_RECV) {
if (READ_BIT(UCSR0A, RXC0)) {
signal HplUart0.rxDone(UDR0);
}
}
AVR_NONATOMIC_HANDLER(SIG_USART0_TRANS) {
signal HplUart0.txDone();
}
command error_t Uart1Init.init() {
Atm128UartMode_t mode;
Atm128UartStatus_t stts;
Atm128UartControl_t ctrl;
uint16_t ubrr1;
ctrl.bits = (struct Atm128_UCSRB_t) {rxcie:0, txcie:0, rxen:0, txen:0};
stts.bits = (struct Atm128_UCSRA_t) {u2x:1};
mode.bits = (struct Atm128_UCSRC_t) {ucsz:ATM128_UART_DATA_SIZE_8_BITS};
ubrr1 = call Atm128Calibrate.baudrateRegister(PLATFORM_BAUDRATE);
UBRR1L = ubrr1;
UBRR1H = ubrr1 >> 8;
UCSR1A = stts.flat;
UCSR1C = mode.flat;
UCSR1B = ctrl.flat;
return SUCCESS;
}
command error_t Uart1TxControl.start() {
SET_BIT(UCSR1B, TXCIE1);
SET_BIT(UCSR1B, TXEN1);
call McuPowerState.update();
return SUCCESS;
}
command error_t Uart1TxControl.stop() {
CLR_BIT(UCSR1B, TXCIE1);
CLR_BIT(UCSR1B, TXEN1);
call McuPowerState.update();
return SUCCESS;
}
command error_t Uart1RxControl.start() {
SET_BIT(UCSR1B, RXCIE1);
SET_BIT(UCSR1B, RXEN1);
call McuPowerState.update();
return SUCCESS;
}
command error_t Uart1RxControl.stop() {
CLR_BIT(UCSR1B, RXCIE1);
CLR_BIT(UCSR1B, RXEN1);
call McuPowerState.update();
return SUCCESS;
}
async command error_t HplUart1.enableTxIntr() {
SET_BIT(UCSR1B, TXEN1);
return SUCCESS;
}
async command error_t HplUart1.disableTxIntr(){
CLR_BIT(UCSR1B, TXEN1);
return SUCCESS;
}
async command error_t HplUart1.enableRxIntr(){
SET_BIT(UCSR1B, RXEN1);
return SUCCESS;
}
async command error_t HplUart1.disableRxIntr(){
CLR_BIT(UCSR1B, RXEN1);
return SUCCESS;
}
async command bool HplUart1.isTxEmpty() {
return READ_BIT(UCSR1A, TXC1);
}
async command bool HplUart1.isRxEmpty() {
return !READ_BIT(UCSR1A, RXC1);
}
async command uint8_t HplUart1.rx(){
return UDR1;
}
async command void HplUart1.tx(uint8_t data) {
atomic{
UDR1 = data;
SET_BIT(UCSR1A, TXC1);
}
}
AVR_ATOMIC_HANDLER(SIG_USART1_RECV) {
if (READ_BIT(UCSR1A, RXC1))
signal HplUart1.rxDone(UDR1);
}
AVR_NONATOMIC_HANDLER(SIG_USART1_TRANS) {
signal HplUart1.txDone();
}
default async event void HplUart0.txDone() {}
default async event void HplUart0.rxDone(uint8_t data) {}
default async event void HplUart1.txDone() {}
default async event void HplUart1.rxDone(uint8_t data) {}
}
--- NEW FILE: McuSleepC.nc ---
/// $Id: McuSleepC.nc,v 1.1 2007/11/05 20:36:41 sallai Exp $
/*
* "Copyright (c) 2005 Stanford University. All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and
* its documentation for any purpose, without fee, and without written
* agreement is hereby granted, provided that the above copyright
* notice, the following two paragraphs and the author appear in all
* copies of this software.
*
* IN NO EVENT SHALL STANFORD UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES
* ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
* IF STANFORD UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* STANFORD UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE
* PROVIDED HEREUNDER IS ON AN "AS IS" BASIS, AND STANFORD UNIVERSITY
* HAS NO OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES,
* ENHANCEMENTS, OR MODIFICATIONS."
*/
/*
* Copyright (c) 2007, Vanderbilt University
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*
*/
/**
* Implementation of TEP 112 (Microcontroller Power Management) for
* the Atmega128. Power state calculation code copied from Rob
* Szewczyk's 1.x code in HPLPowerManagementM.nc.
*
* <pre>
* $Id: McuSleepC.nc,v 1.1 2007/11/05 20:36:41 sallai Exp $
* </pre>
*
* @author Philip Levis
* @author Robert Szewczyk
* @author Janos Sallai <janos.sallai at vanderbilt.edu>
* @date October 30, 2007
*/
module McuSleepC {
provides {
interface McuSleep;
interface McuPowerState;
}
uses {
interface McuPowerOverride;
}
}
implementation {
/* There is no dirty bit management because the sleep mode depends on
the amount of time remaining in timer2. */
/* Note that the power values are maintained in an order
* based on their active components, NOT on their values.
* Look at atm1281hardware.h and page 54 of the ATmeg1281
* manual (Table 25).*/
const_uint8_t atm128PowerBits[ATM128_POWER_DOWN + 1] = {
0,
(1 << SM0),
(1 << SM2) | (1 << SM1) | (1 << SM0),
(1 << SM1) | (1 << SM0),
(1 << SM2) | (1 << SM1),
(1 << SM1)};
mcu_power_t getPowerState() {
// Note: we go to sleep even if timer 0, 1, 3, 4, or 5's overflow interrupt
// is enabled - this allows using these timers as TinyOS "Alarm"s
// while still having power management.
// Are external timers running?
if (
TIMSK0 & (1 << OCIE0A | 1 << OCIE0B | 1 << TOIE0) ||
TIMSK1 & (1 << ICIE1 | 1 << OCIE1A | 1 << OCIE1B | 1 << OCIE1C | 1 << TOIE1) ||
TIMSK3 & (1 << ICIE3 | 1 << OCIE3A | 1 << OCIE3B | 1 << OCIE3C | 1 << TOIE3) ||
// input capture and output compare for timer 4 and 5 are
// not functional on atm1281
TIMSK4 & (1 << TOIE4) ||
TIMSK5 & (1 << TOIE5)
) {
return ATM128_POWER_IDLE;
}
// SPI (Radio stack)
else if (bit_is_set(SPCR, SPIE)) {
return ATM128_POWER_IDLE;
}
// UARTs are active
else if (UCSR0B & (1 << TXCIE0 | 1 << RXCIE0)) { // UART
return ATM128_POWER_IDLE;
}
else if (UCSR1B & (1 << TXCIE1 | 1 << RXCIE1)) { // UART
return ATM128_POWER_IDLE;
}
// I2C (Two-wire) is active
else if (bit_is_set(TWCR, TWEN)){
return ATM128_POWER_IDLE;
}
// ADC is enabled
else if (bit_is_set(ADCSRA, ADEN)) {
return ATM128_POWER_ADC_NR;
}
else {
return ATM128_POWER_DOWN;
}
}
async command void McuSleep.sleep() {
uint8_t powerState;
powerState = mcombine(getPowerState(), call McuPowerOverride.lowestState());
SMCR =
(SMCR & 0xf0) | 1 << SE | read_uint8_t(&atm128PowerBits[powerState]);
sei();
asm volatile ("sleep");
cli();
CLR_BIT(SMCR, SE);
}
async command void McuPowerState.update() {
}
default async command mcu_power_t McuPowerOverride.lowestState() {
return ATM128_POWER_DOWN;
}
}
--- NEW FILE: atm128hardware.h ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Copyright (c) 2004-2005 Crossbow Technology, Inc.
* Copyright (c) 2002-2003 Intel Corporation.
* Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written
* agreement is hereby granted, provided that the above copyright
* notice, the (updated) modification history and the author appear in
* all copies of this source code.
*
* Permission is also granted to distribute this software under the
* standard BSD license as contained in the TinyOS distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/*
* Copyright (c) 2007, Vanderbilt University
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*
*/
/*
* Updated chips/atm128/atm128hardware.h with atm1281's MCU status and
* memory control registers.
*
* @author Janos Sallai, Martin Turon, Jason Hill, Philip Levis, Nelson Lee, David Gay
*/
#ifndef _H_atmega128hardware_H
#define _H_atmega128hardware_H
#include <avr/io.h>
#if __AVR_LIBC_VERSION__ >= 10400UL
#include <avr/interrupt.h>
#else
#include <avr/interrupt.h>
#include <avr/signal.h>
#endif
#include <avr/wdt.h>
#include <avr/pgmspace.h>
#include "atm128const.h"
/* We need slightly different defs than SIGNAL, INTERRUPT */
#define AVR_ATOMIC_HANDLER(signame) \
void signame() __attribute__ ((signal)) @atomic_hwevent() @C()
#define AVR_NONATOMIC_HANDLER(signame) \
void signame() __attribute__ ((interrupt)) @hwevent() @C()
/* Macro to create union casting functions. */
#define DEFINE_UNION_CAST(func_name, from_type, to_type) \
to_type func_name(from_type x) { \
union {from_type f; to_type t;} c = {f:x}; return c.t; }
// Bit operators using bit number
#define SET_BIT(port, bit) ((port) |= _BV(bit))
#define CLR_BIT(port, bit) ((port) &= ~_BV(bit))
#define READ_BIT(port, bit) (((port) & _BV(bit)) != 0)
#define FLIP_BIT(port, bit) ((port) ^= _BV(bit))
#define WRITE_BIT(port, bit, value) \
if (value) SET_BIT((port), (bit)); \
else CLR_BIT((port), (bit))
// Bit operators using bit flag mask
#define SET_FLAG(port, flag) ((port) |= (flag))
#define CLR_FLAG(port, flag) ((port) &= ~(flag))
#define READ_FLAG(port, flag) ((port) & (flag))
/* Enables interrupts. */
inline void __nesc_enable_interrupt() {
sei();
}
/* Disables all interrupts. */
inline void __nesc_disable_interrupt() {
cli();
}
/* Defines data type for storing interrupt mask state during atomic. */
typedef uint8_t __nesc_atomic_t;
__nesc_atomic_t __nesc_atomic_start(void);
void __nesc_atomic_end(__nesc_atomic_t original_SREG);
#ifndef NESC_BUILD_BINARY
/* @spontaneous() functions should not be included when NESC_BUILD_BINARY
is #defined, to avoid duplicate functions definitions wheb binary
components are used. Such functions do need a prototype in all cases,
though. */
/* Saves current interrupt mask state and disables interrupts. */
inline __nesc_atomic_t
__nesc_atomic_start(void) @spontaneous()
{
__nesc_atomic_t result = SREG;
__nesc_disable_interrupt();
asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
return result;
}
/* Restores interrupt mask to original state. */
inline void
__nesc_atomic_end(__nesc_atomic_t original_SREG) @spontaneous()
{
asm volatile("" : : : "memory"); /* ensure atomic section effect visibility */
SREG = original_SREG;
}
#endif
/* Defines the mcu_power_t type for atm128 power management. */
typedef uint8_t mcu_power_t @combine("mcombine");
enum {
ATM128_POWER_IDLE = 0,
ATM128_POWER_ADC_NR = 1,
ATM128_POWER_EXT_STANDBY = 2,
ATM128_POWER_SAVE = 3,
ATM128_POWER_STANDBY = 4,
ATM128_POWER_DOWN = 5,
};
/* Combine function. */
mcu_power_t mcombine(mcu_power_t m1, mcu_power_t m2) {
return (m1 < m2)? m1: m2;
}
/* MCU Status Register*/
typedef struct
{
uint8_t porf : 1; //!< Power-on Reset Flag
uint8_t extrf : 1; //!< External Reset Flag
uint8_t borf : 1; //!< Brown-out Reset Flag
uint8_t wdrf : 1; //!< Watchdog Reset Flag
uint8_t jtrf : 1; //!< JTAG Reset Flag
uint8_t resv1 : 3; //!< Reserved
} Atm128_MCUSR_t;
/* External Memory Control Register A*/
typedef struct
{
uint8_t srw00 : 1; //!< Wait-state Select Bits for Lower Sector
uint8_t srw01 : 1; //!< Wait-state Select Bits for Lower Sector
uint8_t srw10 : 1; //!< Wait-state Select Bits for Upper Sector
uint8_t srw11 : 1; //!< Wait-state Select Bits for Upper Sector
uint8_t srl : 3; //!< Wait-state Sector Limit
uint8_t sre : 1; //!< External SRAM/XMEM Enable
} Atm128_XMCRA_t;
/* External Memory Control Register B*/
typedef struct
{
uint8_t xmm : 3; //!< External Memory High Mask
uint8_t resv1 : 4; //!< Reserved
uint8_t xmbk : 1; //!< External Memory Bus-keeper Enable
} Atm128_XMCRB_t;
#endif //_H_atmega128hardware_H
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