[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281/adc
Atm128Adc.h, NONE, 1.1 Atm128AdcP.nc, NONE,
1.1 HplAtm128AdcP.nc, NONE, 1.1
Janos Sallai
sallai at users.sourceforge.net
Mon Nov 5 12:36:44 PST 2007
- Previous message: [Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281
HplAtm128UartP.nc, NONE, 1.1 McuSleepC.nc, NONE,
1.1 atm128hardware.h, NONE, 1.1
- Next message: [Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281/timer
Atm1281AlarmAsyncP.nc, NONE, 1.1 Atm128AlarmAsyncC.nc, NONE,
1.1 Atm128Timer.h, NONE, 1.1 HplAtm1281Timer1P.nc, NONE,
1.1 HplAtm1281Timer2AsyncC.nc, NONE,
1.1 HplAtm1281Timer2AsyncP.nc, NONE, 1.1 HplAtm1281Timer3P.nc,
NONE, 1.1 HplAtm128Timer1C.nc, NONE, 1.1 HplAtm128Timer3C.nc,
NONE, 1.1 HplAtm128TimerAsync.nc, NONE,
1.1 HplAtm128TimerCtrl16.nc, NONE, 1.1 HplAtm128TimerCtrl8.nc,
NONE, 1.1
- Messages sorted by:
[ date ]
[ thread ]
[ subject ]
[ author ]
Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/atm1281/adc
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv27101/atm1281/adc
Added Files:
Atm128Adc.h Atm128AdcP.nc HplAtm128AdcP.nc
Log Message:
platform support for the IRIS mote (atm1218 MCU and rf230 radio)
--- NEW FILE: Atm128Adc.h ---
// $Id: Atm128Adc.h,v 1.1 2007/11/05 20:36:41 sallai Exp $
/*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
* ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
* IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
* OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
* MODIFICATIONS.
*/
// @author Martin Turon <mturon at xbow.com>
// @author Hu Siquan <husq at xbow.com>
/*
* Copyright (c) 2007, Vanderbilt University
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*
*/
// @author Janos Sallai <janos.sallai at vanderbilt.edu>
/*
Updated chips/atm128 to include atm1281's ADCSRB register.
*/
#ifndef _H_Atm128ADC_h
#define _H_Atm128ADC_h
//================== 8 channel 10-bit ADC ==============================
/* Voltage Reference Settings */
enum {
ATM128_ADC_VREF_OFF = 0, //!< VR+ = AREF and VR- = GND
ATM128_ADC_VREF_AVCC = 1,//!< VR+ = AVcc and VR- = GND
ATM128_ADC_VREF_RSVD,
ATM128_ADC_VREF_2_56 = 3,//!< VR+ = 2.56V and VR- = GND
};
/* Voltage Reference Settings */
enum {
ATM128_ADC_RIGHT_ADJUST = 0,
ATM128_ADC_LEFT_ADJUST = 1,
};
/* ADC Multiplexer Settings */
enum {
ATM128_ADC_SNGL_ADC0 = 0,
ATM128_ADC_SNGL_ADC1,
ATM128_ADC_SNGL_ADC2,
ATM128_ADC_SNGL_ADC3,
ATM128_ADC_SNGL_ADC4,
ATM128_ADC_SNGL_ADC5,
ATM128_ADC_SNGL_ADC6,
ATM128_ADC_SNGL_ADC7,
ATM128_ADC_DIFF_ADC00_10x,
ATM128_ADC_DIFF_ADC10_10x,
ATM128_ADC_DIFF_ADC00_200x,
ATM128_ADC_DIFF_ADC10_200x,
ATM128_ADC_DIFF_ADC22_10x,
ATM128_ADC_DIFF_ADC32_10x,
ATM128_ADC_DIFF_ADC22_200x,
ATM128_ADC_DIFF_ADC32_200x,
ATM128_ADC_DIFF_ADC01_1x,
ATM128_ADC_DIFF_ADC11_1x,
ATM128_ADC_DIFF_ADC21_1x,
ATM128_ADC_DIFF_ADC31_1x,
ATM128_ADC_DIFF_ADC41_1x,
ATM128_ADC_DIFF_ADC51_1x,
ATM128_ADC_DIFF_ADC61_1x,
ATM128_ADC_DIFF_ADC71_1x,
ATM128_ADC_DIFF_ADC02_1x,
ATM128_ADC_DIFF_ADC12_1x,
ATM128_ADC_DIFF_ADC22_1x,
ATM128_ADC_DIFF_ADC32_1x,
ATM128_ADC_DIFF_ADC42_1x,
ATM128_ADC_DIFF_ADC52_1x,
ATM128_ADC_SNGL_1_23,
ATM128_ADC_SNGL_GND,
};
/* ADC Multiplexer Selection Register */
typedef struct
{
uint8_t mux : 5; //!< Analog Channel and Gain Selection Bits
uint8_t adlar : 1; //!< ADC Left Adjust Result
uint8_t refs : 2; //!< Reference Selection Bits
} Atm128Admux_t;
/* ADC Prescaler Settings */
/* Note: each platform must define ATM128_ADC_PRESCALE to the smallest
prescaler which guarantees full A/D precision. */
enum {
ATM128_ADC_PRESCALE_2 = 0,
ATM128_ADC_PRESCALE_2b,
ATM128_ADC_PRESCALE_4,
ATM128_ADC_PRESCALE_8,
ATM128_ADC_PRESCALE_16,
ATM128_ADC_PRESCALE_32,
ATM128_ADC_PRESCALE_64,
ATM128_ADC_PRESCALE_128,
// This special value is used to ask the platform for the prescaler
// which gives full precision.
ATM128_ADC_PRESCALE
};
/* ADC Enable Settings */
enum {
ATM128_ADC_ENABLE_OFF = 0,
ATM128_ADC_ENABLE_ON,
};
/* ADC Start Conversion Settings */
enum {
ATM128_ADC_START_CONVERSION_OFF = 0,
ATM128_ADC_START_CONVERSION_ON,
};
/* ADC Free Running Select Settings */
enum {
ATM128_ADC_FREE_RUNNING_OFF = 0,
ATM128_ADC_FREE_RUNNING_ON,
};
/* ADC Interrupt Flag Settings */
enum {
ATM128_ADC_INT_FLAG_OFF = 0,
ATM128_ADC_INT_FLAG_ON,
};
/* ADC Interrupt Enable Settings */
enum {
ATM128_ADC_INT_ENABLE_OFF = 0,
ATM128_ADC_INT_ENABLE_ON,
};
/* ADC Multiplexer Selection Register */
typedef struct
{
uint8_t adps : 3; //!< ADC Prescaler Select Bits
uint8_t adie : 1; //!< ADC Interrupt Enable
uint8_t adif : 1; //!< ADC Interrupt Flag
uint8_t adate : 1; //!< ADC Auto Trigger Enable
uint8_t adsc : 1; //!< ADC Start Conversion
uint8_t aden : 1; //!< ADC Enable
} Atm128Adcsra_t;
/* ADC Multiplexer Selection Register */
typedef struct
{
uint8_t adts : 3; //!< ADC Trigger Select
uint8_t mux5 : 1; //!< Analog Channel and Gain Selection Bit
uint8_t resv1 : 2; //!< Reserved
uint8_t acme : 1; //!< Analog Comparator Multiplexer Enable
uint8_t resv2 : 1; //!< Reserved
} Atm128Adcsrb_t;
typedef uint8_t Atm128_ADCH_t; //!< ADC data register high
typedef uint8_t Atm128_ADCL_t; //!< ADC data register low
// The resource identifier string for the ADC subsystem
#define UQ_ATM128ADC_RESOURCE "atm128adc.resource"
#endif //_H_Atm128ADC_h
--- NEW FILE: Atm128AdcP.nc ---
/* $Id: Atm128AdcP.nc,v 1.1 2007/11/05 20:36:42 sallai Exp $
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2005 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
* ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
* IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
* OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
* MODIFICATIONS.
*
* Copyright (c) 2007, Vanderbilt University
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*
*/
#include "Atm128Adc.h"
/**
* Internal component of the Atmega1281 A/D HAL.
*
* @author Jason Hill
* @author David Gay
* @author Philip Levis
* @author Phil Buonadonna
* @author Hu Siquan <husq at xbow.com>
* @author Janos Sallai <janos.sallai at vanderbilt.edu>
*/
module Atm128AdcP
{
provides {
interface Init;
interface AsyncStdControl;
interface Atm128AdcSingle;
interface Atm128AdcMultiple;
}
uses {
interface HplAtm128Adc;
interface Atm128Calibrate;
}
}
implementation
{
/* State for the current and next (multiple-sampling only) conversion */
struct {
bool multiple : 1; /* single and multiple-sampling mode */
bool precise : 1; /* is this result going to be precise? */
uint8_t channel : 5; /* what channel did this sample come from? */
} f, nextF;
command error_t Init.init() {
atomic
{
Atm128Adcsra_t adcsr;
adcsr.aden = ATM128_ADC_ENABLE_OFF;
adcsr.adsc = ATM128_ADC_START_CONVERSION_OFF;
adcsr.adate= ATM128_ADC_FREE_RUNNING_OFF;
adcsr.adif = ATM128_ADC_INT_FLAG_OFF;
adcsr.adie = ATM128_ADC_INT_ENABLE_OFF;
adcsr.adps = ATM128_ADC_PRESCALE_2;
call HplAtm128Adc.setAdcsra(adcsr);
}
return SUCCESS;
}
/* We enable the A/D when start is called, and disable it when stop is
called. This drops A/D conversion latency by a factor of two (but
increases idle mode power consumption a little).
*/
async command error_t AsyncStdControl.start() {
atomic call HplAtm128Adc.enableAdc();
return SUCCESS;
}
async command error_t AsyncStdControl.stop() {
atomic call HplAtm128Adc.disableAdc();
return SUCCESS;
}
/* Return TRUE if switching to 'channel' with reference voltage 'refVoltage'
will give a precise result (the first sample after changing reference
voltage or switching to/between a differential channel is imprecise)
*/
inline bool isPrecise(Atm128Admux_t admux, uint8_t channel, uint8_t refVoltage) {
return refVoltage == admux.refs &&
(channel <= ATM128_ADC_SNGL_ADC7 || channel >= ATM128_ADC_SNGL_1_23 || channel == admux.mux);
}
async event void HplAtm128Adc.dataReady(uint16_t data) {
bool precise, multiple;
uint8_t channel;
atomic
{
channel = f.channel;
precise = f.precise;
multiple = f.multiple;
}
if (!multiple)
{
/* A single sample. Disable the ADC interrupt to avoid starting
a new sample at the next "sleep" instruction. */
call HplAtm128Adc.disableInterruption();
signal Atm128AdcSingle.dataReady(data, precise);
}
else
{
/* Multiple sampling. The user can:
- tell us to stop sampling
- or, to continue sampling on a new channel, possibly with a
new reference voltage; however this change applies not to
the next sample (the hardware has already started working on
that), but on the one after.
*/
bool cont;
uint8_t nextChannel, nextVoltage;
Atm128Admux_t admux;
atomic
{
admux = call HplAtm128Adc.getAdmux();
nextVoltage = admux.refs;
nextChannel = admux.mux;
}
cont = signal Atm128AdcMultiple.dataReady(data, precise, channel,
&nextChannel, &nextVoltage);
atomic
if (cont)
{
/* Switch channels and update our internal channel+precision
tracking state (f and nextF). Note that this tracking will
be incorrect if we take too long to get to this point. */
admux.refs = nextVoltage;
admux.mux = nextChannel;
call HplAtm128Adc.setAdmux(admux);
f = nextF;
nextF.channel = nextChannel;
nextF.precise = isPrecise(admux, nextChannel, nextVoltage);
}
else
call HplAtm128Adc.cancel();
}
}
/* Start sampling based on request parameters */
void getData(uint8_t channel, uint8_t refVoltage, bool leftJustify, uint8_t prescaler) {
Atm128Admux_t admux;
Atm128Adcsra_t adcsr;
admux = call HplAtm128Adc.getAdmux();
f.precise = isPrecise(admux, channel, refVoltage);
f.channel = channel;
admux.refs = refVoltage;
admux.adlar = leftJustify;
admux.mux = channel;
call HplAtm128Adc.setAdmux(admux);
adcsr.aden = ATM128_ADC_ENABLE_ON;
adcsr.adsc = ATM128_ADC_START_CONVERSION_ON;
adcsr.adate= f.multiple;
adcsr.adif = ATM128_ADC_INT_FLAG_ON; // clear any stale flag
adcsr.adie = ATM128_ADC_INT_ENABLE_ON;
if (prescaler == ATM128_ADC_PRESCALE)
prescaler = call Atm128Calibrate.adcPrescaler();
adcsr.adps = prescaler;
call HplAtm128Adc.setAdcsra(adcsr);
}
async command bool Atm128AdcSingle.getData(uint8_t channel, uint8_t refVoltage,
bool leftJustify, uint8_t prescaler) {
atomic
{
f.multiple = FALSE;
getData(channel, refVoltage, leftJustify, prescaler);
return f.precise;
}
}
async command bool Atm128AdcSingle.cancel() {
/* There is no Atm128AdcMultiple.cancel, for reasons discussed in that
interface */
return call HplAtm128Adc.cancel();
}
async command bool Atm128AdcMultiple.getData(uint8_t channel, uint8_t refVoltage,
bool leftJustify, uint8_t prescaler) {
atomic
{
f.multiple = TRUE;
getData(channel, refVoltage, leftJustify, prescaler);
nextF = f;
/* We assume the 2nd sample is precise */
nextF.precise = TRUE;
return f.precise;
}
}
default async event void Atm128AdcSingle.dataReady(uint16_t data, bool precise) {
}
default async event bool Atm128AdcMultiple.dataReady(uint16_t data, bool precise, uint8_t channel,
uint8_t *newChannel, uint8_t *newRefVoltage) {
return FALSE; // stop conversion if we somehow end up here.
}
}
--- NEW FILE: HplAtm128AdcP.nc ---
/// $Id: HplAtm128AdcP.nc,v 1.1 2007/11/05 20:36:42 sallai Exp $
/*
* Copyright (c) 2004-2005 Crossbow Technology, Inc. All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO
* ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
* DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
* IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
* DAMAGE.
*
* CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
* OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
* MODIFICATIONS.
*/
/*
* Copyright (c) 2007, Vanderbilt University
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
* UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
*
*/
#include "Atm128Adc.h"
/**
* HPL for the Atmega1281 A/D conversion susbsystem.
*
* @author Martin Turon <mturon at xbow.com>
* @author Hu Siquan <husq at xbow.com>
* @author David Gay
* @author Janos Sallai <janos.sallai at vanderbilt.edu>
*/
module HplAtm128AdcP {
provides interface HplAtm128Adc;
uses interface McuPowerState;
}
implementation {
//=== Direct read of HW registers. =================================
async command Atm128Admux_t HplAtm128Adc.getAdmux() {
return *(Atm128Admux_t*)&ADMUX;
}
async command Atm128Adcsra_t HplAtm128Adc.getAdcsra() {
return *(Atm128Adcsra_t*)&ADCSRA;
}
async command uint16_t HplAtm128Adc.getValue() {
return ADC;
}
DEFINE_UNION_CAST(Admux2int, Atm128Admux_t, uint8_t);
DEFINE_UNION_CAST(Adcsra2int, Atm128Adcsra_t, uint8_t);
//=== Direct write of HW registers. ================================
async command void HplAtm128Adc.setAdmux( Atm128Admux_t x ) {
ADMUX = Admux2int(x);
}
async command void HplAtm128Adc.setAdcsra( Atm128Adcsra_t x ) {
ADCSRA = Adcsra2int(x);
}
async command void HplAtm128Adc.setPrescaler(uint8_t scale){
Atm128Adcsra_t current_val = call HplAtm128Adc.getAdcsra();
current_val.adif = FALSE;
current_val.adps = scale;
call HplAtm128Adc.setAdcsra(current_val);
}
// Individual bit manipulation. These all clear any pending A/D interrupt.
// It's not clear these are that useful...
async command void HplAtm128Adc.enableAdc() {
SET_BIT(ADCSRA, ADEN);
call McuPowerState.update();
}
async command void HplAtm128Adc.disableAdc() {
CLR_BIT(ADCSRA, ADEN);
call McuPowerState.update();
}
async command void HplAtm128Adc.enableInterruption() { SET_BIT(ADCSRA, ADIE); }
async command void HplAtm128Adc.disableInterruption() { CLR_BIT(ADCSRA, ADIE); }
async command void HplAtm128Adc.setContinuous() {
((Atm128Adcsrb_t*)&ADCSRB)->adts = 0;
SET_BIT(ADCSRA, ADATE);
}
async command void HplAtm128Adc.setSingle() { CLR_BIT(ADCSRA, ADATE); }
async command void HplAtm128Adc.resetInterrupt() { SET_BIT(ADCSRA, ADIF); }
async command void HplAtm128Adc.startConversion() { SET_BIT(ADCSRA, ADSC); }
/* A/D status checks */
async command bool HplAtm128Adc.isEnabled() {
return (call HplAtm128Adc.getAdcsra()).aden;
}
async command bool HplAtm128Adc.isStarted() {
return (call HplAtm128Adc.getAdcsra()).adsc;
}
async command bool HplAtm128Adc.isComplete() {
return (call HplAtm128Adc.getAdcsra()).adif;
}
/* A/D interrupt handlers. Signals dataReady event with interrupts enabled */
AVR_ATOMIC_HANDLER(SIG_ADC) {
uint16_t data = call HplAtm128Adc.getValue();
__nesc_enable_interrupt();
signal HplAtm128Adc.dataReady(data);
}
default async event void HplAtm128Adc.dataReady(uint16_t done) { }
async command bool HplAtm128Adc.cancel() {
/* This is tricky */
atomic
{
Atm128Adcsra_t oldSr = call HplAtm128Adc.getAdcsra(), newSr;
/* To cancel a conversion, first turn off ADEN, then turn off
ADSC. We also cancel any pending interrupt.
Finally we reenable the ADC.
*/
newSr = oldSr;
newSr.aden = FALSE;
newSr.adif = TRUE; /* This clears a pending interrupt... */
newSr.adie = FALSE; /* We don't want to start sampling again at the
next sleep */
call HplAtm128Adc.setAdcsra(newSr);
newSr.adsc = FALSE;
call HplAtm128Adc.setAdcsra(newSr);
newSr.aden = TRUE;
call HplAtm128Adc.setAdcsra(newSr);
return oldSr.adif || oldSr.adsc;
}
}
}
- Previous message: [Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281
HplAtm128UartP.nc, NONE, 1.1 McuSleepC.nc, NONE,
1.1 atm128hardware.h, NONE, 1.1
- Next message: [Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281/timer
Atm1281AlarmAsyncP.nc, NONE, 1.1 Atm128AlarmAsyncC.nc, NONE,
1.1 Atm128Timer.h, NONE, 1.1 HplAtm1281Timer1P.nc, NONE,
1.1 HplAtm1281Timer2AsyncC.nc, NONE,
1.1 HplAtm1281Timer2AsyncP.nc, NONE, 1.1 HplAtm1281Timer3P.nc,
NONE, 1.1 HplAtm128Timer1C.nc, NONE, 1.1 HplAtm128Timer3C.nc,
NONE, 1.1 HplAtm128TimerAsync.nc, NONE,
1.1 HplAtm128TimerCtrl16.nc, NONE, 1.1 HplAtm128TimerCtrl8.nc,
NONE, 1.1
- Messages sorted by:
[ date ]
[ thread ]
[ subject ]
[ author ]
More information about the Tinyos-2-commits
mailing list