[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm1281/timer Atm1281AlarmAsyncP.nc, NONE, 1.1 Atm128AlarmAsyncC.nc, NONE, 1.1 Atm128Timer.h, NONE, 1.1 HplAtm1281Timer1P.nc, NONE, 1.1 HplAtm1281Timer2AsyncC.nc, NONE, 1.1 HplAtm1281Timer2AsyncP.nc, NONE, 1.1 HplAtm1281Timer3P.nc, NONE, 1.1 HplAtm128Timer1C.nc, NONE, 1.1 HplAtm128Timer3C.nc, NONE, 1.1 HplAtm128TimerAsync.nc, NONE, 1.1 HplAtm128TimerCtrl16.nc, NONE, 1.1 HplAtm128TimerCtrl8.nc, NONE, 1.1

[Janos Sallai]

Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/atm1281/timer
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv27101/atm1281/timer

Added Files:
	Atm1281AlarmAsyncP.nc Atm128AlarmAsyncC.nc Atm128Timer.h 
	HplAtm1281Timer1P.nc HplAtm1281Timer2AsyncC.nc 
	HplAtm1281Timer2AsyncP.nc HplAtm1281Timer3P.nc 
	HplAtm128Timer1C.nc HplAtm128Timer3C.nc HplAtm128TimerAsync.nc 
	HplAtm128TimerCtrl16.nc HplAtm128TimerCtrl8.nc 
Log Message:
platform support for the IRIS mote (atm1218 MCU and rf230 radio)

--- NEW FILE: Atm1281AlarmAsyncP.nc ---
// $Id: Atm1281AlarmAsyncP.nc,v 1.1 2007/11/05 20:36:42 sallai Exp $
/*
 * Copyright (c) 2007 Intel Corporation
 * All rights reserved.
 *
 * This file is distributed under the terms in the attached INTEL-LICENSE     
 * file. If you do not find these files, copies can be found by writing to
 * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, 
 * 94704.  Attention:  Intel License Inquiry.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */
  
/**
 * Build a 32-bit alarm and counter from the atmega1281's 8-bit timer 2
 * in asynchronous mode. Attempting to use the generic Atm128AlarmC
 * component and the generic timer components runs into problems
 * apparently related to letting timer 2 overflow.
 * 
 * So, instead, this version (inspired by the 1.x code and a remark from
 * Martin Turon) directly builds a 32-bit alarm and counter on top of timer 2
 * and never lets timer 2 overflow.
 *
 * @author David Gay
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */
generic module Atm1281AlarmAsyncP(typedef precision, int divider) {
  provides {
    interface Init;
    interface Alarm<precision, uint32_t>;
    interface Counter<precision, uint32_t>;
  }
  uses {
    interface HplAtm128Timer<uint8_t> as Timer;
    interface HplAtm128TimerCtrl8 as TimerCtrl;
    interface HplAtm128Compare<uint8_t> as Compare;
    interface HplAtm128TimerAsync as TimerAsync;
  }
}
implementation
{
  uint8_t set; 			/* Is the alarm set? */
  uint32_t t0, dt;		/* Time of the next alarm */
  norace uint32_t base;		/* base+TCNT2 is the current time if no
				   interrupt is pending. See Counter.get()
				   for the full details. */

  enum {
    MINDT = 2,			/* Minimum interval between interrupts */
    MAXT = 230			/* Maximum value to let timer 2 reach
				   (from Joe Polastre and Robert Szewczyk's
				   painful experiences with the 1.x timer ;-)) */
  };

  void setInterrupt();

  /* Configure timer 2 */
  command error_t Init.init() {
    atomic
      {
	Atm128_TCCR2A_t x;
	Atm128_TCCR2B_t y;
    
	call TimerAsync.setTimer2Asynchronous();
	x.flat = 0;
	x.bits.wgm21 = 1; /* We use the clear-on-compare mode */
	call TimerCtrl.setControlA(x.flat);
	y.flat = 0;
	y.bits.cs = divider;
	call TimerCtrl.setControlB(y.flat);
	call Compare.set(MAXT); /* setInterrupt needs a valid value here */
	call Compare.start();
      }
    setInterrupt();
    return SUCCESS;
  }

  /* Set compare register for timer 2 to n. But increment n by 1 if TCNT2 
     reaches this value before we can set the compare register.
  */
  void setOcr2A(uint8_t n) {
    while (call TimerAsync.compareABusy())
      ;
    if (n == call Timer.get())
      n++;
    /* Support for overflow. Force interrupt at wrap around value. 
       This does not cause a backwards-in-time value as we do this
       every time we set OCR2A. */
    if (base + n + 1 < base)
      n = -base - 1;
    call Compare.set(n);
  }

  /* Update the compare register to trigger an interrupt at the
     appropriate time based on the current alarm settings
   */
  void setInterrupt() {
    bool fired = FALSE;

    atomic
      {
	/* interrupt_in is the time to the next interrupt. Note that
	   compare register values are off by 1 (i.e., if you set OCR2A to
	   3, the interrupt will happen when TCNT2 is 4) */
	uint8_t interrupt_in = 1 + call Compare.get() - call Timer.get();
	uint8_t newOcr2A;
	uint8_t tifr2 = call TimerCtrl.getInterruptFlag();
	dbg("Atm1281AlarmAsyncP", "Atm1281AlarmAsyncP: TIFR is %hhx\n", tifr2);
	if ((interrupt_in != 0 && interrupt_in < MINDT) || (tifr2 & (1 << OCF2A))) {
	  if (interrupt_in < MINDT) {
	    dbg("Atm1281AlarmAsyncP", "Atm1281AlarmAsyncP: under min: %hhu.\n", interrupt_in);
	  }
	  else {
	    dbg("Atm1281AlarmAsyncP", "Atm1281AlarmAsyncP: OCF2A set.\n");
	  }
	  return; // wait for next interrupt
	}

	/* When no alarm is set, we just ask for an interrupt every MAXT */
	if (!set) {
	  newOcr2A = MAXT;
	  dbg("Atm1281AlarmAsyncP", "Atm1281AlarmAsyncP: no alarm set, set at max.\n");
	}
	else
	  {
	    uint32_t now = call Counter.get();
	    dbg("Atm1281AlarmAsyncP", "Atm1281AlarmAsyncP: now-t0 = %llu, dt = %llu\n", (now-t0), dt);
	    /* Check if alarm expired */
	    if ((uint32_t)(now - t0) >= dt)
	      {
		set = FALSE;
		fired = TRUE;
		newOcr2A = MAXT;
	      }
	    else
	      {
		/* No. Set compare register to time of next alarm if it's
		   within the next MAXT units */
		uint32_t alarm_in = (t0 + dt) - base;

		if (alarm_in > MAXT)
		  newOcr2A = MAXT;
		else if ((uint8_t)alarm_in < MINDT) // alarm_in < MAXT ...
		  newOcr2A = MINDT;
		else
		  newOcr2A = alarm_in;
	      }
	  }
	newOcr2A--; // interrupt is 1ms late
	setOcr2A(newOcr2A);
      }
    if (fired)
      signal Alarm.fired();
  }

  async event void Compare.fired() {
    int overflowed;

    /* Compare register fired. Update time knowledge */
    base += call Compare.get() + 1U; // interrupt is 1ms late
    overflowed = !base;
    __nesc_enable_interrupt();
    setInterrupt();
    if (overflowed)
      signal Counter.overflow();
  }  

  async command uint32_t Counter.get() {
    uint32_t now;

    atomic
      {
	/* Current time is base+TCNT2 if no interrupt is pending. But if
	   an interrupt is pending, then it's base + compare value + 1 + TCNT2 */
	uint8_t now8 = call Timer.get();

	if ((((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag())).bits.ocfa)
	  /* We need to reread TCNT2 as it might've overflowed after we
	     read TCNT2 the first time */
	  now = base + call Compare.get() + 1 + call Timer.get();
	else
	  /* We need to use the value of TCNT2 from before we check the
	     interrupt flag, as it might wrap around after the check */
	  now = base + now8;
      }
    return now;
  }

  async command bool Counter.isOverflowPending() {
    atomic
      return (((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag())).bits.ocfa &&
	!(base + call Compare.get() + 1);
  }

  async command void Counter.clearOverflow() { 
    atomic
      if (call Counter.isOverflowPending())
	{
	  base = 0;
	  call Compare.reset();
	}
      else
	return;
    setInterrupt();
  }

  async command void Alarm.start(uint32_t ndt) {
    call Alarm.startAt(call Counter.get(), ndt);
  }

  async command void Alarm.stop() {
    atomic set = FALSE;
  }

  async command bool Alarm.isRunning() {
    atomic return set;
  }

  async command void Alarm.startAt(uint32_t nt0, uint32_t ndt) {
    atomic
      {
	set = TRUE;
	t0 = nt0;
	dt = ndt;
      }
    setInterrupt();
  }

  async command uint32_t Alarm.getNow() {
    return call Counter.get();
  }

  async command uint32_t Alarm.getAlarm() {
    atomic return t0 + dt;
  }

  async event void Timer.overflow() { }
}

--- NEW FILE: Atm128AlarmAsyncC.nc ---
// $Id: Atm128AlarmAsyncC.nc,v 1.1 2007/11/05 20:36:42 sallai Exp $
/*
 * Copyright (c) 2007 Intel Corporation
 * All rights reserved.
 *
 * This file is distributed under the terms in the attached INTEL-LICENSE     
 * file. If you do not find these files, copies can be found by writing to
 * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, 
 * 94704.  Attention:  Intel License Inquiry.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */
 
/**
 * Build a 32-bit alarm and counter from the atmega1281's 8-bit timer 2
 * in asynchronous mode. Attempting to use the generic Atm128AlarmC
 * component and the generic timer components runs into problems
 * apparently related to letting timer 2 overflow.
 * 
 * So, instead, this version (inspired by the 1.x code and a remark from
 * Martin Turon) directly builds a 32-bit alarm and counter on top of timer 2
 * and never lets timer 2 overflow.
 *
 * @author David Gay
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */
generic configuration Atm128AlarmAsyncC(typedef precision, int divider) {
  provides {
    interface Init @atleastonce();
    interface Alarm<precision, uint32_t>;
    interface Counter<precision, uint32_t>;
  }
}
implementation
{
  components new Atm1281AlarmAsyncP(precision, divider),
    HplAtm1281Timer2AsyncC;

  Init = Atm1281AlarmAsyncP;
  Alarm = Atm1281AlarmAsyncP;
  Counter = Atm1281AlarmAsyncP;

  Atm1281AlarmAsyncP.Timer -> HplAtm1281Timer2AsyncC;
  Atm1281AlarmAsyncP.TimerCtrl -> HplAtm1281Timer2AsyncC;
  Atm1281AlarmAsyncP.Compare -> HplAtm1281Timer2AsyncC;
  Atm1281AlarmAsyncP.TimerAsync -> HplAtm1281Timer2AsyncC;
}

--- NEW FILE: Atm128Timer.h ---
// $Id: Atm128Timer.h,v 1.1 2007/11/05 20:36:42 sallai Exp $

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */


/*
 * This file contains the configuration constants for the Atmega1281
 * clocks and timers.
 *
 * @author Philip Levis
 * @author Martin Turon
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#ifndef _H_Atm128Timer_h
#define _H_Atm128Timer_h

/* Prescaler values for Timer/Counter 2 (8-bit asynchronous ) */
enum {
  ATM128_CLK8_OFF         = 0x0,
  ATM128_CLK8_NORMAL      = 0x1,
  ATM128_CLK8_DIVIDE_8    = 0x2,
  ATM128_CLK8_DIVIDE_32   = 0x3,
  ATM128_CLK8_DIVIDE_64   = 0x4,
  ATM128_CLK8_DIVIDE_128  = 0x5,
  ATM128_CLK8_DIVIDE_256  = 0x6,
  ATM128_CLK8_DIVIDE_1024 = 0x7,
};

/* Prescaler values for Timer/Counter 0 (8-bit) and 1, 3, 4, 5 (16-bit) */
enum {
  ATM128_CLK16_OFF           = 0x0,
  ATM128_CLK16_NORMAL        = 0x1,
  ATM128_CLK16_DIVIDE_8      = 0x2,
  ATM128_CLK16_DIVIDE_64     = 0x3,
  ATM128_CLK16_DIVIDE_256    = 0x4,
  ATM128_CLK16_DIVIDE_1024   = 0x5,
  ATM128_CLK16_EXTERNAL_FALL = 0x6,
  ATM128_CLK16_EXTERNAL_RISE = 0x7,
};

/* Common scales across both 8-bit and 16-bit clocks. */
enum {
    AVR_CLOCK_OFF = 0,
    AVR_CLOCK_ON  = 1,
    AVR_CLOCK_DIVIDE_8 = 2,
};

enum {
    ATM128_TIMER_COMPARE_NORMAL = 0,
    ATM128_TIMER_COMPARE_TOGGLE,
    ATM128_TIMER_COMPARE_CLEAR,
    ATM128_TIMER_COMPARE_SET
};


/* 8-bit Waveform Generation Modes */
enum {
    ATM128_WAVE8_NORMAL = 0,
    ATM128_WAVE8_PWM,
    ATM128_WAVE8_CTC,
    ATM128_WAVE8_PWM_FAST,
};

/* 16-bit Waveform Generation Modes */
enum {
    ATM128_WAVE16_NORMAL = 0,
    ATM128_WAVE16_PWM_8BIT,
    ATM128_WAVE16_PWM_9BIT,
    ATM128_WAVE16_PWM_10BIT,
    ATM128_WAVE16_CTC_COMPARE,
    ATM128_WAVE16_PWM_FAST_8BIT,
    ATM128_WAVE16_PWM_FAST_9BIT,
    ATM128_WAVE16_PWM_FAST_10BIT,
    ATM128_WAVE16_PWM_CAPTURE_LOW,
    ATM128_WAVE16_PWM_COMPARE_LOW,
    ATM128_WAVE16_PWM_CAPTURE_HIGH,
    ATM128_WAVE16_PWM_COMPARE_HIGH,
    ATM128_WAVE16_CTC_CAPTURE,
    ATM128_WAVE16_RESERVED,
    ATM128_WAVE16_PWM_FAST_CAPTURE,
    ATM128_WAVE16_PWM_FAST_COMPARE,
};

/* 8-bit Timer compare settings */
enum {
    ATM128_COMPARE_OFF = 0,  //!< compare disconnected
    ATM128_COMPARE_TOGGLE,   //!< toggle on match (PWM reserved
    ATM128_COMPARE_CLEAR,    //!< clear on match  (PWM downcount)
    ATM128_COMPARE_SET,      //!< set on match    (PWN upcount)
};

/* 8-bit Timer/Counter 0 Control Register A*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t wgm00 : 1;  //!< Waveform generation mode (low bit)
    uint8_t wgm01 : 1;  //!< Waveform generation mode (high bit)
    uint8_t resv1 : 2;  //!< Compare Match Output
    uint8_t com0b0: 1;  //!< Compare Match Output
    uint8_t com0b1: 1;  //!< Compare Match Output
    uint8_t com0a0: 1;  //!< Compare Match Output
    uint8_t com0a1: 1;  //!< Compare Match Output
  } bits;
} Atm128_TCCR0A_t;

/* 8-bit Timer/Counter 0 Control Register B*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t cs00  : 1;  //!< Clock Select 0
    uint8_t cs01  : 1;  //!< Clock Select 1
    uint8_t cs02  : 2;  //!< Clock Select 2
    uint8_t wgm02 : 1;  //!< Waveform Generation Mode
    uint8_t resv1 : 2;  //!< Reserved
    uint8_t foc0b : 1;  //!< Force Output Compare B
    uint8_t foc0a : 1;  //!< Force Output Compare A
  } bits;
} Atm128_TCCR0B_t;

/* Timer/Counter 0 Interrupt Mask Register */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t toie0 : 1; //!< Timer/Counter0 Overflow Interrupt Enable
    uint8_t ocie0a: 1; //!< Timer/Counter0 Output Compare Match A Interrupt Enable
    uint8_t ocie0e: 1; //!< Timer/Counter Output Compare Match B Interrupt Enable
    uint8_t resv1 : 5; //!< Reserved
  } bits;
} Atm128_TIMSK0_t;

/* Timer/Counter 0 Interrupt Flag Register*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t tov0  : 1; //!< Timer/Counter0 Overflow Flag
    uint8_t ocf0a : 1; //!< Timer/Counter 0 Output Compare A Match Flag
    uint8_t ocf0b : 1; //!< Timer/Counter 0 Output Compare B Match Flag
    uint8_t resv1 : 5; //!< Reserved
  } bits;
} Atm128_TIFR0_t;

/* Asynchronous Status Register -- Timer2 */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t tcr2bub: 1;  //!< Timer/Counter Control Register2 Update Busy
    uint8_t tcr2aub: 1;  //!< Timer/Counter Control Register2 Update Busy
    uint8_t ocr2bub: 1;  //!< Output Compare Register2 Update Busy
    uint8_t ocr2aub: 1;  //!< Output Compare Register2 Update Busy
    uint8_t tcn2ub : 1;  //!< Timer/Counter2 Update Busy
    uint8_t as2    : 1;  //!< Asynchronous Timer/Counter2 (off=CLK_IO,on=TOSC1)
    uint8_t exclk  : 1;  //!< Enable External Clock Input
    uint8_t resv1  : 1;  //!< Reserved
  } bits;
} Atm128_ASSR_t;

/* Timer/Counter 2 Control Register A*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t wgm20 : 1; //!< Waveform Generation Mode
    uint8_t wgm21 : 1; //!< Waveform Generation Mode
    uint8_t resv1 : 2; //!< Reserved
    uint8_t comb: 2; //!< Compare Output Mode for Channel B
    uint8_t coma: 2; //!< Compare Output Mode for Channel A
  } bits;
} Atm128_TCCR2A_t;

/* Timer/Counter 2 Control Register B*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t cs    : 3; //!< Clock Select
    uint8_t wgm22 : 1; //!< Waveform Generation Mode
    uint8_t resv1 : 2; //!< Reserved
    uint8_t foc2b : 1; //!< Force Output Compare B
    uint8_t foc2a : 1; //!< Force Output Compare A
  } bits;
} Atm128_TCCR2B_t;

/* Timer/Counter 2 Interrupt Mask Register */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t toie : 1; //!< Timer/Counter2 Overflow Interrupt Enable
    uint8_t ociea: 1; //!< Timer/Counter2 Output Compare Match A Interrupt Enable
    uint8_t ocieb: 1; //!< Timer/Counter Output Compare Match B Interrupt Enable
    uint8_t resv1 : 5; //!< Reserved
  } bits;
} Atm128_TIMSK2_t;

/* Timer/Counter 2 Interrupt Flag Register */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t tov  : 1; //!< Timer1 Overflow Flag
    uint8_t ocfa : 1; //!< Timer1 Output Compare Flag A
    uint8_t ocfb : 1; //!< Timer1 Output Compare Flag B
    uint8_t resv1 : 5; //!< Reserved
  } bits;
} Atm128_TIFR2_t;


/* Timer/Counter 1,3,4,5 Control Register A*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t wgm01  : 2; //!< Waveform Generation Mode
    uint8_t comc   : 2; //!< Compare Output Mode for Channel C
    uint8_t comb   : 2; //!< Compare Output Mode for Channel B
    uint8_t coma   : 2; //!< Compare Output Mode for Channel A
  } bits;
} Atm128_TCCRA_t;

/* Timer/Counter 1,3,4,5 Control Register B*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t cs    : 3; //!< Clock Select
    uint8_t wgm23 : 2; //!< Waveform Generation Mode
    uint8_t resv1 : 1; //!< Reserved
    uint8_t ices  : 1; //!< Input Capture Edge Select
    uint8_t icnc  : 1; //!< Input Capture Noise Canceler
  } bits;
} Atm128_TCCRB_t;

/* Timer/Counter 1,3,4,5 Control Register C*/
typedef union
{
  uint8_t flat;
  struct {
    uint8_t resv1 : 5; //!< Reserved
    uint8_t focc : 1; //!< Force Output Compare for Channel A
    uint8_t focb : 1; //!< Force Output Compare for Channel A
    uint8_t foca : 1; //!< Force Output Compare for Channel A
  } bits;
} Atm128_TCCRC_t;

/* Timer/Counter 1,3,4,5 Interrupt Mask Register */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t toie : 1; //!< Timer/Counter1 Overflow Interrupt Enable
    uint8_t ociea: 1; //!< Timer/Counter1 Output Compare Match A Interrupt Enable
    uint8_t ocieb: 1; //!< Timer/Counter1 Output Compare Match B Interrupt Enable
    uint8_t ociec: 1; //!< Timer/Counter1 Output Compare Match C Interrupt Enable
    uint8_t resv1: 1; //!< Reserved
    uint8_t icie : 1; //!< Timer/Counter1, Input Capture Interrupt Enable
    uint8_t resv2 : 2; //!< Reserved
  } bits;
} Atm128_TIMSK_t;

/* Timer/Counter 1,3,4,5 Interrupt Flag Register */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t tov  : 1; //!< Timer1 Overflow Flag
    uint8_t ocfa : 1; //!< Timer1 Output Compare Flag A
    uint8_t ocfb : 1; //!< Timer1 Output Compare Flag B
    uint8_t ocfc : 1; //!< Timer1 Output Compare Flag C
    uint8_t resv1: 1; //!< Reserved
    uint8_t icf  : 1; //!< Timer1 Input Capture Flag 
    uint8_t resv2: 2; //!< Reserved
  } bits;
} Atm128_TIFR_t;

/* General Timer/Counter Control Register */
typedef union
{
  uint8_t flat;
  struct {
    uint8_t psrsync: 1; //!< Prescaler Reset for Synchronous Timer/Counters 0,1,3,4,5
    uint8_t psrasy : 1; //!< Prescaler Reset Timer/Counter2
    uint8_t resv1  : 5; //!< Reserved
    uint8_t tsm    : 1; //!< Timer/Counter Synchronization Mode
  } bits;
} Atm128_GTCCR_t;

// Read/Write these 16-bit Timer registers
// Access as bytes.  Read low before high.  Write high before low. 
typedef uint8_t Atm128_TCNT1H_t;  //!< Timer1 Register
typedef uint8_t Atm128_TCNT1L_t;  //!< Timer1 Register
typedef uint8_t Atm128_TCNT3H_t;  //!< Timer3 Register
typedef uint8_t Atm128_TCNT3L_t;  //!< Timer3 Register
typedef uint8_t Atm128_TCNT4H_t;  //!< Timer4 Register
typedef uint8_t Atm128_TCNT4L_t;  //!< Timer4 Register
typedef uint8_t Atm128_TCNT5H_t;  //!< Timer5 Register
typedef uint8_t Atm128_TCNT5L_t;  //!< Timer5 Register

/* Contains value to continuously compare with Timer1 */
typedef uint8_t Atm128_OCR1AH_t;  //!< Output Compare Register 1A
typedef uint8_t Atm128_OCR1AL_t;  //!< Output Compare Register 1A
typedef uint8_t Atm128_OCR1BH_t;  //!< Output Compare Register 1B
typedef uint8_t Atm128_OCR1BL_t;  //!< Output Compare Register 1B
typedef uint8_t Atm128_OCR1CH_t;  //!< Output Compare Register 1C
typedef uint8_t Atm128_OCR1CL_t;  //!< Output Compare Register 1C

/* Contains value to continuously compare with Timer3 */
typedef uint8_t Atm128_OCR3AH_t;  //!< Output Compare Register 3A
typedef uint8_t Atm128_OCR3AL_t;  //!< Output Compare Register 3A
typedef uint8_t Atm128_OCR3BH_t;  //!< Output Compare Register 3B
typedef uint8_t Atm128_OCR3BL_t;  //!< Output Compare Register 3B
typedef uint8_t Atm128_OCR3CH_t;  //!< Output Compare Register 3C
typedef uint8_t Atm128_OCR3CL_t;  //!< Output Compare Register 3C

/* Contains value to continuously compare with Timer4 */
typedef uint8_t Atm128_OCR4AH_t;  //!< Output Compare Register 4A
typedef uint8_t Atm128_OCR4AL_t;  //!< Output Compare Register 4A
typedef uint8_t Atm128_OCR4BH_t;  //!< Output Compare Register 4B
typedef uint8_t Atm128_OCR4BL_t;  //!< Output Compare Register 4B
typedef uint8_t Atm128_OCR4CH_t;  //!< Output Compare Register 4C
typedef uint8_t Atm128_OCR4CL_t;  //!< Output Compare Register 4C

/* Contains value to continuously compare with Timer5 */
typedef uint8_t Atm128_OCR5AH_t;  //!< Output Compare Register 5A
typedef uint8_t Atm128_OCR5AL_t;  //!< Output Compare Register 5A
typedef uint8_t Atm128_OCR5BH_t;  //!< Output Compare Register 5B
typedef uint8_t Atm128_OCR5BL_t;  //!< Output Compare Register 5B
typedef uint8_t Atm128_OCR5CH_t;  //!< Output Compare Register 5C
typedef uint8_t Atm128_OCR5CL_t;  //!< Output Compare Register 5C

/* Contains counter value when event occurs on ICPn pin. */
typedef uint8_t Atm128_ICR1H_t;  //!< Input Capture Register 1
typedef uint8_t Atm128_ICR1L_t;  //!< Input Capture Register 1
typedef uint8_t Atm128_ICR3H_t;  //!< Input Capture Register 3
typedef uint8_t Atm128_ICR3L_t;  //!< Input Capture Register 3
typedef uint8_t Atm128_ICR4H_t;  //!< Input Capture Register 4
typedef uint8_t Atm128_ICR4L_t;  //!< Input Capture Register 4
typedef uint8_t Atm128_ICR5H_t;  //!< Input Capture Register 5
typedef uint8_t Atm128_ICR5L_t;  //!< Input Capture Register 5

/* Resource strings for timer 1 and 3 compare registers */
#define UQ_TIMER1_COMPARE "atm128.timer1"
#define UQ_TIMER3_COMPARE "atm128.timer3" 

#endif //_H_Atm128Timer_h


--- NEW FILE: HplAtm1281Timer1P.nc ---

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * Internal component of the HPL interface to Atmega1281 timer 1.
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#include <Atm128Timer.h>

module HplAtm1281Timer1P
{
  provides {
    // 16-bit Timers
    interface HplAtm128Timer<uint16_t>   as Timer;
    interface HplAtm128TimerCtrl16       as TimerCtrl;
    interface HplAtm128Capture<uint16_t> as Capture;
    interface HplAtm128Compare<uint16_t> as CompareA;
    interface HplAtm128Compare<uint16_t> as CompareB;
    interface HplAtm128Compare<uint16_t> as CompareC;
  }
}
implementation
{
  //=== Read the current timer value. ===================================
  async command uint16_t Timer.get() { return TCNT1; }

  //=== Set/clear the current timer value. ==============================
  async command void Timer.set(uint16_t t) { TCNT1 = t; }

  //=== Read the current timer scale. ===================================
  async command uint8_t Timer.getScale() { return TCCR1B & 0x7; }

  //=== Turn off the timers. ============================================
  async command void Timer.off() { call Timer.setScale(AVR_CLOCK_OFF); }

  //=== Write a new timer scale. ========================================
  async command void Timer.setScale(uint8_t s)  { 
    Atm128_TCCRB_t x = (Atm128_TCCRB_t) call TimerCtrl.getControlB();
    x.bits.cs = s;
    call TimerCtrl.setControlB(x.flat);  
  }

  //=== Read the control registers. =====================================
  async command uint8_t TimerCtrl.getControlA() { 
    return TCCR1A; 
  }

  async command uint8_t TimerCtrl.getControlB() { 
    return TCCR1B; 
  }

  async command uint8_t TimerCtrl.getControlC() { 
    return TCCR1C; 
  }

  //=== Write the control registers. ====================================
  async command void TimerCtrl.setControlA( uint8_t x ) { 
    TCCR1A = x; 
  }

  async command void TimerCtrl.setControlB( uint8_t x ) { 
    TCCR1B = x; 
  }

  async command void TimerCtrl.setControlC( uint8_t x ) { 
    TCCR1C = x; 
  }

  //=== Read the interrupt mask. =====================================
  async command uint8_t TimerCtrl.getInterruptMask() { 
    return TIMSK1; 
  }

  //=== Write the interrupt mask. ====================================
  async command void TimerCtrl.setInterruptMask( uint8_t x ) { 
    TIMSK1 = x; 
  }

  //=== Read the interrupt flags. =====================================
  async command uint8_t TimerCtrl.getInterruptFlag() { 
    return TIFR1; 
  }

  //=== Write the interrupt flags. ====================================
  async command void TimerCtrl.setInterruptFlag( uint8_t x ) { 
    TIFR1 = x; 
  }

  //=== Capture 16-bit implementation. ===================================
  async command void Capture.setEdge(bool up) { WRITE_BIT(TCCR1B,ICES1, up); }

  //=== Timer 16-bit implementation. ===================================
  async command void Timer.reset()    { TIFR1 = 1 << TOV1; }
  async command void Capture.reset()  { TIFR1 = 1 << ICF1; }
  async command void CompareA.reset() { TIFR1 = 1 << OCF1A; }
  async command void CompareB.reset() { TIFR1 = 1 << OCF1B; }
  async command void CompareC.reset() { TIFR1 = 1 << OCF1C; }

  async command void Timer.start()    { SET_BIT(TIMSK1,TOIE1); }
  async command void Capture.start()  { SET_BIT(TIMSK1,ICIE1); }
  async command void CompareA.start() { SET_BIT(TIMSK1,OCIE1A); }
  async command void CompareB.start() { SET_BIT(TIMSK1,OCIE1B); }
  async command void CompareC.start() { SET_BIT(TIMSK1,OCIE1C); }

  async command void Timer.stop()    { CLR_BIT(TIMSK1,TOIE1); }
  async command void Capture.stop()  { CLR_BIT(TIMSK1,ICIE1); }
  async command void CompareA.stop() { CLR_BIT(TIMSK1,OCIE1A); }
  async command void CompareB.stop() { CLR_BIT(TIMSK1,OCIE1B); }
  async command void CompareC.stop() { CLR_BIT(TIMSK1,OCIE1C); }

  async command bool Timer.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.tov; 
  }
  async command bool Capture.test()  { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.icf; 
  }
  async command bool CompareA.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; 
  }
  async command bool CompareB.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfb; 
  }
  async command bool CompareC.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfc; 
  }

  async command bool Timer.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.toie;
  }
  async command bool Capture.isOn()  {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.icie;
  }
  async command bool CompareA.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.ociea;
  }
  async command bool CompareB.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.ocieb;
  }
  async command bool CompareC.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.ociec;
  }

  //=== Read the compare registers. =====================================
  async command uint16_t CompareA.get() { return OCR1A; }
  async command uint16_t CompareB.get() { return OCR1B; }
  async command uint16_t CompareC.get() { return OCR1C; }

  //=== Write the compare registers. ====================================
  async command void CompareA.set(uint16_t t) { OCR1A = t; }
  async command void CompareB.set(uint16_t t) { OCR1B = t; }
  async command void CompareC.set(uint16_t t) { OCR1C = t; }

  //=== Read the capture registers. =====================================
  async command uint16_t Capture.get() { return ICR1; }

  //=== Write the capture registers. ====================================
  async command void Capture.set(uint16_t t)  { ICR1 = t; }

  //=== Timer interrupts signals ========================================
  default async event void CompareA.fired() { }
  AVR_NONATOMIC_HANDLER(SIG_OUTPUT_COMPARE1A) {
    signal CompareA.fired();
  }
  default async event void CompareB.fired() { }
  AVR_NONATOMIC_HANDLER(SIG_OUTPUT_COMPARE1B) {
    signal CompareB.fired();
  }
  default async event void CompareC.fired() { }
  AVR_NONATOMIC_HANDLER(SIG_OUTPUT_COMPARE1C) {
    signal CompareC.fired();
  }
  default async event void Capture.captured(uint16_t time) { }
  AVR_NONATOMIC_HANDLER(SIG_INPUT_CAPTURE1) {
    signal Capture.captured(call Timer.get());
  }
  default async event void Timer.overflow() { }
  AVR_NONATOMIC_HANDLER(SIG_OVERFLOW1) {
    signal Timer.overflow();
  }
}

--- NEW FILE: HplAtm1281Timer2AsyncC.nc ---
/// $Id: HplAtm1281Timer2AsyncC.nc,v 1.1 2007/11/05 20:36:43 sallai Exp $
/*
 * Copyright (c) 2006 Stanford University.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the
 *   distribution.
 * - Neither the name of the Stanford University nor the names of
 *   its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL STANFORD
 * UNIVERSITY OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 * OF THE POSSIBILITY OF SUCH DAMAGE.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * Simple wrapper around the actual timer implementation that automatically
 * wires it to McuSleepC for low-power calculations..
 *
 * @author Philip Levis
 * @author David Gay
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#include <Atm128Timer.h>

configuration HplAtm1281Timer2AsyncC
{
  provides {
    // 8-bit Timers
    interface HplAtm128Timer<uint8_t>   as Timer;
    interface HplAtm128TimerCtrl8       as TimerCtrl;
    interface HplAtm128Compare<uint8_t> as Compare;
    interface HplAtm128TimerAsync       as TimerAsync;
  }
}
implementation
{
  components HplAtm1281Timer2AsyncP;
  components McuSleepC;

  McuSleepC.McuPowerOverride -> HplAtm1281Timer2AsyncP;

  Timer = HplAtm1281Timer2AsyncP;
  TimerCtrl = HplAtm1281Timer2AsyncP;
  Compare = HplAtm1281Timer2AsyncP;
  TimerAsync = HplAtm1281Timer2AsyncP;
}

--- NEW FILE: HplAtm1281Timer2AsyncP.nc ---
/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * HPL interface to Atmega1281 timer 2 in ASYNC mode. This is a specialised
 * HPL component that assumes that timer 2 is used in ASYNC mode and
 * includes some workarounds for some of the weirdnesses (delayed overflow
 * interrupt) of that mode.
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author David Gay <dgay at intel-research.net>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#include <Atm128Timer.h>

module HplAtm1281Timer2AsyncP
{
  provides {
    // 8-bit Timers
    interface HplAtm128Timer<uint8_t>   as Timer;
    interface HplAtm128TimerCtrl8       as TimerCtrl;
    interface HplAtm128Compare<uint8_t> as Compare;
    interface McuPowerOverride;
    interface HplAtm128TimerAsync       as TimerAsync;
  }
}
implementation
{
//  bool inOverflow;

//  command error_t Init.init() {
//    SET_BIT(ASSR, AS2);  // set Timer/Counter2 to asynchronous mode
//    return SUCCESS;
//  }

  //=== Read the current timer value. ===================================
  async command uint8_t  Timer.get() { return TCNT2; }

  //=== Set/clear the current timer value. ==============================
  async command void Timer.set(uint8_t t)  {
    while (ASSR & 1 << TCN2UB)
      ;
    TCNT2 = t;
  }

  //=== Read the current timer scale. ===================================
  async command uint8_t Timer.getScale() { return TCCR2B & 0x7; }

  //=== Turn off the timers. ============================================
  async command void Timer.off() { call Timer.setScale(AVR_CLOCK_OFF); }

  //=== Write a new timer scale. ========================================
  async command void Timer.setScale(uint8_t s)  { 
    Atm128_TCCR2B_t x = (Atm128_TCCR2B_t) call TimerCtrl.getControlB();
    x.bits.cs = s;
    call TimerCtrl.setControlB(x.flat);  
  }

  //=== Read the control registers. =====================================
  async command uint8_t TimerCtrl.getControlA() { 
    return TCCR2A; 
  }

  async command uint8_t TimerCtrl.getControlB() { 
    return TCCR2B; 
  }

  //=== Write the control registers. ====================================
  async command void TimerCtrl.setControlA( uint8_t x ) { 
    while (ASSR & 1 << TCR2AUB)
      ;
    TCCR2A = ((Atm128_TCCR2A_t)x).flat; 
  }

  async command void TimerCtrl.setControlB( uint8_t x ) { 
    while (ASSR & 1 << TCR2BUB)
      ;
    TCCR2B = ((Atm128_TCCR2B_t)x).flat; 
  }

  //=== Read the interrupt mask. =====================================
  async command uint8_t TimerCtrl.getInterruptMask() { 
    return TIMSK2; 
  }

  //=== Write the interrupt mask. ====================================
  async command void TimerCtrl.setInterruptMask( uint8_t x ) { 
    TIMSK2 = x; 
  }

  //=== Read the interrupt flags. =====================================
  async command uint8_t TimerCtrl.getInterruptFlag() { 
    return TIFR2; 
  }

  //=== Write the interrupt flags. ====================================
  async command void TimerCtrl.setInterruptFlag( uint8_t x ) { 
    TIFR2 = x; 
  }

  //=== Timer 8-bit implementation. ====================================
  async command void Timer.reset() { TIFR2 = 1 << TOV2; }
  async command void Timer.start() { SET_BIT(TIMSK2, TOIE2); }
  async command void Timer.stop()  { CLR_BIT(TIMSK2, TOIE2); }

  bool overflowed() {
    return ((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag()).bits.tov; 
  }

  async command bool Timer.test()  { 
    return overflowed();
  }
  
  async command bool Timer.isOn()  { 
    return ((Atm128_TIMSK2_t)call TimerCtrl.getInterruptMask()).bits.toie; 
  }
  
  async command void Compare.reset() { TIFR2 = 1 << OCF2A; }
  async command void Compare.start() { SET_BIT(TIMSK2,OCIE2A); }
  async command void Compare.stop()  { CLR_BIT(TIMSK2,OCIE2A); }
  async command bool Compare.test()  { 
    return ((Atm128_TIFR2_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; 
  }
  async command bool Compare.isOn()  { 
    return ((Atm128_TIMSK2_t)call TimerCtrl.getInterruptMask()).bits.ociea; 
  }

  //=== Read the compare registers. =====================================
  async command uint8_t Compare.get(){ return OCR2A; }

  //=== Write the compare registers. ====================================
  async command void Compare.set(uint8_t t)   { 
    atomic
      {
	while (ASSR & 1 << OCR2AUB)
	  ;
	OCR2A = t; 
      }
  }

  //=== Timer interrupts signals ========================================
  inline void stabiliseTimer2() {
    TCCR2A = TCCR2A;
    while (ASSR & 1 << TCR2AUB)
      ;
  }

  /**
   * On the atm128, there is a small latency when waking up from
   * POWER_SAVE mode. So if a timer is going to go off very soon, it's
   * better to drop down until EXT_STANDBY, which has a 6 cycle wakeup
   * latency. This function calculates whether staying in EXT_STANDBY
   * is needed. If the timer is not running it returns POWER_DOWN.
   * Please refer to TEP 112 and the atm128 datasheet for details.
   */
  
  async command mcu_power_t McuPowerOverride.lowestState() {
    uint8_t diff;
    // We need to make sure that the sleep wakeup latency will not
    // cause us to miss a timer. POWER_SAVE 
    if (TIMSK2 & (1 << OCIE2A | 1 << TOIE2)) {
      // need to wait for timer 2 updates propagate before sleeping
      // (we don't need to worry about reentering sleep mode too early,
      // as the wake ups from timer2 wait at least one TOSC1 cycle
      // anyway - see the stabiliseTimer2 function)
      while (ASSR & (1 << TCN2UB | 1 << OCR2AUB | 1 << TCR2AUB))
	;
      diff = OCR2A - TCNT2;
      if (diff < EXT_STANDBY_T0_THRESHOLD ||
	  TCNT2 > 256 - EXT_STANDBY_T0_THRESHOLD) 
	return ATM128_POWER_EXT_STANDBY;
      return ATM128_POWER_SAVE;
    }
    else {
      return ATM128_POWER_DOWN;
    }
  }

  default async event void Compare.fired() { }
  AVR_ATOMIC_HANDLER(SIG_OUTPUT_COMPARE2A) {
    stabiliseTimer2();
//    __nesc_enable_interrupt();
   
    signal Compare.fired();
  }

  default async event void Timer.overflow() { }
  AVR_ATOMIC_HANDLER(SIG_OVERFLOW2) {
    stabiliseTimer2();
//    inOverflow = TRUE;
    signal Timer.overflow();
//    inOverflow = FALSE;
  }

  // Asynchronous status register support
  async command Atm128_ASSR_t TimerAsync.getAssr() {
    return *(Atm128_ASSR_t *)&ASSR;
  }

  async command void TimerAsync.setAssr(Atm128_ASSR_t x) {
    ASSR = x.flat;
  }

  async command void TimerAsync.setTimer2Asynchronous() {
    ASSR |= 1 << AS2;
  }

  async command int TimerAsync.controlABusy() {
    return (ASSR & (1 << TCR2AUB)) != 0;
  }

  async command int TimerAsync.controlBBusy() {
    return (ASSR & (1 << TCR2BUB)) != 0;
  }

  async command int TimerAsync.compareABusy() {
    return (ASSR & (1 << OCR2AUB)) != 0;
  }

  async command int TimerAsync.compareBBusy() {
    return (ASSR & (1 << OCR2BUB)) != 0;
  }

  async command int TimerAsync.countBusy() {
    return (ASSR & (1 << TCN2UB)) != 0;
  }

}

--- NEW FILE: HplAtm1281Timer3P.nc ---

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * Internal component of the HPL interface to Atmega1281 timer 3.
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#include <Atm128Timer.h>

module HplAtm1281Timer3P
{
  provides {
    // 16-bit Timers
    interface HplAtm128Timer<uint16_t>   as Timer;
    interface HplAtm128TimerCtrl16       as TimerCtrl;
    interface HplAtm128Capture<uint16_t> as Capture;
    interface HplAtm128Compare<uint16_t> as CompareA;
    interface HplAtm128Compare<uint16_t> as CompareB;
    interface HplAtm128Compare<uint16_t> as CompareC;
  }
}
implementation
{
  //=== Read the current timer value. ===================================
  async command uint16_t Timer.get() { return TCNT3; }

  //=== Set/clear the current timer value. ==============================
  async command void Timer.set(uint16_t t) { TCNT3 = t; }

  //=== Read the current timer scale. ===================================
  async command uint8_t Timer.getScale() { return TCCR3B & 0x7; }

  //=== Turn off the timers. ============================================
  async command void Timer.off() { call Timer.setScale(AVR_CLOCK_OFF); }

  //=== Write a new timer scale. ========================================
  async command void Timer.setScale(uint8_t s)  { 
    Atm128_TCCRB_t x = (Atm128_TCCRB_t) call TimerCtrl.getControlB();
    x.bits.cs = s;
    call TimerCtrl.setControlB(x.flat);  
  }

  //=== Read the control registers. =====================================
  async command uint8_t TimerCtrl.getControlA() { 
    return TCCR3A; 
  }

  async command uint8_t TimerCtrl.getControlB() { 
    return TCCR3B; 
  }

  async command uint8_t TimerCtrl.getControlC() { 
    return TCCR3C; 
  }

  //=== Write the control registers. ====================================
  async command void TimerCtrl.setControlA( uint8_t x ) { 
    TCCR3A = x; 
  }

  async command void TimerCtrl.setControlB( uint8_t x ) { 
    TCCR3B = x; 
  }

  async command void TimerCtrl.setControlC( uint8_t x ) { 
    TCCR3C = x; 
  }

  //=== Read the interrupt mask. =====================================
  async command uint8_t TimerCtrl.getInterruptMask() { 
    return TIMSK3; 
  }

  //=== Write the interrupt mask. ====================================
  async command void TimerCtrl.setInterruptMask( uint8_t x ) { 
    TIMSK3 = x; 
  }

  //=== Read the interrupt flags. =====================================
  async command uint8_t TimerCtrl.getInterruptFlag() { 
    return TIFR3; 
  }

  //=== Write the interrupt flags. ====================================
  async command void TimerCtrl.setInterruptFlag( uint8_t x ) { 
    TIFR3 = x; 
  }

  //=== Capture 16-bit implementation. ===================================
  async command void Capture.setEdge(bool up) { WRITE_BIT(TCCR3B, ICES3, up); }

  //=== Timer 16-bit implementation. ===================================
  async command void Timer.reset()    { TIFR3 = 1 << TOV3; }
  async command void Capture.reset()  { TIFR3 = 1 << ICF3; }
  async command void CompareA.reset() { TIFR3 = 1 << OCF3A; }
  async command void CompareB.reset() { TIFR3 = 1 << OCF3B; }
  async command void CompareC.reset() { TIFR3 = 1 << OCF3C; }

  async command void Timer.start()    { SET_BIT(TIMSK3,TOIE3); }
  async command void Capture.start()  { SET_BIT(TIMSK3,ICIE3); }
  async command void CompareA.start() { SET_BIT(TIMSK3,OCIE3A); }
  async command void CompareB.start() { SET_BIT(TIMSK3,OCIE3B); }
  async command void CompareC.start() { SET_BIT(TIMSK3,OCIE3C); }

  async command void Timer.stop()    { CLR_BIT(TIMSK3,TOIE3); }
  async command void Capture.stop()  { CLR_BIT(TIMSK3,ICIE3); }
  async command void CompareA.stop() { CLR_BIT(TIMSK3,OCIE3A); }
  async command void CompareB.stop() { CLR_BIT(TIMSK3,OCIE3B); }
  async command void CompareC.stop() { CLR_BIT(TIMSK3,OCIE3C); }

  async command bool Timer.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.tov; 
  }
  async command bool Capture.test()  { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.icf; 
  }
  async command bool CompareA.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfa; 
  }
  async command bool CompareB.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfb; 
  }
  async command bool CompareC.test() { 
    return ((Atm128_TIFR_t)call TimerCtrl.getInterruptFlag()).bits.ocfc; 
  }

  async command bool Timer.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.toie;
  }
  async command bool Capture.isOn()  {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.icie;
  }
  async command bool CompareA.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.ociea;
  }
  async command bool CompareB.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.ocieb;
  }
  async command bool CompareC.isOn() {
    return ((Atm128_TIMSK_t)call TimerCtrl.getInterruptMask()).bits.ociec;
  }

  //=== Read the compare registers. =====================================
  async command uint16_t CompareA.get() { return OCR3A; }
  async command uint16_t CompareB.get() { return OCR3B; }
  async command uint16_t CompareC.get() { return OCR3C; }

  //=== Write the compare registers. ====================================
  async command void CompareA.set(uint16_t t) { OCR3A = t; }
  async command void CompareB.set(uint16_t t) { OCR3B = t; }
  async command void CompareC.set(uint16_t t) { OCR3C = t; }

  //=== Read the capture registers. =====================================
  async command uint16_t Capture.get() { return ICR3; }

  //=== Write the capture registers. ====================================
  async command void Capture.set(uint16_t t)  { ICR3 = t; }

  //=== Timer interrupts signals ========================================
  default async event void CompareA.fired() { }
  AVR_NONATOMIC_HANDLER(SIG_OUTPUT_COMPARE3A) {
    signal CompareA.fired();
  }
  default async event void CompareB.fired() { }
  AVR_NONATOMIC_HANDLER(SIG_OUTPUT_COMPARE3B) {
    signal CompareB.fired();
  }
  default async event void CompareC.fired() { }
  AVR_NONATOMIC_HANDLER(SIG_OUTPUT_COMPARE3C) {
    signal CompareC.fired();
  }
  default async event void Capture.captured(uint16_t time) { }
  AVR_NONATOMIC_HANDLER(SIG_INPUT_CAPTURE3) {
    signal Capture.captured(call Timer.get());
  }
  default async event void Timer.overflow() { }
  AVR_NONATOMIC_HANDLER(SIG_OVERFLOW3) {
    signal Timer.overflow();
  }
}

--- NEW FILE: HplAtm128Timer1C.nc ---
/// $Id: HplAtm128Timer1C.nc,v 1.1 2007/11/05 20:36:43 sallai Exp $

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * HPL interface to Atmega1281 timer 1.
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author David Gay <dgay at intel-research.net>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

configuration HplAtm128Timer1C
{
  provides {
    // 16-bit Timers
    interface HplAtm128Timer<uint16_t>   as Timer;
    interface HplAtm128TimerCtrl16       as TimerCtrl;
    interface HplAtm128Capture<uint16_t> as Capture;
    interface HplAtm128Compare<uint16_t> as Compare[uint8_t id];
  }
}
implementation
{
  components HplAtm1281Timer1P;

  Timer = HplAtm1281Timer1P;
  TimerCtrl = HplAtm1281Timer1P;
  Capture = HplAtm1281Timer1P;

  Compare[0] = HplAtm1281Timer1P.CompareA; 
  Compare[1] = HplAtm1281Timer1P.CompareB;
  Compare[2] = HplAtm1281Timer1P.CompareC;
}

--- NEW FILE: HplAtm128Timer3C.nc ---
/// $Id: HplAtm128Timer3C.nc,v 1.1 2007/11/05 20:36:43 sallai Exp $

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * HPL interface to Atmega1281 timer 3.
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author David Gay <dgay at intel-research.net>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

configuration HplAtm128Timer3C
{
  provides {
    // 16-bit Timers
    interface HplAtm128Timer<uint16_t>   as Timer;
    interface HplAtm128TimerCtrl16       as TimerCtrl;
    interface HplAtm128Capture<uint16_t> as Capture;
    interface HplAtm128Compare<uint16_t> as Compare[uint8_t id];
  }
}
implementation
{
  components HplAtm1281Timer3P;

  Timer = HplAtm1281Timer3P;
  TimerCtrl = HplAtm1281Timer3P;
  Capture = HplAtm1281Timer3P;

  Compare[0] = HplAtm1281Timer3P.CompareA; 
  Compare[1] = HplAtm1281Timer3P.CompareB;
  Compare[2] = HplAtm1281Timer3P.CompareC;
}

--- NEW FILE: HplAtm128TimerAsync.nc ---
// $Id: HplAtm128TimerAsync.nc,v 1.1 2007/11/05 20:36:43 sallai Exp $
/*
 * Copyright (c) 2007 Intel Corporation
 * All rights reserved.
 *
 * This file is distributed under the terms in the attached INTEL-LICENSE     
 * file. If you do not find these files, copies can be found by writing to
 * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, 
 * 94704.  Attention:  Intel License Inquiry.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * HPL Interface to Atmega1281 8-bit asynchronous timer control registers
 *
 * @author David Gay
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */
interface HplAtm128TimerAsync
{
  /**
   * Read timer2 asynchronous status register (ASSR)
   * @return Current value of ASSR
   */
  async command Atm128_ASSR_t getAssr();

  /**
   * Set timer2 asynchronous status register (ASSR)
   * @param x New value for ASSR
   */
  async command void setAssr(Atm128_ASSR_t x);

  /**
   * Turn on timer 2 asynchronous mode
   */
  async command void setTimer2Asynchronous();

  /**
   * Check if control register TCCR2A is busy (should not be updated if true)
   * @return TRUE if TCCR2A is busy, FALSE otherwise (can be updated)
   */
  async command int controlABusy();

  /**
   * Check if control register TCCR2B is busy (should not be updated if true)
   * @return TRUE if TCCR2B is busy, FALSE otherwise (can be updated)
   */
  async command int controlBBusy();

  /**
   * Check if compare register OCR2A is busy (should not be updated if true)
   * @return TRUE if OCR2A is busy, FALSE otherwise (can be updated)
   */
  async command int compareABusy();

  /**
   * Check if compare register OCR2B is busy (should not be updated if true)
   * @return TRUE if OCR2B is busy, FALSE otherwise (can be updated)
   */
  async command int compareBBusy();

  /**
   * Check if current timer value (TCNT2) is busy (should not be updated if true)
   * @return TRUE if TCNT2 is busy, FALSE otherwise (can be updated)
   */
  async command int countBusy();

}

--- NEW FILE: HplAtm128TimerCtrl16.nc ---
/// $Id: HplAtm128TimerCtrl16.nc,v 1.1 2007/11/05 20:36:43 sallai Exp $

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * HPL Interface to Atmega1281 16-bit timer control registers
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#include <Atm128Timer.h>

interface HplAtm128TimerCtrl16
{
  /// Timer control register: Direct access
  async command uint8_t getControlA();
  async command uint8_t getControlB();
  async command uint8_t getControlC();
  async command void setControlA( uint8_t control );
  async command void setControlB( uint8_t control );
  async command void setControlC( uint8_t control );
    
  /// Interrupt mask register: Direct access
  async command uint8_t getInterruptMask();
  async command void setInterruptMask( uint8_t mask);

  /// Interrupt flag register: Direct access
  async command uint8_t getInterruptFlag();
  async command void setInterruptFlag( uint8_t flags );
}


--- NEW FILE: HplAtm128TimerCtrl8.nc ---
/// $Id: HplAtm128TimerCtrl8.nc,v 1.1 2007/11/05 20:36:44 sallai Exp $

/*
 * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE TO 
 * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL 
 * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN
 * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 * DAMAGE. 
 *
 * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS 
 * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY 
 * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR 
 * MODIFICATIONS.
 */

/*
 * Copyright (c) 2007, Vanderbilt University
 * All rights reserved.
 *
 * Permission to use, copy, modify, and distribute this software and its
 * documentation for any purpose, without fee, and without written agreement is
 * hereby granted, provided that the above copyright notice, the following
 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE VANDERBILT
 * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
 * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER IS
 * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
 * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
 *
 */

/**
 * HPL Interface to Atmega1281 8-bit timer control registers
 *
 * @author Martin Turon <mturon at xbow.com>
 * @author Janos Sallai <janos.sallai at vanderbilt.edu>
 */

#include <Atm128Timer.h>

interface HplAtm128TimerCtrl8
{
  /// Timer control register: Direct access
  async command uint8_t getControlA();
  async command uint8_t getControlB();
  async command void setControlA( uint8_t control );
  async command void setControlB( uint8_t control );

  /// Interrupt mask register: Direct access
  async command uint8_t getInterruptMask();
  async command void setInterruptMask( uint8_t mask);

  /// Interrupt flag register: Direct access
  async command uint8_t getInterruptFlag();
  async command void setInterruptFlag( uint8_t flags );
}