[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/msp430/dma HplMsp430DmaXP.nc, 1.4, 1.5 Msp430Dma.h, 1.4, 1.5

dmm rincon at users.sourceforge.net
Thu Nov 8 13:34:45 PST 2007 

Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/msp430/dma
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv24198/dma

Modified Files:
	HplMsp430DmaXP.nc Msp430Dma.h 
Log Message:
Mark Hays repair the SPI code, unit testing demonstrates SPI0 w/ and w/out DMA works properly, and we have a chance at SPI1 working properly now as well - although it still hasn't been tested completely.

Index: HplMsp430DmaXP.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/msp430/dma/HplMsp430DmaXP.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HplMsp430DmaXP.nc	12 Dec 2006 18:23:07 -0000	1.4
--- HplMsp430DmaXP.nc	8 Nov 2007 21:34:42 -0000	1.5
***************
*** 55,58 ****
--- 55,59 ----
   * @author Jonathan Hui <jhui at archrock.com>
   * @author Joe Polastre <info at moteiv.com>
+  * @author Mark Hays
   * @version $Revision$ $Date$
   */
***************
*** 106,158 ****
    async command void DMA.setSingleMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
    }
  
    async command void DMA.setBlockMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMADT0;
    }
  
    async command void DMA.setBurstMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMADT1;
    }
  
    async command void DMA.setRepeatedSingleMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMADT2;
    }
  
    async command void DMA.setRepeatedBlockMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= ( DMADT2 | DMADT0 );
    }
  
    async command void DMA.setRepeatedBurstMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= ( DMADT2 | DMADT1 );
    }
  
    async command void DMA.setSrcNoIncrement() {
      DMAxCTL &= ~( DMASRCINCR0 | DMASRCINCR1 );
    }
  
    async command void DMA.setSrcDecrement() {
!     DMAxCTL |= DMASRCINCR1;
    }
  
    async command void DMA.setSrcIncrement() {
!     DMAxCTL |= ( DMASRCINCR0 | DMASRCINCR1 );
    }
  
    async command void DMA.setDstNoIncrement() {
      DMAxCTL &= ~( DMADSTINCR0 | DMADSTINCR1 );
    }          
  
    async command void DMA.setDstDecrement() {
!     DMAxCTL |= DMADSTINCR1;
    }
  
    async command void DMA.setDstIncrement() {
!     DMAxCTL |= ( DMADSTINCR0 | DMADSTINCR1 );
    }
  
--- 107,166 ----
    async command void DMA.setSingleMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
+     DMAxCTL |= DMA_SINGLE_TRANSFER;
    }
  
    async command void DMA.setBlockMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMA_BLOCK_TRANSFER;
    }
  
    async command void DMA.setBurstMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMA_BURST_BLOCK_TRANSFER;
    }
  
    async command void DMA.setRepeatedSingleMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMA_REPEATED_SINGLE_TRANSFER;
    }
  
    async command void DMA.setRepeatedBlockMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMA_REPEATED_BLOCK_TRANSFER;
    }
  
    async command void DMA.setRepeatedBurstMode() {
      DMAxCTL &= ~( DMADT0 | DMADT1 | DMADT2 );
!     DMAxCTL |= DMA_REPEATED_BURST_BLOCK_TRANSFER;
    }
  
    async command void DMA.setSrcNoIncrement() {
      DMAxCTL &= ~( DMASRCINCR0 | DMASRCINCR1 );
+     DMAxCTL |= DMA_ADDRESS_UNCHANGED;
    }
  
    async command void DMA.setSrcDecrement() {
!     DMAxCTL &= ~( DMASRCINCR0 | DMASRCINCR1 );
!     DMAxCTL |= DMA_ADDRESS_DECREMENTED;
    }
  
    async command void DMA.setSrcIncrement() {
!     DMAxCTL &= ~( DMASRCINCR0 | DMASRCINCR1 );
!     DMAxCTL |= DMA_ADDRESS_INCREMENTED;
    }
  
    async command void DMA.setDstNoIncrement() {
      DMAxCTL &= ~( DMADSTINCR0 | DMADSTINCR1 );
+     DMAxCTL |= DMA_ADDRESS_UNCHANGED;
    }          
  
    async command void DMA.setDstDecrement() {
!     DMAxCTL &= ~( DMADSTINCR0 | DMADSTINCR1 );
!     DMAxCTL |= DMA_ADDRESS_DECREMENTED;
    }
  
    async command void DMA.setDstIncrement() {
!     DMAxCTL &= ~( DMADSTINCR0 | DMADSTINCR1 );
!     DMAxCTL |= DMA_ADDRESS_INCREMENTED;
    }
  
***************
*** 161,172 ****
--- 169,183 ----
      DMAxCTL |= DMASWDW;
    }
+ 
    async command void DMA.setByteToWord() {
      DMAxCTL &= ~(DMASRCBYTE | DMADSTBYTE);
      DMAxCTL |= DMASBDW;
    }
+ 
    async command void DMA.setWordToByte() {
      DMAxCTL &= ~(DMASRCBYTE | DMADSTBYTE);
      DMAxCTL |= DMASWDB;
    }
+ 
    async command void DMA.setByteToByte() {
      DMAxCTL &= ~(DMASRCBYTE | DMADSTBYTE);
***************
*** 191,199 ****
  
    async command void DMA.enableInterrupt() {
!     DMAxCTL  |= DMAIE;
    }
  
    async command void DMA.disableInterrupt() {
!     DMAxCTL  &= ~DMAIE;
    }
  
--- 202,210 ----
  
    async command void DMA.enableInterrupt() {
!     DMAxCTL |= DMAIE;
    }
  
    async command void DMA.disableInterrupt() {
!     DMAxCTL &= ~DMAIE;
    }
  
***************
*** 236,240 ****
      DMAxDA = (uint16_t)dest;
      DMAxSZ = size;
!     DMACTL0 = ( DMACTL0 & ~DMAxTSEL_mask ) | ( t << DMAxTSEL_shift );
      DMAxCTL = s;
    }
--- 247,251 ----
      DMAxDA = (uint16_t)dest;
      DMAxSZ = size;
!     call DMA.setTrigger((dma_trigger_t) t);
      DMAxCTL = s;
    }
***************
*** 269,274 ****
      DMAxSZ = 0;
    }
- 
- 
  }
  
--- 280,283 ----

Index: Msp430Dma.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/msp430/dma/Msp430Dma.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** Msp430Dma.h	12 Dec 2006 18:23:07 -0000	1.4
--- Msp430Dma.h	8 Nov 2007 21:34:42 -0000	1.5
***************
*** 54,57 ****
--- 54,58 ----
   * @author Ben Greenstein <ben at cs.ucla.edu>
   * @author Jonathan Hui <jhui at archrock.com>
+  * @author Mark Hays
   * $Revision$ $Date$
   */
***************
*** 60,66 ****
--- 61,69 ----
  #define MSP430DMA_H
  
+ // General stuff
  enum {
    DMA_CHANNELS = 3
  };
+ 
  enum {
    DMA_CHANNEL0 = 0,
***************
*** 69,79 ****
    DMA_CHANNEL_UNKNOWN = 3
  };
  enum { 
    DMA_CHANNEL_AVAILABLE = 0,
!   DMA_CHANNEL_IN_USE = 1
  };
  
! // HPL constants
! 
  enum {
    DMA0TSEL_SHIFT = 0,
--- 72,83 ----
    DMA_CHANNEL_UNKNOWN = 3
  };
+ 
  enum { 
    DMA_CHANNEL_AVAILABLE = 0,
!   DMA_CHANNEL_IN_USE    = 1
  };
  
! ////////////////////////////////////////
! // Per-channel fields in DMACTL0
  enum {
    DMA0TSEL_SHIFT = 0,
***************
*** 85,109 ****
    DMA2TSEL_MASK  = ( 0xf00 ),
  };
! enum {
!   DMASRCINCR_SHIFT = (8),
!   DMADSTINCR_SHIFT = (10),
!   DMAINCR_MASK = (0x3)
! };
! enum {
!   DMADT_SHIFT = (12),
!   DMADT_MASK = (0x3)
! };
  typedef enum {
    DMA_TRIGGER_DMAREQ =          0x0, // software trigger
    DMA_TRIGGER_TACCR2 =          0x1,            
    DMA_TRIGGER_TBCCR2 =          0x2,
!   DMA_TRIGGER_USARTRX =         0x3, // URXIFG0 (UART/SPI), data received (I2C)
!   DMA_TRIGGER_USARTTX =         0x4, // UTXIFG0 (UART/SPI), transmit ready (I2C)
    DMA_TRIGGER_DAC12IFG =        0x5, // DAC12_0CTL DAC12IFG bit
    DMA_TRIGGER_ADC12IFGx =       0x6, 
    DMA_TRIGGER_TACCR0 =          0x7, // CCIFG bit
    DMA_TRIGGER_TBCCR0 =          0x8, // CCIFG bit
!   DMA_TRIGGER_URXIFG1 =         0x9,            
!   DMA_TRIGGER_UTXIFG1 =         0xa,
    DMA_TRIGGER_MULT =            0xb, // Hardware Multiplier Ready
    DMA_TRIGGER_DMAxIFG =         0xe, // DMA0IFG triggers DMA channel 1
--- 89,106 ----
    DMA2TSEL_MASK  = ( 0xf00 ),
  };
! 
! // Per-field (channel) in DMACTL0
  typedef enum {
    DMA_TRIGGER_DMAREQ =          0x0, // software trigger
    DMA_TRIGGER_TACCR2 =          0x1,            
    DMA_TRIGGER_TBCCR2 =          0x2,
!   DMA_TRIGGER_URXIFG0 =         0x3, // RX on USART0 (UART/SPI)
!   DMA_TRIGGER_UTXIFG0 =         0x4, // TX on USART0 (UART/SPI)
    DMA_TRIGGER_DAC12IFG =        0x5, // DAC12_0CTL DAC12IFG bit
    DMA_TRIGGER_ADC12IFGx =       0x6, 
    DMA_TRIGGER_TACCR0 =          0x7, // CCIFG bit
    DMA_TRIGGER_TBCCR0 =          0x8, // CCIFG bit
!   DMA_TRIGGER_URXIFG1 =         0x9, // RX on USART1 (UART/SPI)
!   DMA_TRIGGER_UTXIFG1 =         0xa, // TX on USART1 (UART/SPI)
    DMA_TRIGGER_MULT =            0xb, // Hardware Multiplier Ready
    DMA_TRIGGER_DMAxIFG =         0xe, // DMA0IFG triggers DMA channel 1
***************
*** 113,143 ****
  } dma_trigger_t;
  
  enum {
    DISABLE_NMI = 0,
!   ENABLE_NMI = 1
  };
  
  enum {
    NOT_ROUND_ROBIN = 0,
!   ROUND_ROBIN = 1,
  };
  
  enum {
    NOT_ON_FETCH = 0,
!   ON_FETCH = 1
  };
  
! typedef enum {
!   DMA_EDGE_SENSITIVE = 0x0,
!   DMA_LEVEL_SENSITIVE = 0x1
! } dma_level_t;
  
  typedef enum {
!   DMA_WORD = 0x0,
!   DMA_BYTE = 0x1
! } dma_byte_t;
  
  typedef enum {
!   DMA_ADDRESS_UNCHANGED = 0x0,
    DMA_ADDRESS_DECREMENTED = 0x2,
    DMA_ADDRESS_INCREMENTED = 0x3
--- 110,169 ----
  } dma_trigger_t;
  
+ typedef struct dma_channel_trigger_s {
+   unsigned int trigger : 4; 
+   unsigned int reserved : 12;
+ } __attribute__ ((packed)) dma_channel_trigger_t;
+ 
+ ////////////////////////////////////////
+ // Bits in DMACTL1
  enum {
    DISABLE_NMI = 0,
!   ENABLE_NMI  = 1,
  };
  
  enum {
    NOT_ROUND_ROBIN = 0,
!   ROUND_ROBIN     = 1,
  };
  
  enum {
    NOT_ON_FETCH = 0,
!   ON_FETCH     = 1,
  };
  
! typedef struct dma_state_s {
!   unsigned int enableNMI : 1;
!   unsigned int roundRobin : 1;
!   unsigned int onFetch : 1;
!   unsigned int reserved : 13;
! } __attribute__ ((packed)) dma_state_t;
! 
! ////////////////////////////////////////
! // Stuff in DMAxCTL
! 
! // DMADTx
! enum {
!   DMADT_SHIFT = 12,
!   DMADT_MASK  = 0x7,
! };
  
  typedef enum {
!   DMA_SINGLE_TRANSFER               = 0x0,
!   DMA_BLOCK_TRANSFER                = 0x1,
!   DMA_BURST_BLOCK_TRANSFER          = 0x2,
!   DMA_REPEATED_SINGLE_TRANSFER      = 0x4,
!   DMA_REPEATED_BLOCK_TRANSFER       = 0x5,
!   DMA_REPEATED_BURST_BLOCK_TRANSFER = 0x7
! } dma_transfer_mode_t;
! 
! // DMA{SRC,DST}INCRx
! enum {
!   DMASRCINCR_SHIFT = 8,
!   DMADSTINCR_SHIFT = 10,
!   DMAINCR_MASK     = 0x3,
! };
  
  typedef enum {
!   DMA_ADDRESS_UNCHANGED   = 0x0,
    DMA_ADDRESS_DECREMENTED = 0x2,
    DMA_ADDRESS_INCREMENTED = 0x3
***************
*** 145,167 ****
  
  typedef enum {
!   DMA_SINGLE_TRANSFER = 0x0,
!   DMA_BLOCK_TRANSFER = 0x1,
!   DMA_BURST_BLOCK_TRANSFER = 0x2,
!   DMA_REPEATED_SINGLE_TRANSFER = 0x4,
!   DMA_REPEATED_BLOCK_TRANSFER = 0x5,
!   DMA_REPEATED_BURST_BLOCK_TRANSFER = 0x7
! } dma_transfer_mode_t;
! 
! typedef struct dma_state_s {
!   unsigned int enableNMI : 1;
!   unsigned int roundRobin : 1;
!   unsigned int onFetch : 1;
!   unsigned int reserved : 13;
! } __attribute__ ((packed)) dma_state_t;
  
! typedef struct dma_channel_trigger_s {
!   unsigned int trigger : 4; 
!   unsigned int reserved : 12;
! } __attribute__ ((packed)) dma_channel_trigger_t;
  
  typedef struct dma_channel_state_s {
--- 171,183 ----
  
  typedef enum {
!   DMA_WORD = 0x0,
!   DMA_BYTE = 0x1
! } dma_byte_t;
  
! // DMALEVEL
! typedef enum {
!   DMA_EDGE_SENSITIVE  = 0x0,
!   DMA_LEVEL_SENSITIVE = 0x1
! } dma_level_t;
  
  typedef struct dma_channel_state_s {
***************
*** 181,182 ****
--- 197,199 ----
  
  #endif
+

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