[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/atm128
HplAtm128UartP.nc, 1.5, 1.6
Phil Levis
scipio at users.sourceforge.net
Wed Nov 28 11:17:10 PST 2007
Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/atm128
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv10477
Modified Files:
HplAtm128UartP.nc
Log Message:
Merge in Alec's fixes.
Index: HplAtm128UartP.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/atm128/HplAtm128UartP.nc,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** HplAtm128UartP.nc 12 Dec 2006 18:23:03 -0000 1.5
--- HplAtm128UartP.nc 28 Nov 2007 19:17:08 -0000 1.6
***************
*** 106,110 ****
command error_t Uart0TxControl.start() {
- SET_BIT(UCSR0B, TXCIE);
SET_BIT(UCSR0B, TXEN);
call McuPowerState.update();
--- 106,109 ----
***************
*** 113,117 ****
command error_t Uart0TxControl.stop() {
- CLR_BIT(UCSR0B, TXCIE);
CLR_BIT(UCSR0B, TXEN);
call McuPowerState.update();
--- 112,115 ----
***************
*** 120,124 ****
command error_t Uart0RxControl.start() {
- SET_BIT(UCSR0B, RXCIE);
SET_BIT(UCSR0B, RXEN);
call McuPowerState.update();
--- 118,121 ----
***************
*** 127,131 ****
command error_t Uart0RxControl.stop() {
- CLR_BIT(UCSR0B, RXCIE);
CLR_BIT(UCSR0B, RXEN);
call McuPowerState.update();
--- 124,127 ----
***************
*** 134,153 ****
async command error_t HplUart0.enableTxIntr() {
! SET_BIT(UCSR0B, TXEN);
return SUCCESS;
}
async command error_t HplUart0.disableTxIntr(){
! CLR_BIT(UCSR0B, TXEN);
return SUCCESS;
}
async command error_t HplUart0.enableRxIntr(){
! SET_BIT(UCSR0B, RXEN);
return SUCCESS;
}
async command error_t HplUart0.disableRxIntr(){
! CLR_BIT(UCSR0B, RXEN);
return SUCCESS;
}
--- 130,150 ----
async command error_t HplUart0.enableTxIntr() {
! SET_BIT(UCSR0A, TXC);
! SET_BIT(UCSR0B, TXCIE);
return SUCCESS;
}
async command error_t HplUart0.disableTxIntr(){
! CLR_BIT(UCSR0B, TXCIE);
return SUCCESS;
}
async command error_t HplUart0.enableRxIntr(){
! SET_BIT(UCSR0B, RXCIE);
return SUCCESS;
}
async command error_t HplUart0.disableRxIntr(){
! CLR_BIT(UCSR0B, RXCIE);
return SUCCESS;
}
***************
*** 203,207 ****
command error_t Uart1TxControl.start() {
- SET_BIT(UCSR1B, TXCIE);
SET_BIT(UCSR1B, TXEN);
call McuPowerState.update();
--- 200,203 ----
***************
*** 210,214 ****
command error_t Uart1TxControl.stop() {
- CLR_BIT(UCSR1B, TXCIE);
CLR_BIT(UCSR1B, TXEN);
call McuPowerState.update();
--- 206,209 ----
***************
*** 217,221 ****
command error_t Uart1RxControl.start() {
- SET_BIT(UCSR1B, RXCIE);
SET_BIT(UCSR1B, RXEN);
call McuPowerState.update();
--- 212,215 ----
***************
*** 224,228 ****
command error_t Uart1RxControl.stop() {
- CLR_BIT(UCSR1B, RXCIE);
CLR_BIT(UCSR1B, RXEN);
call McuPowerState.update();
--- 218,221 ----
***************
*** 231,250 ****
async command error_t HplUart1.enableTxIntr() {
! SET_BIT(UCSR1B, TXEN);
return SUCCESS;
}
async command error_t HplUart1.disableTxIntr(){
! CLR_BIT(UCSR1B, TXEN);
return SUCCESS;
}
async command error_t HplUart1.enableRxIntr(){
! SET_BIT(UCSR1B, RXEN);
return SUCCESS;
}
async command error_t HplUart1.disableRxIntr(){
! CLR_BIT(UCSR1B, RXEN);
return SUCCESS;
}
--- 224,244 ----
async command error_t HplUart1.enableTxIntr() {
! SET_BIT(UCSR1A, TXC);
! SET_BIT(UCSR1B, TXCIE);
return SUCCESS;
}
async command error_t HplUart1.disableTxIntr(){
! CLR_BIT(UCSR1B, TXCIE);
return SUCCESS;
}
async command error_t HplUart1.enableRxIntr(){
! SET_BIT(UCSR1B, RXCIE);
return SUCCESS;
}
async command error_t HplUart1.disableRxIntr(){
! CLR_BIT(UCSR1B, RXCIE);
return SUCCESS;
}
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