[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/pxa27x HplPXA27xInterrupt.nc, 1.4, 1.5 HplPXA27xInterruptCntl.nc, 1.4, 1.5 inttypes.h, 1.2, 1.3 HplPXA27xInterruptM.nc, 1.4, 1.5 pxa27x_util.s, 1.2, 1.3 arm_defs.h, 1.2, 1.3
Razvan Musaloiu-E.
razvanm at users.sourceforge.net
Tue Jun 10 17:42:16 PDT 2008
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Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv9551/chips/pxa27x
Modified Files:
HplPXA27xInterrupt.nc HplPXA27xInterruptCntl.nc inttypes.h
HplPXA27xInterruptM.nc pxa27x_util.s arm_defs.h
Log Message:
Convert to Unix-style line terminators.
Index: HplPXA27xInterrupt.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/HplPXA27xInterrupt.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HplPXA27xInterrupt.nc 12 Dec 2006 18:23:11 -0000 1.4
--- HplPXA27xInterrupt.nc 11 Jun 2008 00:42:13 -0000 1.5
***************
*** 1,76 ****
! // $Id$
! /* tab:4
! * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
! * downloading, copying, installing or using the software you agree to
! * this license. If you do not agree to this license, do not download,
! * install, copy or use the software.
! *
! * Intel Open Source License
! *
! * Copyright (c) 2002 Intel Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! *
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! * Neither the name of the Intel Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
! * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
! * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
! * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
! * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
! * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
! * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! *
! *
! */
! /**
! * This interface supports the core peripheral interrupts of the PXA27X
! * processor.
! * It is usually parameterized based on the Peripheral ID (PPID) of the
! * interrupt signal.
! * ARM interrupt levels (IRQ/FIQ) are established by wiring.
! * Priorities are established by a static table (TOSH_IRP_TABLE)
! *
! * Components implementing this interface are expected to provide reentrant
! * (i.e. atomic) semantics.
! *
! * @author: Philip Buonadonna
! */
!
! interface HplPXA27xInterrupt
! {
! /**
! * Allocates a given peripheral interrupt with the PXA27X interrupt manager.
! * Specifically, it establishes the interrupt level (IRQ or FIQ) and the
! * priority.
! */
! async command error_t allocate();
!
! /**
! * Enables a periperhal interrupt.
! */
! async command void enable();
!
! /**
! * Disables a peripheral interrupt.
! */
! async command void disable();
!
! /**
! * The peripheral interrupt event.
! */
! async event void fired();
! }
--- 1,76 ----
! // $Id$
! /* tab:4
! * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
! * downloading, copying, installing or using the software you agree to
! * this license. If you do not agree to this license, do not download,
! * install, copy or use the software.
! *
! * Intel Open Source License
! *
! * Copyright (c) 2002 Intel Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! *
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! * Neither the name of the Intel Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
! * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
! * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
! * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
! * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
! * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
! * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! *
! *
! */
! /**
! * This interface supports the core peripheral interrupts of the PXA27X
! * processor.
! * It is usually parameterized based on the Peripheral ID (PPID) of the
! * interrupt signal.
! * ARM interrupt levels (IRQ/FIQ) are established by wiring.
! * Priorities are established by a static table (TOSH_IRP_TABLE)
! *
! * Components implementing this interface are expected to provide reentrant
! * (i.e. atomic) semantics.
! *
! * @author: Philip Buonadonna
! */
!
! interface HplPXA27xInterrupt
! {
! /**
! * Allocates a given peripheral interrupt with the PXA27X interrupt manager.
! * Specifically, it establishes the interrupt level (IRQ or FIQ) and the
! * priority.
! */
! async command error_t allocate();
!
! /**
! * Enables a periperhal interrupt.
! */
! async command void enable();
!
! /**
! * Disables a peripheral interrupt.
! */
! async command void disable();
!
! /**
! * The peripheral interrupt event.
! */
! async event void fired();
! }
Index: HplPXA27xInterruptCntl.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/HplPXA27xInterruptCntl.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HplPXA27xInterruptCntl.nc 12 Dec 2006 18:23:11 -0000 1.4
--- HplPXA27xInterruptCntl.nc 11 Jun 2008 00:42:13 -0000 1.5
***************
*** 1,58 ****
! // $Id$
! /*
! * Copyright (c) 2005 Arch Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arch Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! * This interface provides access to the ICCR functionality of
! * the PXA27x interrupt controller.
! *
! * Refer to the PXA27x Developers Guide for more information.
! *
! * @author: Philip Buonadonna
! */
!
! interface HplPXA27xInterruptCntl
! {
! /**
! * Sets the ICCR DIM bit of the PXA27x interrupt controller
! *
! * @param flag TRUE to set the DIM bit, FALSE to clear
! *
! */
! async command void setICCR_DIM(bool flag);
!
! /**
! * Gets the value of the ICCR DIM bit.
! *
! * @return value TRUE if set, FALSE if clear.
! */
! async command bool getICCR_DIM();
!
! }
!
--- 1,58 ----
! // $Id$
! /*
! * Copyright (c) 2005 Arch Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arch Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! * This interface provides access to the ICCR functionality of
! * the PXA27x interrupt controller.
! *
! * Refer to the PXA27x Developers Guide for more information.
! *
! * @author: Philip Buonadonna
! */
!
! interface HplPXA27xInterruptCntl
! {
! /**
! * Sets the ICCR DIM bit of the PXA27x interrupt controller
! *
! * @param flag TRUE to set the DIM bit, FALSE to clear
! *
! */
! async command void setICCR_DIM(bool flag);
!
! /**
! * Gets the value of the ICCR DIM bit.
! *
! * @return value TRUE if set, FALSE if clear.
! */
! async command bool getICCR_DIM();
!
! }
!
Index: inttypes.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/inttypes.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** inttypes.h 12 Jul 2006 17:01:51 -0000 1.2
--- inttypes.h 11 Jun 2008 00:42:13 -0000 1.3
***************
*** 1,19 ****
! #ifndef __INTTYPES_H_
! #define __INTTYPES_H_
!
! typedef signed char int8_t;
! typedef unsigned char uint8_t;
!
! typedef short int16_t;
! typedef unsigned short uint16_t;
!
! typedef int int32_t;
! typedef unsigned int uint32_t;
!
! typedef long long int64_t;
! typedef unsigned long long uint64_t;
!
! typedef int32_t intptr_t;
! typedef uint32_t uintptr_t;
!
! #endif
--- 1,19 ----
! #ifndef __INTTYPES_H_
! #define __INTTYPES_H_
!
! typedef signed char int8_t;
! typedef unsigned char uint8_t;
!
! typedef short int16_t;
! typedef unsigned short uint16_t;
!
! typedef int int32_t;
! typedef unsigned int uint32_t;
!
! typedef long long int64_t;
! typedef unsigned long long uint64_t;
!
! typedef int32_t intptr_t;
! typedef uint32_t uintptr_t;
!
! #endif
Index: HplPXA27xInterruptM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/HplPXA27xInterruptM.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HplPXA27xInterruptM.nc 12 Dec 2006 18:23:11 -0000 1.4
--- HplPXA27xInterruptM.nc 11 Jun 2008 00:42:13 -0000 1.5
***************
*** 1,232 ****
! // $Id$
!
! /* tab:4
! * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
! * downloading, copying, installing or using the software you agree to
! * this license. If you do not agree to this license, do not download,
! * install, copy or use the software.
! *
! * Intel Open Source License
! *
! * Copyright (c) 2002 Intel Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! *
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! * Neither the name of the Intel Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
! * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
! * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
! * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
! * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
! * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
! * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! *
! *
! */
! /*
! *
! * Authors: Phil Buonadonna
! *
! * Edits: Josh Herbach
! * Revised: 09/02/2005
! */
!
! module HplPXA27xInterruptM
! {
! provides {
! interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];
! interface HplPXA27xInterruptCntl;
! }
! }
!
! implementation
! {
!
! uint32_t getICHP() {
! uint32_t val;
!
! asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));
! return val;
! }
!
! /* Core PXA27X interrupt dispatch vectors */
! /* DO NOT change the name of these functions */
! void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {
!
! uint32_t IRQPending;
!
! IRQPending = getICHP(); // Determine which interrupt to service
! IRQPending >>= 16; // Right justify to the IRQ portion
!
! while (IRQPending & (1 << 15)) {
! uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit
! signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt
! IRQPending = getICHP(); // Determine which interrupt to service
! IRQPending >>= 16; // Right justify to the IRQ portion
! }
!
! return;
! }
!
! void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {
!
! }
!
! static uint8_t usedPriorities = 0;
!
! /* Helper functions */
! /* NOTE: Read-back of all register writes is necessary to ensure the data latches */
!
! error_t allocate(uint8_t id, bool level, uint8_t priority)
! {
! uint32_t tmp;
! error_t error = FAIL;
!
! atomic{
! uint8_t i;
! if(usedPriorities == 0){//assumed that the table will have some entries
! uint8_t PriorityTable[40], DuplicateTable[40];
! for(i = 0; i < 40; i++){
! DuplicateTable[i] = PriorityTable[i] = 0xFF;
! }
!
! for(i = 0; i < 40; i++)
! if(TOSH_IRP_TABLE[i] != 0xff){
! if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities
! in the table, mark
! for later fixing*/
! DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];
! else
! PriorityTable[TOSH_IRP_TABLE[i]] = i;
! }
!
! //compress table
! for(i = 0; i < 40; i++){
! if(PriorityTable[i] != 0xff){
! PriorityTable[usedPriorities] = PriorityTable[i];
! if(i != usedPriorities)
! PriorityTable[i] = 0xFF;
! usedPriorities++;
! }
! }
!
! for(i = 0; i < 40; i++)
! if(DuplicateTable[i] != 0xFF){
! uint8_t j, ExtraTable[40];
! for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);
! memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);
! memcpy(PriorityTable + j + 1, ExtraTable + j + 1,
! usedPriorities - j);
! PriorityTable[j] = i;
! usedPriorities++;
! }
!
! for(i = 0; i < usedPriorities; i++){
! IPR(i) = (IPR_VALID | PriorityTable[i]);
! tmp = IPR(i);
! }
! }
!
! if (id < 34){
! if(priority == 0xff){
! priority = usedPriorities;
! usedPriorities++;
! IPR(priority) = (IPR_VALID | (id));
! tmp = IPR(priority);
! }
! if (level) {
! _ICLR(id) |= _PPID_Bit(id);
! tmp = _ICLR(id);
! }
!
! error = SUCCESS;
! }
! }
! return error;
! }
!
! void enable(uint8_t id)
! {
! uint32_t tmp;
! atomic {
! if (id < 34) {
! _ICMR(id) |= _PPID_Bit(id);
! tmp = _ICMR(id);
! }
! }
! return;
! }
!
! void disable(uint8_t id)
! {
! uint32_t tmp;
! atomic {
! if (id < 34) {
! _ICMR(id) &= ~(_PPID_Bit(id));
! tmp = _ICMR(id);
! }
! }
! return;
! }
!
! /* Interface implementation */
!
! async command error_t PXA27xIrq.allocate[uint8_t id]()
! {
! return allocate(id, FALSE, TOSH_IRP_TABLE[id]);
! }
!
! async command void PXA27xIrq.enable[uint8_t id]()
! {
! enable(id);
! return;
! }
!
! async command void PXA27xIrq.disable[uint8_t id]()
! {
! disable(id);
! return;
! }
!
! async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {
!
! if (flag) {
! ICCR |= ICCR_DIM;
! }
! else {
! ICCR = 0;
! }
! return;
!
! }
!
! async command bool HplPXA27xInterruptCntl.getICCR_DIM() {
! bool result = FALSE;
!
! if (ICCR & ICCR_DIM) {
! result = TRUE;
! }
!
! return result;
! }
!
! default async event void PXA27xIrq.fired[uint8_t id]()
! {
! return;
! }
!
! }
--- 1,232 ----
! // $Id$
!
! /* tab:4
! * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
! * downloading, copying, installing or using the software you agree to
! * this license. If you do not agree to this license, do not download,
! * install, copy or use the software.
! *
! * Intel Open Source License
! *
! * Copyright (c) 2002 Intel Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! *
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! * Neither the name of the Intel Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
! * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
! * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
! * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
! * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
! * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
! * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! *
! *
! */
! /*
! *
! * Authors: Phil Buonadonna
! *
! * Edits: Josh Herbach
! * Revised: 09/02/2005
! */
!
! module HplPXA27xInterruptM
! {
! provides {
! interface HplPXA27xInterrupt as PXA27xIrq[uint8_t id];
! interface HplPXA27xInterruptCntl;
! }
! }
!
! implementation
! {
!
! uint32_t getICHP() {
! uint32_t val;
!
! asm volatile ("mrc p6,0,%0,c5,c0,0\n\t":"=r" (val));
! return val;
! }
!
! /* Core PXA27X interrupt dispatch vectors */
! /* DO NOT change the name of these functions */
! void hplarmv_irq() __attribute__ ((interrupt ("IRQ"))) @C() @atomic_hwevent() {
!
! uint32_t IRQPending;
!
! IRQPending = getICHP(); // Determine which interrupt to service
! IRQPending >>= 16; // Right justify to the IRQ portion
!
! while (IRQPending & (1 << 15)) {
! uint8_t PeripheralID = (IRQPending & 0x3f); // Get rid of the Valid bit
! signal PXA27xIrq.fired[PeripheralID](); // Handler is responsible for clearing interrupt
! IRQPending = getICHP(); // Determine which interrupt to service
! IRQPending >>= 16; // Right justify to the IRQ portion
! }
!
! return;
! }
!
! void hplarmv_fiq() __attribute__ ((interrupt ("FIQ"))) @C() @atomic_hwevent() {
!
! }
!
! static uint8_t usedPriorities = 0;
!
! /* Helper functions */
! /* NOTE: Read-back of all register writes is necessary to ensure the data latches */
!
! error_t allocate(uint8_t id, bool level, uint8_t priority)
! {
! uint32_t tmp;
! error_t error = FAIL;
!
! atomic{
! uint8_t i;
! if(usedPriorities == 0){//assumed that the table will have some entries
! uint8_t PriorityTable[40], DuplicateTable[40];
! for(i = 0; i < 40; i++){
! DuplicateTable[i] = PriorityTable[i] = 0xFF;
! }
!
! for(i = 0; i < 40; i++)
! if(TOSH_IRP_TABLE[i] != 0xff){
! if(PriorityTable[TOSH_IRP_TABLE[i]] != 0xFF)/*duplicate priorities
! in the table, mark
! for later fixing*/
! DuplicateTable[i] = PriorityTable[TOSH_IRP_TABLE[i]];
! else
! PriorityTable[TOSH_IRP_TABLE[i]] = i;
! }
!
! //compress table
! for(i = 0; i < 40; i++){
! if(PriorityTable[i] != 0xff){
! PriorityTable[usedPriorities] = PriorityTable[i];
! if(i != usedPriorities)
! PriorityTable[i] = 0xFF;
! usedPriorities++;
! }
! }
!
! for(i = 0; i < 40; i++)
! if(DuplicateTable[i] != 0xFF){
! uint8_t j, ExtraTable[40];
! for(j = 0; DuplicateTable[i] != PriorityTable[j]; j++);
! memcpy(ExtraTable + j + 1, PriorityTable + j, usedPriorities - j);
! memcpy(PriorityTable + j + 1, ExtraTable + j + 1,
! usedPriorities - j);
! PriorityTable[j] = i;
! usedPriorities++;
! }
!
! for(i = 0; i < usedPriorities; i++){
! IPR(i) = (IPR_VALID | PriorityTable[i]);
! tmp = IPR(i);
! }
! }
!
! if (id < 34){
! if(priority == 0xff){
! priority = usedPriorities;
! usedPriorities++;
! IPR(priority) = (IPR_VALID | (id));
! tmp = IPR(priority);
! }
! if (level) {
! _ICLR(id) |= _PPID_Bit(id);
! tmp = _ICLR(id);
! }
!
! error = SUCCESS;
! }
! }
! return error;
! }
!
! void enable(uint8_t id)
! {
! uint32_t tmp;
! atomic {
! if (id < 34) {
! _ICMR(id) |= _PPID_Bit(id);
! tmp = _ICMR(id);
! }
! }
! return;
! }
!
! void disable(uint8_t id)
! {
! uint32_t tmp;
! atomic {
! if (id < 34) {
! _ICMR(id) &= ~(_PPID_Bit(id));
! tmp = _ICMR(id);
! }
! }
! return;
! }
!
! /* Interface implementation */
!
! async command error_t PXA27xIrq.allocate[uint8_t id]()
! {
! return allocate(id, FALSE, TOSH_IRP_TABLE[id]);
! }
!
! async command void PXA27xIrq.enable[uint8_t id]()
! {
! enable(id);
! return;
! }
!
! async command void PXA27xIrq.disable[uint8_t id]()
! {
! disable(id);
! return;
! }
!
! async command void HplPXA27xInterruptCntl.setICCR_DIM(bool flag) {
!
! if (flag) {
! ICCR |= ICCR_DIM;
! }
! else {
! ICCR = 0;
! }
! return;
!
! }
!
! async command bool HplPXA27xInterruptCntl.getICCR_DIM() {
! bool result = FALSE;
!
! if (ICCR & ICCR_DIM) {
! result = TRUE;
! }
!
! return result;
! }
!
! default async event void PXA27xIrq.fired[uint8_t id]()
! {
! return;
! }
!
! }
Index: pxa27x_util.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/pxa27x_util.s,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** pxa27x_util.s 12 Jul 2006 17:01:51 -0000 1.2
--- pxa27x_util.s 11 Jun 2008 00:42:13 -0000 1.3
***************
*** 1,255 ****
!
! .macro CPWAIT Rd
! MRC P15, 0, \Rd, C2, C0, 0 @ arbitrary read of CP15 into register Rd
! MOV \Rd, \Rd @ wait for it (foward dependency)
! SUB PC, PC, #4 @ branch to next instruction
! .endm
!
!
! .macro ALLOCATE Rd
! MCR P15, 0, \Rd, C7, C2, 5 @ perform line allocation based on Rd
! .endm
! @@@@@@@@@@@@@@@@@@@@@@@@@
! @ to create an assembly function that confirms to AAPCS (or so I think ;o)
! @ .func function name
! @ STMFD R13!, {R4 - R12, LR}..alternatively STMFD R13!, {registers used, LR}
! @ {function body}
! @ LDMFD R13!, {R4 - R12, PC}...must match above with LR replaced by PC
! @ .endfunc
! @@@@@@@@@@@@@@@@@@@@@@@@@@
!
! @whether WT or WB is used is determined in mmu_table.s
! .extern MMUTable
!
! .equ MEMORY_CONFIG_BASE,(0x48000000)
! .equ FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode
! @.equ FLASH_SYNC_value, (0x25C2<<1) @ Value to set flash into burst 8 sync mode
! .equ FLASH_WRITE,(0x0060) @ Code for writing to flash
! .equ FLASH_READSTATUS,(0x0070) @ Code for reading status
! .equ FLASH_WCONF,(0x0003) @ Code to confirm write to flash
! .equ FLASH_READ,(0x00FF) @ Code to place flash in read mode
! .equ SXCNFG_sync_value,(0x7011) @ SXCNFG value for burst16 sync flash operation
! @ .equ SXCNFG_sync_value,(0x6011) @ SXCNFG value for burst8 sync flash operation
! .equ SXCNFG_offset,(0x1c)
!
! .global initMMU
! .global initSyncFlash
! .global enableICache
! .global enableDCache
! .global disableDCache
! .global invalidateDCache
! .global cleanDCache
! .global globalCleanAndInvalidateDCache
!
! initSyncFlash:
! @this function MUST be called after the ICACHE is initialized to work correctly!!!
! @also, the DCache being on in WB mode will possibly cause this to randomly FAIL!
! .func initSyncFlash
! STMFD R13!, {R4 - R7, LR}
! ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base
! ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register
! ldr r3, =FLASH_WRITE @ Write to flash instruction
! ldr r4, =FLASH_WCONF @ Write to flash confirm instruction
! ldr r5, =FLASH_READ @ Load "read array" mode command
! ldr r6, =0x0 @ Boot ROM Flash Base address
! ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now
! b goSyncFlash
!
! @align on cache line so that we fetch the next 8 instructions...
! .align 5
! goSyncFlash:
! @ Now program everything into the Flash and SXCNFG registers
! str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register
! strh r3, [r2] @ Yes, the data is on the address bus!
! strh r4, [r2] @ Confirm the write to the RCR
! strh r5, [r6] @ Place flash back in read mode
! ldrh r5, [r6] @ Create a data dependency stall to guarantee write
! nop @ go to the end of the cache line
! nop
! nop
! LDMFD R13!, {R4 - R7, PC}
! .endfunc
!
! @assembly routine to init our MMU
! initMMU:
! .func initMMU
! MRC P15,0,R0,C3,C0,0 @read the domain register into R0
! ORR R0, R0, #0xFF @make sure that we completely enable domain 0
! MCR P15,0,R0,C3,C0,0 @write the domain register
! CPWAIT R0 @be anal and make sure it completes
!
! @time to setup the page table base register
! @LDR R0, =MMUTable @move the table we want into R0
! MCR P15, 0, R0, C2, C0 @save it
! CPWAIT R0 @wait it
!
! @time to enable the MMU!
! MRC P15,0,R0,C1,C0,0 @get CP15 register 1
! ORR R0, R0, #0x1 @set the MMU enable bit
! MCR P15,0,R0,C1,C0,0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
! enableICache:
! .func enableICache
! @icache section
! @globally unlock the icache
! MCR P15, 0, R0, C9, C1, 1
! CPWAIT R0
!
! @globally unlock the itlb
! MCR P15, 0, R0, C10, C4, 1
! CPWAIT R0
!
! @invalidate just the icache and BTB....write to P15 C7, C5, 0
! MCR P15, 0, R0, C7, C5, 0
! CPWAIT R0
!
! @invalidate the iTLB...write to P15 C8, C5, 0
! MCR P15, 0, R0, c8, c5, 0 @save it
! CPWAIT R0 @wait it
!
! @Enable instruction cache
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! ORR R0, R0, #0x1000 @set the icache bit
! MCR P15, 0, R0, C1, C0, 0 @wait it
! CPWAIT R0
!
! @enable the BTB
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! ORR R0, R0, #0x800 @set the btb enable bit
! MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
!
! enableDCache:
! .func enableDCache
! @globally unlock the dtlb
! MCR P15, 0, R0, c10, c8, 1
! CPWAIT R0
!
! @globally unlock the dcache
! MCR P15, 0, R0, C9, c2, 1
! CPWAIT R0
!
! @first invalidate dcache and mini-dcache
! MCR P15, 0, R0, C7, C6, 0
! CPWAIT R0
!
! @invalidate the dTLB...write to P15 C8, C6, 0
! MCR P15, 0, R0, C8, C6, 0 @save it
! CPWAIT R0 @wait it
!
!
! @ now, enable data cache
! MCR P15, 0, R0, C7, C10, 4 @drain write buffer
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! ORR R0, R0, #0x4 @set the dcache enable bit
! MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
! disableDCache:
! .func disableDCache
! @since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency
! @globally unlock the dcache
! STMFD R13!, {R0, LR}
! MCR P15, 0, R0, C9, c2, 1
! CPWAIT R0
!
! @globally clean and invalidate the cache
! bl globalCleanAndInvalidateDCache
!
! @ now, disable data cache
! MCR P15, 0, R0, C7, C10, 4 @drain write buffer
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! BIC R0, R0, #0x4 @clear the dcache enable bit
! MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! LDMFD R13!, {R0, LR}
! .endfunc
!
! @function to invalidate the DCCache for a given Buffer
! @funtion take 2 parameters
! @R0 = base virtual address to evict
! @R1 = number of bytes to evict...cache line is 32 bytes
! invalidateDCache:
! .func invalidateDCache
! CMPS R1,#0 @check that we're greater than 0
! MOVLE PC, LR @return if not
! invalidateDCacheLoop:
! MCR P15, 0, R0, C7, C6, 1 @invalidate this line
! SUBS R1, R1, #32 @subtract out 32 w/CPSR update
! ADD R0, R0, #32 @add 32 to the address w/o CPSR update
! BGT invalidateDCacheLoop @rerun if subtract is greater than
! MOV PC, LR
! .endfunc
!
! @function to clean the DCCache for a given Buffer
! @if a line is dirty, it will be cleaned...i.e. written back to memory in WB mode
! @funtion take 2 parameters
! @R0 = base virtual address to evict
! @R1 = number of bytes to evict...cache line is 32 bytes
! cleanDCache:
! .func cleanDCache
! CMPS R1,#0 @check that we're greater than 0
! MOVLE PC, LR @return if not
! cleanDCacheLoop:
! MCR P15, 0, R0, C7, C10, 1 @clean this line
! SUBS R1, R1, #32 @subtract out 32 w/CPSR update
! ADD R0, R0, #32 @add 32 to the address w/o CPSR update
! BGT cleanDCacheLoop @rerun if subtract is greater than
! MCR P15, 0, R0, C7, C10, 4 @drain write buffer
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
!
! @Global Clean/Invalidate THE DATA CACHE
! @R1 contains the virtual address of a region of cacheable memory reserved for
! @this clean operation
! @R0 is the loop count; Iterate 1024 times which is the number of lines in the
! @data cache
!
! globalCleanAndInvalidateDCache:
! .func globalCleanAndInvalidateDCache
! @note, this function assumes that we will NEVER have anything physical at
! @address 0x04000000 corresponds to static chip select 1
! STMFD R13!, {R0 - R3, LR}
! LDR R1, =0x04000000
! MOV R0, #1024
! LOOP1:
!
! ALLOCATE R1 @ Allocate a line at the virtual address
! @ specified by R1.
! SUBS R0, R0, #1 @ Decrement loop count
! ADD R1, R1, #32 @ Increment the address in R1 to the next cache line
! BNE LOOP1
!
! @Clean the Mini-data Cache
! @ Can’t use line-allocate command, so cycle 2KB of unused data through.
! @ R2 contains the virtual address of a region of cacheable memory reserved for
! @ cleaning the Mini-data Cache
! @ R0 is the loop count; Iterate 64 times which is the number of lines in the
! @ Mini-data Cache.
!
! @note, this function assumes that we will NEVER have anything physical at
! @address 0x05000000 corresponds to static chip select 1
! LDR R2, =0x05000000
! MOV R0, #64
! LOOP2:
! SUBS R0, R0, #1 @ Decrement loop count
! LDR R3,[R2],#32 @ Load and increment to next cache line
! BNE LOOP2
!
! @ Invalidate the data cache and mini-data cache
! MCR P15, 0, R0, C7, C6, 0
! LDMFD R13!, {R0 - R3, PC}
! .endfunc
!
! .end
\ No newline at end of file
--- 1,255 ----
!
! .macro CPWAIT Rd
! MRC P15, 0, \Rd, C2, C0, 0 @ arbitrary read of CP15 into register Rd
! MOV \Rd, \Rd @ wait for it (foward dependency)
! SUB PC, PC, #4 @ branch to next instruction
! .endm
!
!
! .macro ALLOCATE Rd
! MCR P15, 0, \Rd, C7, C2, 5 @ perform line allocation based on Rd
! .endm
! @@@@@@@@@@@@@@@@@@@@@@@@@
! @ to create an assembly function that confirms to AAPCS (or so I think ;o)
! @ .func function name
! @ STMFD R13!, {R4 - R12, LR}..alternatively STMFD R13!, {registers used, LR}
! @ {function body}
! @ LDMFD R13!, {R4 - R12, PC}...must match above with LR replaced by PC
! @ .endfunc
! @@@@@@@@@@@@@@@@@@@@@@@@@@
!
! @whether WT or WB is used is determined in mmu_table.s
! .extern MMUTable
!
! .equ MEMORY_CONFIG_BASE,(0x48000000)
! .equ FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode
! @.equ FLASH_SYNC_value, (0x25C2<<1) @ Value to set flash into burst 8 sync mode
! .equ FLASH_WRITE,(0x0060) @ Code for writing to flash
! .equ FLASH_READSTATUS,(0x0070) @ Code for reading status
! .equ FLASH_WCONF,(0x0003) @ Code to confirm write to flash
! .equ FLASH_READ,(0x00FF) @ Code to place flash in read mode
! .equ SXCNFG_sync_value,(0x7011) @ SXCNFG value for burst16 sync flash operation
! @ .equ SXCNFG_sync_value,(0x6011) @ SXCNFG value for burst8 sync flash operation
! .equ SXCNFG_offset,(0x1c)
!
! .global initMMU
! .global initSyncFlash
! .global enableICache
! .global enableDCache
! .global disableDCache
! .global invalidateDCache
! .global cleanDCache
! .global globalCleanAndInvalidateDCache
!
! initSyncFlash:
! @this function MUST be called after the ICACHE is initialized to work correctly!!!
! @also, the DCache being on in WB mode will possibly cause this to randomly FAIL!
! .func initSyncFlash
! STMFD R13!, {R4 - R7, LR}
! ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base
! ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register
! ldr r3, =FLASH_WRITE @ Write to flash instruction
! ldr r4, =FLASH_WCONF @ Write to flash confirm instruction
! ldr r5, =FLASH_READ @ Load "read array" mode command
! ldr r6, =0x0 @ Boot ROM Flash Base address
! ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now
! b goSyncFlash
!
! @align on cache line so that we fetch the next 8 instructions...
! .align 5
! goSyncFlash:
! @ Now program everything into the Flash and SXCNFG registers
! str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register
! strh r3, [r2] @ Yes, the data is on the address bus!
! strh r4, [r2] @ Confirm the write to the RCR
! strh r5, [r6] @ Place flash back in read mode
! ldrh r5, [r6] @ Create a data dependency stall to guarantee write
! nop @ go to the end of the cache line
! nop
! nop
! LDMFD R13!, {R4 - R7, PC}
! .endfunc
!
! @assembly routine to init our MMU
! initMMU:
! .func initMMU
! MRC P15,0,R0,C3,C0,0 @read the domain register into R0
! ORR R0, R0, #0xFF @make sure that we completely enable domain 0
! MCR P15,0,R0,C3,C0,0 @write the domain register
! CPWAIT R0 @be anal and make sure it completes
!
! @time to setup the page table base register
! @LDR R0, =MMUTable @move the table we want into R0
! MCR P15, 0, R0, C2, C0 @save it
! CPWAIT R0 @wait it
!
! @time to enable the MMU!
! MRC P15,0,R0,C1,C0,0 @get CP15 register 1
! ORR R0, R0, #0x1 @set the MMU enable bit
! MCR P15,0,R0,C1,C0,0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
! enableICache:
! .func enableICache
! @icache section
! @globally unlock the icache
! MCR P15, 0, R0, C9, C1, 1
! CPWAIT R0
!
! @globally unlock the itlb
! MCR P15, 0, R0, C10, C4, 1
! CPWAIT R0
!
! @invalidate just the icache and BTB....write to P15 C7, C5, 0
! MCR P15, 0, R0, C7, C5, 0
! CPWAIT R0
!
! @invalidate the iTLB...write to P15 C8, C5, 0
! MCR P15, 0, R0, c8, c5, 0 @save it
! CPWAIT R0 @wait it
!
! @Enable instruction cache
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! ORR R0, R0, #0x1000 @set the icache bit
! MCR P15, 0, R0, C1, C0, 0 @wait it
! CPWAIT R0
!
! @enable the BTB
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! ORR R0, R0, #0x800 @set the btb enable bit
! MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
!
! enableDCache:
! .func enableDCache
! @globally unlock the dtlb
! MCR P15, 0, R0, c10, c8, 1
! CPWAIT R0
!
! @globally unlock the dcache
! MCR P15, 0, R0, C9, c2, 1
! CPWAIT R0
!
! @first invalidate dcache and mini-dcache
! MCR P15, 0, R0, C7, C6, 0
! CPWAIT R0
!
! @invalidate the dTLB...write to P15 C8, C6, 0
! MCR P15, 0, R0, C8, C6, 0 @save it
! CPWAIT R0 @wait it
!
!
! @ now, enable data cache
! MCR P15, 0, R0, C7, C10, 4 @drain write buffer
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! ORR R0, R0, #0x4 @set the dcache enable bit
! MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
! disableDCache:
! .func disableDCache
! @since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency
! @globally unlock the dcache
! STMFD R13!, {R0, LR}
! MCR P15, 0, R0, C9, c2, 1
! CPWAIT R0
!
! @globally clean and invalidate the cache
! bl globalCleanAndInvalidateDCache
!
! @ now, disable data cache
! MCR P15, 0, R0, C7, C10, 4 @drain write buffer
! MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
! BIC R0, R0, #0x4 @clear the dcache enable bit
! MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! LDMFD R13!, {R0, LR}
! .endfunc
!
! @function to invalidate the DCCache for a given Buffer
! @funtion take 2 parameters
! @R0 = base virtual address to evict
! @R1 = number of bytes to evict...cache line is 32 bytes
! invalidateDCache:
! .func invalidateDCache
! CMPS R1,#0 @check that we're greater than 0
! MOVLE PC, LR @return if not
! invalidateDCacheLoop:
! MCR P15, 0, R0, C7, C6, 1 @invalidate this line
! SUBS R1, R1, #32 @subtract out 32 w/CPSR update
! ADD R0, R0, #32 @add 32 to the address w/o CPSR update
! BGT invalidateDCacheLoop @rerun if subtract is greater than
! MOV PC, LR
! .endfunc
!
! @function to clean the DCCache for a given Buffer
! @if a line is dirty, it will be cleaned...i.e. written back to memory in WB mode
! @funtion take 2 parameters
! @R0 = base virtual address to evict
! @R1 = number of bytes to evict...cache line is 32 bytes
! cleanDCache:
! .func cleanDCache
! CMPS R1,#0 @check that we're greater than 0
! MOVLE PC, LR @return if not
! cleanDCacheLoop:
! MCR P15, 0, R0, C7, C10, 1 @clean this line
! SUBS R1, R1, #32 @subtract out 32 w/CPSR update
! ADD R0, R0, #32 @add 32 to the address w/o CPSR update
! BGT cleanDCacheLoop @rerun if subtract is greater than
! MCR P15, 0, R0, C7, C10, 4 @drain write buffer
! CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
!
! @Global Clean/Invalidate THE DATA CACHE
! @R1 contains the virtual address of a region of cacheable memory reserved for
! @this clean operation
! @R0 is the loop count; Iterate 1024 times which is the number of lines in the
! @data cache
!
! globalCleanAndInvalidateDCache:
! .func globalCleanAndInvalidateDCache
! @note, this function assumes that we will NEVER have anything physical at
! @address 0x04000000 corresponds to static chip select 1
! STMFD R13!, {R0 - R3, LR}
! LDR R1, =0x04000000
! MOV R0, #1024
! LOOP1:
!
! ALLOCATE R1 @ Allocate a line at the virtual address
! @ specified by R1.
! SUBS R0, R0, #1 @ Decrement loop count
! ADD R1, R1, #32 @ Increment the address in R1 to the next cache line
! BNE LOOP1
!
! @Clean the Mini-data Cache
! @ CanÆt use line-allocate command, so cycle 2KB of unused data through.
! @ R2 contains the virtual address of a region of cacheable memory reserved for
! @ cleaning the Mini-data Cache
! @ R0 is the loop count; Iterate 64 times which is the number of lines in the
! @ Mini-data Cache.
!
! @note, this function assumes that we will NEVER have anything physical at
! @address 0x05000000 corresponds to static chip select 1
! LDR R2, =0x05000000
! MOV R0, #64
! LOOP2:
! SUBS R0, R0, #1 @ Decrement loop count
! LDR R3,[R2],#32 @ Load and increment to next cache line
! BNE LOOP2
!
! @ Invalidate the data cache and mini-data cache
! MCR P15, 0, R0, C7, C6, 0
! LDMFD R13!, {R0 - R3, PC}
! .endfunc
!
! .end
\ No newline at end of file
Index: arm_defs.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/arm_defs.h,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** arm_defs.h 12 Jul 2006 17:01:51 -0000 1.2
--- arm_defs.h 11 Jun 2008 00:42:13 -0000 1.3
***************
*** 1,70 ****
! /* tab:4
! * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
! * downloading, copying, installing or using the software you agree to
! * this license. If you do not agree to this license, do not download,
! * install, copy or use the software.
! *
! * Intel Open Source License
! *
! * Copyright (c) 2002 Intel Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! *
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! * Neither the name of the Intel Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
! * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
! * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
! * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
! * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
! * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
! * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! *
! *
! */
! /*
! *
! * Authors: Philip Buonadonna
! *
! *
! */
!
! #ifndef _ARM_DEFS_H
! #define _ARM_DEFS_H
!
! #define ARM_CPSR_MODE_MASK (0x0000001F)
! #define ARM_CPSR_INT_MASK (0x000000C0)
! #define ARM_CPSR_COND_MASK (0xF8000000)
!
! #define ARM_CPSR_MODE_USR (0x10)
! #define ARM_CPSR_MODE_FIQ (0x11)
! #define ARM_CPSR_MODE_IRQ (0x12)
! #define ARM_CPSR_MODE_SVC (0x13)
! #define ARM_CPSR_MODE_ABT (0x17)
! #define ARM_CPSR_MODE_UND (0x1B)
! #define ARM_CPSR_MODE_SYS (0x1F)
!
! #define ARM_CPSR_BIT_N (1 << 31)
! #define ARM_CPSR_BIT_Z (1 << 30)
! #define ARM_CPSR_BIT_C (1 << 29)
! #define ARM_CPSR_BIT_V (1 << 28)
! #define ARM_CPSR_BIT_Q (1 << 27)
!
! #define ARM_CPSR_BIT_I (1 << 7)
! #define ARM_CPSR_BIT_F (1 << 6)
! #define ARM_CPRS_BIT_T (1 << 5)
!
! #endif /*_ARM_DEFS_H */
--- 1,70 ----
! /* tab:4
! * IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
! * downloading, copying, installing or using the software you agree to
! * this license. If you do not agree to this license, do not download,
! * install, copy or use the software.
! *
! * Intel Open Source License
! *
! * Copyright (c) 2002 Intel Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! *
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! * Neither the name of the Intel Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
! * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
! * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
! * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
! * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
! * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
! * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
! * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
! * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
! *
! *
! */
! /*
! *
! * Authors: Philip Buonadonna
! *
! *
! */
!
! #ifndef _ARM_DEFS_H
! #define _ARM_DEFS_H
!
! #define ARM_CPSR_MODE_MASK (0x0000001F)
! #define ARM_CPSR_INT_MASK (0x000000C0)
! #define ARM_CPSR_COND_MASK (0xF8000000)
!
! #define ARM_CPSR_MODE_USR (0x10)
! #define ARM_CPSR_MODE_FIQ (0x11)
! #define ARM_CPSR_MODE_IRQ (0x12)
! #define ARM_CPSR_MODE_SVC (0x13)
! #define ARM_CPSR_MODE_ABT (0x17)
! #define ARM_CPSR_MODE_UND (0x1B)
! #define ARM_CPSR_MODE_SYS (0x1F)
!
! #define ARM_CPSR_BIT_N (1 << 31)
! #define ARM_CPSR_BIT_Z (1 << 30)
! #define ARM_CPSR_BIT_C (1 << 29)
! #define ARM_CPSR_BIT_V (1 << 28)
! #define ARM_CPSR_BIT_Q (1 << 27)
!
! #define ARM_CPSR_BIT_I (1 << 7)
! #define ARM_CPSR_BIT_F (1 << 6)
! #define ARM_CPRS_BIT_T (1 << 5)
!
! #endif /*_ARM_DEFS_H */
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