[Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/pxa27x/ssp HplPXA27xSSP1C.nc, 1.3, 1.4 HplPXA27xSSP3C.nc, 1.3, 1.4 HplPXA27xSSP.nc, 1.4, 1.5 HalPXA27xSpiPioM.nc, 1.5, 1.6 HplPXA27xSSPP.nc, 1.4, 1.5 HalPXA27xSpiDMAM.nc, 1.4, 1.5 HplPXA27xSSP2C.nc, 1.3, 1.4
Razvan Musaloiu-E.
razvanm at users.sourceforge.net
Tue Jun 10 17:42:15 PDT 2008
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Update of /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv9551/chips/pxa27x/ssp
Modified Files:
HplPXA27xSSP1C.nc HplPXA27xSSP3C.nc HplPXA27xSSP.nc
HalPXA27xSpiPioM.nc HplPXA27xSSPP.nc HalPXA27xSpiDMAM.nc
HplPXA27xSSP2C.nc
Log Message:
Convert to Unix-style line terminators.
Index: HplPXA27xSSP1C.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HplPXA27xSSP1C.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** HplPXA27xSSP1C.nc 7 Nov 2006 19:31:14 -0000 1.3
--- HplPXA27xSSP1C.nc 11 Jun 2008 00:42:13 -0000 1.4
***************
*** 1,59 ****
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! configuration HplPXA27xSSP1C
! {
! provides {
! interface HplPXA27xSSP;
! interface HplPXA27xDMAInfo as SSPRxDMAReg;
! interface HplPXA27xDMAInfo as SSPTxDMAReg;
! }
! }
!
! implementation
! {
! components HplPXA27xSSPP;
! components HplPXA27xInterruptM;
! components PlatformP;
!
! HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[1];
! components new HplPXA27xDMAInfoC(13, (uint32_t)&SSDR_1) as SSPRxDMA;
! components new HplPXA27xDMAInfoC(14, (uint32_t)&SSDR_1) as SSPTxDMA;
! SSPRxDMAReg = SSPRxDMA;
! SSPTxDMAReg = SSPTxDMA;
!
! HplPXA27xSSPP.Init[1] <- PlatformP.InitL1;
!
! HplPXA27xSSPP.SSP1Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP1];
! }
--- 1,59 ----
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! configuration HplPXA27xSSP1C
! {
! provides {
! interface HplPXA27xSSP;
! interface HplPXA27xDMAInfo as SSPRxDMAReg;
! interface HplPXA27xDMAInfo as SSPTxDMAReg;
! }
! }
!
! implementation
! {
! components HplPXA27xSSPP;
! components HplPXA27xInterruptM;
! components PlatformP;
!
! HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[1];
! components new HplPXA27xDMAInfoC(13, (uint32_t)&SSDR_1) as SSPRxDMA;
! components new HplPXA27xDMAInfoC(14, (uint32_t)&SSDR_1) as SSPTxDMA;
! SSPRxDMAReg = SSPRxDMA;
! SSPTxDMAReg = SSPTxDMA;
!
! HplPXA27xSSPP.Init[1] <- PlatformP.InitL1;
!
! HplPXA27xSSPP.SSP1Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP1];
! }
Index: HplPXA27xSSP3C.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HplPXA27xSSP3C.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** HplPXA27xSSP3C.nc 7 Nov 2006 19:31:14 -0000 1.3
--- HplPXA27xSSP3C.nc 11 Jun 2008 00:42:13 -0000 1.4
***************
*** 1,59 ****
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! configuration HplPXA27xSSP3C
! {
! provides {
! interface HplPXA27xSSP;
! interface HplPXA27xDMAInfo as SSPRxDMAInfo;
! interface HplPXA27xDMAInfo as SSPTxDMAInfo;
! }
! }
!
! implementation
! {
! components HplPXA27xSSPP;
! components HplPXA27xInterruptM;
! components PlatformP;
!
! HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[3];
! components new HplPXA27xDMAInfoC(66, (uint32_t)&SSDR_3) as SSPRxDMA;
! components new HplPXA27xDMAInfoC(67, (uint32_t)&SSDR_3) as SSPTxDMA;
! SSPRxDMAInfo = SSPRxDMA;
! SSPTxDMAInfo = SSPTxDMA;
!
! HplPXA27xSSPP.Init[3] <- PlatformP.InitL1;
!
! HplPXA27xSSPP.SSP3Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP3];
! }
--- 1,59 ----
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! configuration HplPXA27xSSP3C
! {
! provides {
! interface HplPXA27xSSP;
! interface HplPXA27xDMAInfo as SSPRxDMAInfo;
! interface HplPXA27xDMAInfo as SSPTxDMAInfo;
! }
! }
!
! implementation
! {
! components HplPXA27xSSPP;
! components HplPXA27xInterruptM;
! components PlatformP;
!
! HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[3];
! components new HplPXA27xDMAInfoC(66, (uint32_t)&SSDR_3) as SSPRxDMA;
! components new HplPXA27xDMAInfoC(67, (uint32_t)&SSDR_3) as SSPTxDMA;
! SSPRxDMAInfo = SSPRxDMA;
! SSPTxDMAInfo = SSPTxDMA;
!
! HplPXA27xSSPP.Init[3] <- PlatformP.InitL1;
!
! HplPXA27xSSPP.SSP3Irq -> HplPXA27xInterruptM.PXA27xIrq[PPID_SSP3];
! }
Index: HplPXA27xSSP.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HplPXA27xSSP.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HplPXA27xSSP.nc 12 Dec 2006 18:23:12 -0000 1.4
--- HplPXA27xSSP.nc 11 Jun 2008 00:42:13 -0000 1.5
***************
*** 1,72 ****
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
! interface HplPXA27xSSP
! {
! async command void setSSCR0(uint32_t val);
! async command uint32_t getSSCR0();
!
! async command void setSSCR1(uint32_t val);
! async command uint32_t getSSCR1();
!
! async command void setSSSR(uint32_t val);
! async command uint32_t getSSSR();
!
! async command void setSSITR(uint32_t val);
! async command uint32_t getSSITR();
!
! async command void setSSDR(uint32_t val);
! async command uint32_t getSSDR();
!
! async command void setSSTO(uint32_t val);
! async command uint32_t getSSTO();
!
! async command void setSSPSP(uint32_t val);
! async command uint32_t getSSPSP();
!
! async command void setSSTSA(uint32_t val);
! async command uint32_t getSSTSA();
!
! async command void setSSRSA(uint32_t val);
! async command uint32_t getSSRSA();
!
! async command void setSSTSS(uint32_t val);
! async command uint32_t getSSTSS();
!
! async command void setSSACD(uint32_t val);
! async command uint32_t getSSACD();
!
! async event void interruptSSP();
!
! }
--- 1,72 ----
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
! interface HplPXA27xSSP
! {
! async command void setSSCR0(uint32_t val);
! async command uint32_t getSSCR0();
!
! async command void setSSCR1(uint32_t val);
! async command uint32_t getSSCR1();
!
! async command void setSSSR(uint32_t val);
! async command uint32_t getSSSR();
!
! async command void setSSITR(uint32_t val);
! async command uint32_t getSSITR();
!
! async command void setSSDR(uint32_t val);
! async command uint32_t getSSDR();
!
! async command void setSSTO(uint32_t val);
! async command uint32_t getSSTO();
!
! async command void setSSPSP(uint32_t val);
! async command uint32_t getSSPSP();
!
! async command void setSSTSA(uint32_t val);
! async command uint32_t getSSTSA();
!
! async command void setSSRSA(uint32_t val);
! async command uint32_t getSSRSA();
!
! async command void setSSTSS(uint32_t val);
! async command uint32_t getSSTSS();
!
! async command void setSSACD(uint32_t val);
! async command uint32_t getSSACD();
!
! async event void interruptSSP();
!
! }
Index: HalPXA27xSpiPioM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HalPXA27xSpiPioM.nc,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** HalPXA27xSpiPioM.nc 27 May 2008 17:28:32 -0000 1.5
--- HalPXA27xSpiPioM.nc 11 Jun 2008 00:42:13 -0000 1.6
***************
*** 1,213 ****
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.
! * Provides master mode communication for a variety of frame formats, speeds
! * and data sizes.
! *
! * @param valFRF The frame format to use.
! *
! * @param valSCR The value for the SSP clock rate.
! *
! * @param valDSS The value for the DSS field in the SSCR0 register of the
! * associated SSP peripheral.
! *
! * @param enableRWOT Enables Receive without transmit mode. Used only for
! * the SpiPacket interface. If the txBuf parameter of SpiPacket.send is null
! * the implementation will continuously clock in data without regard to the
! * contents of the TX FIFO. This is different from the spec for the interface
! * which requires that the transmitter send zeros (0) for this case.
! *
! * @author Phil Buonadonna
! * @author Miklos Maroti, Brano Kusy
! */
!
! generic module HalPXA27xSpiPioM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT)
! {
! provides {
! interface Init;
! interface SpiByte;
! interface SpiPacket[uint8_t instance];
! }
! uses {
! interface HplPXA27xSSP as SSP;
! }
! }
!
! implementation
! {
! enum{
! FLAGS_SSCR0 = SSCR0_SCR(valSCR) | SSCR0_FRF(/*0*/valFRF) | SSCR0_DSS(valDSS),
! FLAGS_SSCR1 = 0
! };
!
! // The BitBuckets need to be 8 bytes.
! norace unsigned long long txBitBucket, rxBitBucket;
! norace uint8_t *txCurrentBuf, *rxCurrentBuf, *txPtr, *rxPtr;
! norace uint8_t txInc, rxInc;
! norace uint8_t instanceCurrent;
! uint32_t lenCurrent, lenRemain;
!
! command error_t Init.init() {
!
! txBitBucket = 0, rxBitBucket = 0;
! txCurrentBuf = rxCurrentBuf = NULL;
! lenCurrent = 0 ;
! instanceCurrent = 0;
! atomic lenRemain = 0;
!
! call SSP.setSSCR1(FLAGS_SSCR1);
! call SSP.setSSTO(3500 /*96*8*/);
! call SSP.setSSCR0(FLAGS_SSCR0);
! call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
!
! return SUCCESS;
! }
!
! async command uint8_t SpiByte.write(uint8_t tx) {
! volatile uint8_t val;
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! call SSP.getSSDR();
! }
! #endif
! call SSP.setSSDR(tx);
!
! while ((call SSP.getSSSR()) & SSSR_BSY);
!
! val = call SSP.getSSDR();
!
! return val;
! }
!
! async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {
! uint32_t i;
!
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! call SSP.getSSDR();
! }
! #endif
!
! txCurrentBuf = txBuf;
! rxCurrentBuf = rxBuf;
! atomic lenCurrent = lenRemain = len;
! instanceCurrent = instance;
!
! if (rxBuf == NULL) {
! rxPtr = (uint8_t *)&rxBitBucket;
! rxInc = 0;
! }
! else {
! rxPtr = rxBuf;
! rxInc = 1;
! }
!
! if (txBuf == NULL) {
! txPtr = (uint8_t *)&txBitBucket;
! txInc = 0;
! }
! else {
! txPtr = txBuf;
! txInc = 1;
! }
!
! if ((txBuf == NULL) && (enableRWOT == TRUE)) {
! call SSP.setSSCR0(FLAGS_SSCR0);
! call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_RWOT);
! call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
! while (len > 0) {
! while (!(call SSP.getSSSR() & SSSR_RNE));
! *rxPtr = call SSP.getSSDR();
! rxPtr += rxInc;
! len--;
! }
! call SSP.setSSCR0(FLAGS_SSCR0);
! call SSP.setSSCR1(FLAGS_SSCR1);
! call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
! }
! else {
! uint8_t burst = (len < 16) ? len : 16;
! for (i = 0;i < burst; i++) {
! call SSP.setSSDR(*txPtr);
! txPtr += txInc;
! }
! call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_TINTE | SSCR1_RIE);
! }
!
! return SUCCESS;
! }
!
! async event void SSP.interruptSSP() {
! uint32_t i, uiStatus, uiFifoLevel;
! uint32_t burst;
!
! uiStatus = call SSP.getSSSR();
! call SSP.setSSSR(SSSR_TINT);
!
! uiFifoLevel = (((uiStatus & SSSR_RFL) >> 12) | 0xF) + 1;
! uiFifoLevel = (uiFifoLevel > lenRemain) ? lenRemain : uiFifoLevel;
!
! if( !(uiStatus & SSSR_RNE))
! return;
!
! for (i = 0; i < uiFifoLevel; i++) {
! *rxPtr = call SSP.getSSDR();
! rxPtr += rxInc;
! }
!
! atomic {
! lenRemain -= uiFifoLevel;
! burst = (lenRemain < 16) ? lenRemain : 16;
! }
!
! if (burst > 0) {
! for (i = 0;i < burst;i++) {
! call SSP.setSSDR(*txPtr);
! txPtr += txInc;
! }
! }
! else {
! uint32_t len = lenCurrent;
! call SSP.setSSCR1(FLAGS_SSCR1);
! lenCurrent = 0;
! signal SpiPacket.sendDone[instanceCurrent](txCurrentBuf, rxCurrentBuf,len,SUCCESS);
! }
!
! return;
! }
!
! default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf,
! uint16_t len, error_t error) {
! return;
! }
!
! }
--- 1,213 ----
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.
! * Provides master mode communication for a variety of frame formats, speeds
! * and data sizes.
! *
! * @param valFRF The frame format to use.
! *
! * @param valSCR The value for the SSP clock rate.
! *
! * @param valDSS The value for the DSS field in the SSCR0 register of the
! * associated SSP peripheral.
! *
! * @param enableRWOT Enables Receive without transmit mode. Used only for
! * the SpiPacket interface. If the txBuf parameter of SpiPacket.send is null
! * the implementation will continuously clock in data without regard to the
! * contents of the TX FIFO. This is different from the spec for the interface
! * which requires that the transmitter send zeros (0) for this case.
! *
! * @author Phil Buonadonna
! * @author Miklos Maroti, Brano Kusy
! */
!
! generic module HalPXA27xSpiPioM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT)
! {
! provides {
! interface Init;
! interface SpiByte;
! interface SpiPacket[uint8_t instance];
! }
! uses {
! interface HplPXA27xSSP as SSP;
! }
! }
!
! implementation
! {
! enum{
! FLAGS_SSCR0 = SSCR0_SCR(valSCR) | SSCR0_FRF(/*0*/valFRF) | SSCR0_DSS(valDSS),
! FLAGS_SSCR1 = 0
! };
!
! // The BitBuckets need to be 8 bytes.
! norace unsigned long long txBitBucket, rxBitBucket;
! norace uint8_t *txCurrentBuf, *rxCurrentBuf, *txPtr, *rxPtr;
! norace uint8_t txInc, rxInc;
! norace uint8_t instanceCurrent;
! uint32_t lenCurrent, lenRemain;
!
! command error_t Init.init() {
!
! txBitBucket = 0, rxBitBucket = 0;
! txCurrentBuf = rxCurrentBuf = NULL;
! lenCurrent = 0 ;
! instanceCurrent = 0;
! atomic lenRemain = 0;
!
! call SSP.setSSCR1(FLAGS_SSCR1);
! call SSP.setSSTO(3500 /*96*8*/);
! call SSP.setSSCR0(FLAGS_SSCR0);
! call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
!
! return SUCCESS;
! }
!
! async command uint8_t SpiByte.write(uint8_t tx) {
! volatile uint8_t val;
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! call SSP.getSSDR();
! }
! #endif
! call SSP.setSSDR(tx);
!
! while ((call SSP.getSSSR()) & SSSR_BSY);
!
! val = call SSP.getSSDR();
!
! return val;
! }
!
! async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {
! uint32_t i;
!
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! call SSP.getSSDR();
! }
! #endif
!
! txCurrentBuf = txBuf;
! rxCurrentBuf = rxBuf;
! atomic lenCurrent = lenRemain = len;
! instanceCurrent = instance;
!
! if (rxBuf == NULL) {
! rxPtr = (uint8_t *)&rxBitBucket;
! rxInc = 0;
! }
! else {
! rxPtr = rxBuf;
! rxInc = 1;
! }
!
! if (txBuf == NULL) {
! txPtr = (uint8_t *)&txBitBucket;
! txInc = 0;
! }
! else {
! txPtr = txBuf;
! txInc = 1;
! }
!
! if ((txBuf == NULL) && (enableRWOT == TRUE)) {
! call SSP.setSSCR0(FLAGS_SSCR0);
! call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_RWOT);
! call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
! while (len > 0) {
! while (!(call SSP.getSSSR() & SSSR_RNE));
! *rxPtr = call SSP.getSSDR();
! rxPtr += rxInc;
! len--;
! }
! call SSP.setSSCR0(FLAGS_SSCR0);
! call SSP.setSSCR1(FLAGS_SSCR1);
! call SSP.setSSCR0(FLAGS_SSCR0 | SSCR0_SSE);
! }
! else {
! uint8_t burst = (len < 16) ? len : 16;
! for (i = 0;i < burst; i++) {
! call SSP.setSSDR(*txPtr);
! txPtr += txInc;
! }
! call SSP.setSSCR1(FLAGS_SSCR1 | SSCR1_TINTE | SSCR1_RIE);
! }
!
! return SUCCESS;
! }
!
! async event void SSP.interruptSSP() {
! uint32_t i, uiStatus, uiFifoLevel;
! uint32_t burst;
!
! uiStatus = call SSP.getSSSR();
! call SSP.setSSSR(SSSR_TINT);
!
! uiFifoLevel = (((uiStatus & SSSR_RFL) >> 12) | 0xF) + 1;
! uiFifoLevel = (uiFifoLevel > lenRemain) ? lenRemain : uiFifoLevel;
!
! if( !(uiStatus & SSSR_RNE))
! return;
!
! for (i = 0; i < uiFifoLevel; i++) {
! *rxPtr = call SSP.getSSDR();
! rxPtr += rxInc;
! }
!
! atomic {
! lenRemain -= uiFifoLevel;
! burst = (lenRemain < 16) ? lenRemain : 16;
! }
!
! if (burst > 0) {
! for (i = 0;i < burst;i++) {
! call SSP.setSSDR(*txPtr);
! txPtr += txInc;
! }
! }
! else {
! uint32_t len = lenCurrent;
! call SSP.setSSCR1(FLAGS_SSCR1);
! lenCurrent = 0;
! signal SpiPacket.sendDone[instanceCurrent](txCurrentBuf, rxCurrentBuf,len,SUCCESS);
! }
!
! return;
! }
!
! default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf,
! uint16_t len, error_t error) {
! return;
! }
!
! }
Index: HplPXA27xSSPP.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HplPXA27xSSPP.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HplPXA27xSSPP.nc 12 Dec 2006 18:23:12 -0000 1.4
--- HplPXA27xSSPP.nc 11 Jun 2008 00:42:13 -0000 1.5
***************
*** 1,297 ****
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! module HplPXA27xSSPP
! {
! provides {
! interface Init[uint8_t chnl];
! interface HplPXA27xSSP[uint8_t chnl];
! }
! uses {
! interface HplPXA27xInterrupt as SSP1Irq;
! interface HplPXA27xInterrupt as SSP2Irq;
! interface HplPXA27xInterrupt as SSP3Irq;
! }
! }
!
! implementation
! {
!
! command error_t Init.init[uint8_t chnl]() {
! error_t error = SUCCESS;
!
! switch (chnl) {
! case 1:
! CKEN |= CKEN23_SSP1;
! call SSP1Irq.enable();
! break;
! case 2:
! CKEN |= CKEN3_SSP2;
! call SSP2Irq.enable();
! break;
! case 3:
! CKEN |= CKEN4_SSP3;
! //call SSP3Irq.allocate();
! call SSP3Irq.enable();
! break;
! default:
! error = FAIL;
! break;
! }
!
! return error;
! }
!
! async command void HplPXA27xSSP.setSSCR0[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSCR0_1 = val; break;
! case 2: SSCR0_2 = val; break;
! case 3: SSCR0_3 = val; break;
! default: break;
! }
! return;
! }
!
! async command uint32_t HplPXA27xSSP.getSSCR0[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSCR0_1; break;
! case 2: return SSCR0_2; break;
! case 3: return SSCR0_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSCR1[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSCR1_1 = val; break;
! case 2: SSCR1_2 = val; break;
! case 3: SSCR1_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSCR1[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSCR1_1; break;
! case 2: return SSCR1_2; break;
! case 3: return SSCR1_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSSR[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSSR_1 = val; break;
! case 2: SSSR_2 = val; break;
! case 3: SSSR_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSSR[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSSR_1; break;
! case 2: return SSSR_2; break;
! case 3: return SSSR_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSITR[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSITR_1 = val; break;
! case 2: SSITR_2 = val; break;
! case 3: SSITR_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSITR[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSITR_1; break;
! case 2: return SSITR_2; break;
! case 3: return SSITR_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSDR[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSDR_1 = val; break;
! case 2: SSDR_2 = val; break;
! case 3: SSDR_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSDR[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSDR_1; break;
! case 2: return SSDR_2; break;
! case 3: return SSDR_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSTO[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSTO_1 = val; break;
! case 2: SSTO_2 = val; break;
! case 3: SSTO_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSTO[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSTO_1; break;
! case 2: return SSTO_2; break;
! case 3: return SSTO_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSPSP[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSPSP_1 = val; break;
! case 2: SSPSP_2 = val; break;
! case 3: SSPSP_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSPSP[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSPSP_1; break;
! case 2: return SSPSP_2; break;
! case 3: return SSPSP_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSTSA[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSTSA_1 = val; break;
! case 2: SSTSA_2 = val; break;
! case 3: SSTSA_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSTSA[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSTSA_1; break;
! case 2: return SSTSA_2; break;
! case 3: return SSTSA_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSRSA[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSRSA_1 = val; break;
! case 2: SSRSA_2 = val; break;
! case 3: SSRSA_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSRSA[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSRSA_1; break;
! case 2: return SSRSA_2; break;
! case 3: return SSRSA_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSTSS[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSTSS_1 = val; break;
! case 2: SSTSS_2 = val; break;
! case 3: SSTSS_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSTSS[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSTSS_1; break;
! case 2: return SSTSS_2; break;
! case 3: return SSTSS_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSACD[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSACD_1 = val; break;
! case 2: SSACD_2 = val; break;
! case 3: SSACD_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSACD[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSACD_1; break;
! case 2: return SSACD_2; break;
! case 3: return SSACD_3; break;
! default: return 0;
! }
! }
!
! default async event void HplPXA27xSSP.interruptSSP[uint8_t chnl]() {
! call HplPXA27xSSP.setSSSR[chnl](SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT |
! SSSR_PINT | SSSR_ROR );
! return;
! }
!
! async event void SSP1Irq.fired() {
! signal HplPXA27xSSP.interruptSSP[1]();
! }
! async event void SSP2Irq.fired() {
! signal HplPXA27xSSP.interruptSSP[2]();
! }
! async event void SSP3Irq.fired() {
! signal HplPXA27xSSP.interruptSSP[3]();
! }
!
! default async command void SSP1Irq.enable() {return;}
! default async command void SSP2Irq.enable() {return;}
! default async command void SSP3Irq.enable() {return;}
!
! }
!
--- 1,297 ----
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! module HplPXA27xSSPP
! {
! provides {
! interface Init[uint8_t chnl];
! interface HplPXA27xSSP[uint8_t chnl];
! }
! uses {
! interface HplPXA27xInterrupt as SSP1Irq;
! interface HplPXA27xInterrupt as SSP2Irq;
! interface HplPXA27xInterrupt as SSP3Irq;
! }
! }
!
! implementation
! {
!
! command error_t Init.init[uint8_t chnl]() {
! error_t error = SUCCESS;
!
! switch (chnl) {
! case 1:
! CKEN |= CKEN23_SSP1;
! call SSP1Irq.enable();
! break;
! case 2:
! CKEN |= CKEN3_SSP2;
! call SSP2Irq.enable();
! break;
! case 3:
! CKEN |= CKEN4_SSP3;
! //call SSP3Irq.allocate();
! call SSP3Irq.enable();
! break;
! default:
! error = FAIL;
! break;
! }
!
! return error;
! }
!
! async command void HplPXA27xSSP.setSSCR0[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSCR0_1 = val; break;
! case 2: SSCR0_2 = val; break;
! case 3: SSCR0_3 = val; break;
! default: break;
! }
! return;
! }
!
! async command uint32_t HplPXA27xSSP.getSSCR0[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSCR0_1; break;
! case 2: return SSCR0_2; break;
! case 3: return SSCR0_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSCR1[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSCR1_1 = val; break;
! case 2: SSCR1_2 = val; break;
! case 3: SSCR1_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSCR1[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSCR1_1; break;
! case 2: return SSCR1_2; break;
! case 3: return SSCR1_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSSR[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSSR_1 = val; break;
! case 2: SSSR_2 = val; break;
! case 3: SSSR_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSSR[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSSR_1; break;
! case 2: return SSSR_2; break;
! case 3: return SSSR_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSITR[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSITR_1 = val; break;
! case 2: SSITR_2 = val; break;
! case 3: SSITR_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSITR[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSITR_1; break;
! case 2: return SSITR_2; break;
! case 3: return SSITR_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSDR[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSDR_1 = val; break;
! case 2: SSDR_2 = val; break;
! case 3: SSDR_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSDR[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSDR_1; break;
! case 2: return SSDR_2; break;
! case 3: return SSDR_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSTO[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSTO_1 = val; break;
! case 2: SSTO_2 = val; break;
! case 3: SSTO_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSTO[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSTO_1; break;
! case 2: return SSTO_2; break;
! case 3: return SSTO_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSPSP[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSPSP_1 = val; break;
! case 2: SSPSP_2 = val; break;
! case 3: SSPSP_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSPSP[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSPSP_1; break;
! case 2: return SSPSP_2; break;
! case 3: return SSPSP_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSTSA[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSTSA_1 = val; break;
! case 2: SSTSA_2 = val; break;
! case 3: SSTSA_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSTSA[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSTSA_1; break;
! case 2: return SSTSA_2; break;
! case 3: return SSTSA_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSRSA[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSRSA_1 = val; break;
! case 2: SSRSA_2 = val; break;
! case 3: SSRSA_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSRSA[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSRSA_1; break;
! case 2: return SSRSA_2; break;
! case 3: return SSRSA_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSTSS[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSTSS_1 = val; break;
! case 2: SSTSS_2 = val; break;
! case 3: SSTSS_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSTSS[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSTSS_1; break;
! case 2: return SSTSS_2; break;
! case 3: return SSTSS_3; break;
! default: return 0;
! }
! }
!
! async command void HplPXA27xSSP.setSSACD[uint8_t chnl](uint32_t val) {
! switch (chnl) {
! case 1: SSACD_1 = val; break;
! case 2: SSACD_2 = val; break;
! case 3: SSACD_3 = val; break;
! default: break;
! }
! return;
! }
! async command uint32_t HplPXA27xSSP.getSSACD[uint8_t chnl]() {
! switch (chnl) {
! case 1: return SSACD_1; break;
! case 2: return SSACD_2; break;
! case 3: return SSACD_3; break;
! default: return 0;
! }
! }
!
! default async event void HplPXA27xSSP.interruptSSP[uint8_t chnl]() {
! call HplPXA27xSSP.setSSSR[chnl](SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT |
! SSSR_PINT | SSSR_ROR );
! return;
! }
!
! async event void SSP1Irq.fired() {
! signal HplPXA27xSSP.interruptSSP[1]();
! }
! async event void SSP2Irq.fired() {
! signal HplPXA27xSSP.interruptSSP[2]();
! }
! async event void SSP3Irq.fired() {
! signal HplPXA27xSSP.interruptSSP[3]();
! }
!
! default async command void SSP1Irq.enable() {return;}
! default async command void SSP2Irq.enable() {return;}
! default async command void SSP3Irq.enable() {return;}
!
! }
!
Index: HalPXA27xSpiDMAM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HalPXA27xSpiDMAM.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HalPXA27xSpiDMAM.nc 12 Dec 2006 18:23:12 -0000 1.4
--- HalPXA27xSpiDMAM.nc 11 Jun 2008 00:42:13 -0000 1.5
***************
*** 1,210 ****
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.
! * It assumes the Motorola Serial Peripheral Interface format.
! * Uses DMA for the packet based transfers.
! *
! * @param valSCR The value for the SCR field in the SSCR0 register of the
! * associated SSP peripheral.
! *
! * @param valDSS The value for the DSS field in the SSCR0 register of the
! * associated SSP peripheral.
! *
! * @author Phil Buonadonna
! */
!
! generic module HalPXA27xSpiDMAM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT)
! {
! provides {
! interface Init;
! interface SpiByte;
! interface SpiPacket[uint8_t instance];
! }
! uses {
! interface HplPXA27xSSP as SSP;
! interface HplPXA27xDMAChnl as RxDMA;
! interface HplPXA27xDMAChnl as TxDMA;
! interface HplPXA27xDMAInfo as SSPRxDMAInfo;
! interface HplPXA27xDMAInfo as SSPTxDMAInfo;
! }
! }
!
! implementation
! {
! // The BitBuckets need to be 8 bytes.
! norace unsigned long long txBitBucket, rxBitBucket;
! //norace uint8_t ucBitBucket[0x10000];
! //norace uint32_t txBitBucket, rxBitBucket;
! uint8_t *txCurrentBuf, *rxCurrentBuf;
! uint8_t instanceCurrent;
! uint32_t lenCurrent;
!
! command error_t Init.init() {
!
! //txBitBucket = (uint32_t)((uint32_t)&ullBitBucket[1] * ~0x7);
! //rxBitBucket = txBitBucket + 8;
! //rxBitBucket = txBitBucket = (uint32_t)&ucBitBucket[0];
! txCurrentBuf = rxCurrentBuf = NULL;
! lenCurrent = 0 ;
! instanceCurrent = 0;
!
! call SSP.setSSCR1((SSCR1_TRAIL | SSCR1_RFT(8) | SSCR1_TFT(8)));
! call SSP.setSSTO(3500);
! call SSP.setSSCR0(SSCR0_SCR(valSCR) | SSCR0_SSE | SSCR0_FRF(valFRF) | SSCR0_DSS(valDSS) );
!
! call TxDMA.setMap(call SSPTxDMAInfo.getMapIndex());
! call RxDMA.setMap(call SSPRxDMAInfo.getMapIndex());
! call TxDMA.setDALGNbit(TRUE);
! call RxDMA.setDALGNbit(TRUE);
!
! return SUCCESS;
! }
!
! async command uint8_t SpiByte.write(uint8_t tx) {
! volatile uint32_t tmp;
! volatile uint8_t val;
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! tmp = call SSP.getSSDR();
! }
! #endif
! call SSP.setSSDR(tx);
!
! while ((call SSP.getSSSR()) & SSSR_BSY);
!
! val = call SSP.getSSDR();
!
! return val;
! }
!
! async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {
! uint32_t tmp;
! uint32_t txAddr,rxAddr;
! uint32_t txDMAFlags, rxDMAFlags;
! error_t error = FAIL;
!
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! tmp = call SSP.getSSDR();
! }
! #endif
!
! atomic {
! txCurrentBuf = txBuf;
! rxCurrentBuf = rxBuf;
! lenCurrent = len;
! instanceCurrent = instance;
! }
!
! txDMAFlags = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1
! | DCMD_LEN(len));
! rxDMAFlags = (DCMD_FLOWSRC | DCMD_ENDIRQEN | DCMD_BURST8 | DCMD_WIDTH1
! | DCMD_LEN(len));
!
! if (rxBuf == NULL) {
! rxAddr = (uint32_t)&rxBitBucket;
! }
! else {
! rxAddr = (uint32_t)rxBuf;
! rxDMAFlags |= DCMD_INCTRGADDR;
! }
!
! if (txBuf == NULL) {
! txAddr = (uint32_t)&txBitBucket;
! }
! else {
! txAddr = (uint32_t)txBuf;
! txDMAFlags |= DCMD_INCSRCADDR;
! }
!
! call RxDMA.setDCSR(DCSR_NODESCFETCH | DCSR_EORIRQEN | DCSR_EORINT);
! call RxDMA.setDSADR(call SSPRxDMAInfo.getAddr());
! call RxDMA.setDTADR(rxAddr);
! call RxDMA.setDCMD(rxDMAFlags);
!
! call TxDMA.setDCSR(DCSR_NODESCFETCH);
! call TxDMA.setDSADR(txAddr);
! call TxDMA.setDTADR(call SSPTxDMAInfo.getAddr());
! call TxDMA.setDCMD(txDMAFlags);
!
! call SSP.setSSSR(SSSR_TINT);
! call SSP.setSSCR1((call SSP.getSSCR1()) | SSCR1_RSRE | SSCR1_TSRE);
!
! call RxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH | DCSR_EORIRQEN);
! call TxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);
!
! error = SUCCESS;
!
! return error;
! }
!
! async event void RxDMA.interruptDMA() {
! uint8_t *txBuf,*rxBuf;
! uint8_t instance;
! uint32_t len;
!
! atomic {
! instance = instanceCurrent;
! len = lenCurrent;
! txBuf = txCurrentBuf;
! rxBuf = rxCurrentBuf;
! lenCurrent = 0;
! }
! call RxDMA.setDCMD(0);
! call RxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
!
! signal SpiPacket.sendDone[instance](txBuf,rxBuf,len,SUCCESS);
!
! return;
! }
!
! async event void TxDMA.interruptDMA() {
! // The transmit side should NOT generate an interrupt.
! call TxDMA.setDCMD(0);
! call TxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
! return;
! }
!
! async event void SSP.interruptSSP() {
! // For this Hal, we should never get here normally
! // Perhaps we should signal any weird errors? For now, just clear the interrupts
! call SSP.setSSSR(SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT |
! SSSR_PINT | SSSR_ROR );
! return;
! }
!
! default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf,
! uint16_t len, error_t error) {
! return;
! }
!
! }
--- 1,210 ----
! /* $Id$ */
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! * Implements the TOS 2.0 SpiByte and SpiPacket interfaces for the PXA27x.
! * It assumes the Motorola Serial Peripheral Interface format.
! * Uses DMA for the packet based transfers.
! *
! * @param valSCR The value for the SCR field in the SSCR0 register of the
! * associated SSP peripheral.
! *
! * @param valDSS The value for the DSS field in the SSCR0 register of the
! * associated SSP peripheral.
! *
! * @author Phil Buonadonna
! */
!
! generic module HalPXA27xSpiDMAM(uint8_t valFRF, uint8_t valSCR, uint8_t valDSS, bool enableRWOT)
! {
! provides {
! interface Init;
! interface SpiByte;
! interface SpiPacket[uint8_t instance];
! }
! uses {
! interface HplPXA27xSSP as SSP;
! interface HplPXA27xDMAChnl as RxDMA;
! interface HplPXA27xDMAChnl as TxDMA;
! interface HplPXA27xDMAInfo as SSPRxDMAInfo;
! interface HplPXA27xDMAInfo as SSPTxDMAInfo;
! }
! }
!
! implementation
! {
! // The BitBuckets need to be 8 bytes.
! norace unsigned long long txBitBucket, rxBitBucket;
! //norace uint8_t ucBitBucket[0x10000];
! //norace uint32_t txBitBucket, rxBitBucket;
! uint8_t *txCurrentBuf, *rxCurrentBuf;
! uint8_t instanceCurrent;
! uint32_t lenCurrent;
!
! command error_t Init.init() {
!
! //txBitBucket = (uint32_t)((uint32_t)&ullBitBucket[1] * ~0x7);
! //rxBitBucket = txBitBucket + 8;
! //rxBitBucket = txBitBucket = (uint32_t)&ucBitBucket[0];
! txCurrentBuf = rxCurrentBuf = NULL;
! lenCurrent = 0 ;
! instanceCurrent = 0;
!
! call SSP.setSSCR1((SSCR1_TRAIL | SSCR1_RFT(8) | SSCR1_TFT(8)));
! call SSP.setSSTO(3500);
! call SSP.setSSCR0(SSCR0_SCR(valSCR) | SSCR0_SSE | SSCR0_FRF(valFRF) | SSCR0_DSS(valDSS) );
!
! call TxDMA.setMap(call SSPTxDMAInfo.getMapIndex());
! call RxDMA.setMap(call SSPRxDMAInfo.getMapIndex());
! call TxDMA.setDALGNbit(TRUE);
! call RxDMA.setDALGNbit(TRUE);
!
! return SUCCESS;
! }
!
! async command uint8_t SpiByte.write(uint8_t tx) {
! volatile uint32_t tmp;
! volatile uint8_t val;
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! tmp = call SSP.getSSDR();
! }
! #endif
! call SSP.setSSDR(tx);
!
! while ((call SSP.getSSSR()) & SSSR_BSY);
!
! val = call SSP.getSSDR();
!
! return val;
! }
!
! async command error_t SpiPacket.send[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf, uint16_t len) {
! uint32_t tmp;
! uint32_t txAddr,rxAddr;
! uint32_t txDMAFlags, rxDMAFlags;
! error_t error = FAIL;
!
! #if 1
! while ((call SSP.getSSSR()) & SSSR_RNE) {
! tmp = call SSP.getSSDR();
! }
! #endif
!
! atomic {
! txCurrentBuf = txBuf;
! rxCurrentBuf = rxBuf;
! lenCurrent = len;
! instanceCurrent = instance;
! }
!
! txDMAFlags = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1
! | DCMD_LEN(len));
! rxDMAFlags = (DCMD_FLOWSRC | DCMD_ENDIRQEN | DCMD_BURST8 | DCMD_WIDTH1
! | DCMD_LEN(len));
!
! if (rxBuf == NULL) {
! rxAddr = (uint32_t)&rxBitBucket;
! }
! else {
! rxAddr = (uint32_t)rxBuf;
! rxDMAFlags |= DCMD_INCTRGADDR;
! }
!
! if (txBuf == NULL) {
! txAddr = (uint32_t)&txBitBucket;
! }
! else {
! txAddr = (uint32_t)txBuf;
! txDMAFlags |= DCMD_INCSRCADDR;
! }
!
! call RxDMA.setDCSR(DCSR_NODESCFETCH | DCSR_EORIRQEN | DCSR_EORINT);
! call RxDMA.setDSADR(call SSPRxDMAInfo.getAddr());
! call RxDMA.setDTADR(rxAddr);
! call RxDMA.setDCMD(rxDMAFlags);
!
! call TxDMA.setDCSR(DCSR_NODESCFETCH);
! call TxDMA.setDSADR(txAddr);
! call TxDMA.setDTADR(call SSPTxDMAInfo.getAddr());
! call TxDMA.setDCMD(txDMAFlags);
!
! call SSP.setSSSR(SSSR_TINT);
! call SSP.setSSCR1((call SSP.getSSCR1()) | SSCR1_RSRE | SSCR1_TSRE);
!
! call RxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH | DCSR_EORIRQEN);
! call TxDMA.setDCSR(DCSR_RUN | DCSR_NODESCFETCH);
!
! error = SUCCESS;
!
! return error;
! }
!
! async event void RxDMA.interruptDMA() {
! uint8_t *txBuf,*rxBuf;
! uint8_t instance;
! uint32_t len;
!
! atomic {
! instance = instanceCurrent;
! len = lenCurrent;
! txBuf = txCurrentBuf;
! rxBuf = rxCurrentBuf;
! lenCurrent = 0;
! }
! call RxDMA.setDCMD(0);
! call RxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
!
! signal SpiPacket.sendDone[instance](txBuf,rxBuf,len,SUCCESS);
!
! return;
! }
!
! async event void TxDMA.interruptDMA() {
! // The transmit side should NOT generate an interrupt.
! call TxDMA.setDCMD(0);
! call TxDMA.setDCSR(DCSR_EORINT | DCSR_ENDINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
! return;
! }
!
! async event void SSP.interruptSSP() {
! // For this Hal, we should never get here normally
! // Perhaps we should signal any weird errors? For now, just clear the interrupts
! call SSP.setSSSR(SSSR_BCE | SSSR_TUR | SSSR_EOC | SSSR_TINT |
! SSSR_PINT | SSSR_ROR );
! return;
! }
!
! default async event void SpiPacket.sendDone[uint8_t instance](uint8_t* txBuf, uint8_t* rxBuf,
! uint16_t len, error_t error) {
! return;
! }
!
! }
Index: HplPXA27xSSP2C.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-2.x/tos/chips/pxa27x/ssp/HplPXA27xSSP2C.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** HplPXA27xSSP2C.nc 7 Nov 2006 19:31:14 -0000 1.3
--- HplPXA27xSSP2C.nc 11 Jun 2008 00:42:13 -0000 1.4
***************
*** 1,59 ****
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! configuration HplPXA27xSSP2C
! {
! provides {
! interface HplPXA27xSSP;
! interface HplPXA27xDMAInfo as SSPRxDMAReg;
! interface HplPXA27xDMAInfo as SSPTxDMAReg;
! }
! }
!
! implementation
! {
! components HplPXA27xSSPP;
! components HplPXA27xInterruptM;
! components PlatformP;
!
! HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[2];
! components new HplPXA27xDMAInfoC(15, (uint32_t)&SSDR_2) as SSPRxDMA;
! components new HplPXA27xDMAInfoC(16, (uint32_t)&SSDR_2) as SSPTxDMA;
! SSPRxDMAReg = SSPRxDMA;
! SSPTxDMAReg = SSPTxDMA;
!
! HplPXA27xSSPP.Init[2] <- PlatformP.InitL1;
!
! HplPXA27xSSPP.SSP2Irq -> HplPXA27xInterrupM.PXA27xIrq[PPID_SSP2];
! }
--- 1,59 ----
! /*
! * Copyright (c) 2005 Arched Rock Corporation
! * All rights reserved.
! * Redistribution and use in source and binary forms, with or without
! * modification, are permitted provided that the following conditions are
! * met:
! * Redistributions of source code must retain the above copyright
! * notice, this list of conditions and the following disclaimer.
! * Redistributions in binary form must reproduce the above copyright
! * notice, this list of conditions and the following disclaimer in the
! * documentation and/or other materials provided with the distribution.
! *
! * Neither the name of the Arched Rock Corporation nor the names of its
! * contributors may be used to endorse or promote products derived from
! * this software without specific prior written permission.
! *
! * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
! * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
! * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
! * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE ARCHED
! * ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
! * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
! * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
! * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
! * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
! * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
! * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
! * DAMAGE.
! */
! /**
! *
! * @author Phil Buonadonna
! */
!
! configuration HplPXA27xSSP2C
! {
! provides {
! interface HplPXA27xSSP;
! interface HplPXA27xDMAInfo as SSPRxDMAReg;
! interface HplPXA27xDMAInfo as SSPTxDMAReg;
! }
! }
!
! implementation
! {
! components HplPXA27xSSPP;
! components HplPXA27xInterruptM;
! components PlatformP;
!
! HplPXA27xSSP = HplPXA27xSSPP.HplPXA27xSSP[2];
! components new HplPXA27xDMAInfoC(15, (uint32_t)&SSDR_2) as SSPRxDMA;
! components new HplPXA27xDMAInfoC(16, (uint32_t)&SSDR_2) as SSPTxDMA;
! SSPRxDMAReg = SSPRxDMA;
! SSPTxDMAReg = SSPTxDMA;
!
! HplPXA27xSSPP.Init[2] <- PlatformP.InitL1;
!
! HplPXA27xSSPP.SSP2Irq -> HplPXA27xInterrupM.PXA27xIrq[PPID_SSP2];
! }
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