[Tinyos-2-commits] [tinyos-main] r5720 committed - add ucmini platform (and chips atm128rfa1, bh1750fvi, bma180, ms5607)

tinyos-main at googlecode.com tinyos-main at googlecode.com
Sun Sep 4 02:06:50 PDT 2011


Revision: 5720
Author:   mmaroti
Date:     Sun Sep  4 02:04:37 2011
Log:      add ucmini platform (and chips atm128rfa1, bh1750fvi, bma180,  
ms5607)
http://code.google.com/p/tinyos-main/source/detail?r=5720

Added:
  /trunk/support/make/Makeplatformopts
  /trunk/support/make/avr/avr109.extra
  /trunk/support/make/avr/avr109m.extra
  /trunk/support/make/avr/dragonjtag.extra
  /trunk/support/make/avr/zbp.extra
  /trunk/support/make/rst.extra
  /trunk/support/make/ucmini.target
  /trunk/tos/chips/atm128rfa1
  /trunk/tos/chips/atm128rfa1/HplAtm128UartC.nc
  /trunk/tos/chips/atm128rfa1/HplAtm128UartP.nc
  /trunk/tos/chips/atm128rfa1/McuInitC.nc
  /trunk/tos/chips/atm128rfa1/McuInitP.nc
  /trunk/tos/chips/atm128rfa1/McuSleepC.nc
  /trunk/tos/chips/atm128rfa1/adc
  /trunk/tos/chips/atm128rfa1/adc/Atm128Adc.h
  /trunk/tos/chips/atm128rfa1/adc/HplAtm128AdcC.nc
  /trunk/tos/chips/atm128rfa1/adc/HplAtm128AdcP.nc
  /trunk/tos/chips/atm128rfa1/atm128hardware.h
  /trunk/tos/chips/atm128rfa1/i2c
  /trunk/tos/chips/atm128rfa1/i2c/HplAtm128I2CBusC.nc
  /trunk/tos/chips/atm128rfa1/i2c/HplAtm128I2CBusP.nc
  /trunk/tos/chips/atm128rfa1/pins
  /trunk/tos/chips/atm128rfa1/pins/AtmegaExtInterrupt0C.nc
  /trunk/tos/chips/atm128rfa1/pins/AtmegaExtInterruptP.nc
  /trunk/tos/chips/atm128rfa1/pins/AtmegaPinChange0C.nc
  /trunk/tos/chips/atm128rfa1/pins/AtmegaPinChange1C.nc
  /trunk/tos/chips/atm128rfa1/pins/AtmegaPinChangeP.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtm128GeneralIOC.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtm128InterruptC.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtm128InterruptPinP.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtm128InterruptSigP.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt.h
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt0C.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt1C.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt2C.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt3C.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaPinChange.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaPinChange0C.nc
  /trunk/tos/chips/atm128rfa1/pins/HplAtmegaPinChange1C.nc
  /trunk/tos/chips/atm128rfa1/radio
  /trunk/tos/chips/atm128rfa1/radio/RFA1ActiveMessageC.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1DriverConfig.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1DriverLayer.h
  /trunk/tos/chips/atm128rfa1/radio/RFA1DriverLayerC.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1DriverLayerP.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1Radio.h
  /trunk/tos/chips/atm128rfa1/radio/RFA1RadioC.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1RadioOffP.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1RadioP.nc
  /trunk/tos/chips/atm128rfa1/radio/RFA1TimeSyncMessageC.nc
  /trunk/tos/chips/atm128rfa1/radio/RadioConfig.h
  /trunk/tos/chips/atm128rfa1/sensors
  /trunk/tos/chips/atm128rfa1/sensors/ArbitratedInternalTempDeviceP.nc
  /trunk/tos/chips/atm128rfa1/sensors/Atm128InternalTempDeviceC.nc
  /trunk/tos/chips/atm128rfa1/sensors/Atm128InternalTemperatureC.nc
  /trunk/tos/chips/atm128rfa1/sensors/ITempC.nc
  /trunk/tos/chips/atm128rfa1/sensors/ITempP.nc
  /trunk/tos/chips/atm128rfa1/sensors/InternalTempControlP.nc
  /trunk/tos/chips/atm128rfa1/sensors/InternalTempP.nc
  /trunk/tos/chips/atm128rfa1/sensors/InternalTempStreamC.nc
  /trunk/tos/chips/atm128rfa1/sensors/TempDeviceP.nc
  /trunk/tos/chips/atm128rfa1/sensors/TempP.nc
  /trunk/tos/chips/atm128rfa1/spi
  /trunk/tos/chips/atm128rfa1/spi/HplAtm128SpiC.nc
  /trunk/tos/chips/atm128rfa1/spi/HplAtm128SpiP.nc
  /trunk/tos/chips/atm128rfa1/timer
  /trunk/tos/chips/atm128rfa1/timer/Alarm62khz32C.nc
  /trunk/tos/chips/atm128rfa1/timer/AlarmMcu16C.nc
  /trunk/tos/chips/atm128rfa1/timer/AlarmMcu32C.nc
  /trunk/tos/chips/atm128rfa1/timer/AlarmMicro32C.nc
  /trunk/tos/chips/atm128rfa1/timer/AlarmMilli32C.nc
  /trunk/tos/chips/atm128rfa1/timer/AlarmRtc16C.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaCapture.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaCompare.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaCompareP.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaCounter.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaCounterP.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaRtcCompareP.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaRtcCounterP.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaTransformCounterC.nc
  /trunk/tos/chips/atm128rfa1/timer/AtmegaTransformCounterP.nc
  /trunk/tos/chips/atm128rfa1/timer/BusyWaitMicroC.nc
  /trunk/tos/chips/atm128rfa1/timer/Counter62khz32C.nc
  /trunk/tos/chips/atm128rfa1/timer/CounterMcu16C.nc
  /trunk/tos/chips/atm128rfa1/timer/CounterMcu32C.nc
  /trunk/tos/chips/atm128rfa1/timer/CounterMicro32C.nc
  /trunk/tos/chips/atm128rfa1/timer/CounterMilli32C.nc
  /trunk/tos/chips/atm128rfa1/timer/CounterRtc16C.nc
  /trunk/tos/chips/atm128rfa1/timer/CounterRtc32C.nc
  /trunk/tos/chips/atm128rfa1/timer/HighBits.nc
  /trunk/tos/chips/atm128rfa1/timer/HighBitsC.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer.h
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer1C.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer1P.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer2AsyncC.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer2AsyncP.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer3C.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1Timer3P.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1TimerMacC.nc
  /trunk/tos/chips/atm128rfa1/timer/HplAtmRfa1TimerMacP.nc
  /trunk/tos/chips/atm128rfa1/timer/LocalTime62khzC.nc
  /trunk/tos/chips/atm128rfa1/timer/LocalTimeMcuC.nc
  /trunk/tos/chips/atm128rfa1/timer/LocalTimeMicroC.nc
  /trunk/tos/chips/atm128rfa1/timer/LocalTimeMilliC.nc
  /trunk/tos/chips/atm128rfa1/timer/MeasureClockC.nc
  /trunk/tos/chips/atm128rfa1/timer/README
  /trunk/tos/chips/atm128rfa1/timer/TimerConfig.h
  /trunk/tos/chips/atm128rfa1/timer/TimerMilliP.nc
  /trunk/tos/chips/bh1750fvi
  /trunk/tos/chips/bh1750fvi/Bh1750fvi.h
  /trunk/tos/chips/bh1750fvi/Bh1750fviC.nc
  /trunk/tos/chips/bh1750fvi/Bh1750fviP.nc
  /trunk/tos/chips/bma180
  /trunk/tos/chips/bma180/Bma180.h
  /trunk/tos/chips/bma180/Bma180C.nc
  /trunk/tos/chips/bma180/BmaReadC.nc
  /trunk/tos/chips/bma180/BmaReadP.nc
  /trunk/tos/chips/bma180/BmaStreamC.nc
  /trunk/tos/chips/bma180/BmaStreamP.nc
  /trunk/tos/chips/bma180/HplImpC.nc
  /trunk/tos/chips/bma180/HplImpP.nc
  /trunk/tos/chips/bma180/SpiImpC.nc
  /trunk/tos/chips/bma180/SpiImpM.nc
  /trunk/tos/chips/ms5607
  /trunk/tos/chips/ms5607/Calibration.nc
  /trunk/tos/chips/ms5607/Ms5607.h
  /trunk/tos/chips/ms5607/Ms5607C.nc
  /trunk/tos/chips/ms5607/Ms5607P.nc
  /trunk/tos/chips/ms5607/RomReaderP.nc
  /trunk/tos/chips/sht21
  /trunk/tos/chips/sht21/Sht21.h
  /trunk/tos/chips/sht21/Sht21C.nc
  /trunk/tos/chips/sht21/Sht21DriverC.nc
  /trunk/tos/chips/sht21/Sht21DriverP.nc
  /trunk/tos/platforms/ucmini
  /trunk/tos/platforms/ucmini/.platform
  /trunk/tos/platforms/ucmini/ActiveMessageC.nc
  /trunk/tos/platforms/ucmini/DemoSensorC.nc
  /trunk/tos/platforms/ucmini/DemoSensorStreamC.nc
  /trunk/tos/platforms/ucmini/HplSerialAutoControlC.nc
  /trunk/tos/platforms/ucmini/I2CBusC.nc
  /trunk/tos/platforms/ucmini/I2CBusP.nc
  /trunk/tos/platforms/ucmini/Leds.nc
  /trunk/tos/platforms/ucmini/LedsC.nc
  /trunk/tos/platforms/ucmini/LedsP.nc
  /trunk/tos/platforms/ucmini/NoLedsC.nc
  /trunk/tos/platforms/ucmini/PlatformC.nc
  /trunk/tos/platforms/ucmini/PlatformLedsC.nc
  /trunk/tos/platforms/ucmini/PlatformP.nc
  /trunk/tos/platforms/ucmini/PlatformSerialC.nc
  /trunk/tos/platforms/ucmini/RCCalibrate.nc
  /trunk/tos/platforms/ucmini/RCCalibrateP.nc
  /trunk/tos/platforms/ucmini/README
  /trunk/tos/platforms/ucmini/SerialAutoControlC.nc
  /trunk/tos/platforms/ucmini/SerialAutoControlP.nc
  /trunk/tos/platforms/ucmini/SerialResetC.nc
  /trunk/tos/platforms/ucmini/SerialResetP.nc
  /trunk/tos/platforms/ucmini/TimeSyncMessageC.nc
  /trunk/tos/platforms/ucmini/UserButton.h
  /trunk/tos/platforms/ucmini/UserButtonC.nc
  /trunk/tos/platforms/ucmini/UserButtonP.nc
  /trunk/tos/platforms/ucmini/chips
  /trunk/tos/platforms/ucmini/chips/bh1750fvi
  /trunk/tos/platforms/ucmini/chips/bh1750fvi/Hplbh1750C.nc
  /trunk/tos/platforms/ucmini/chips/bma180
  /trunk/tos/platforms/ucmini/chips/bma180/HplBma180C.nc
  /trunk/tos/platforms/ucmini/chips/ms5607
  /trunk/tos/platforms/ucmini/chips/ms5607/HplMs5607C.nc
  /trunk/tos/platforms/ucmini/chips/sht21
  /trunk/tos/platforms/ucmini/chips/sht21/HplSht21C.nc
  /trunk/tos/platforms/ucmini/chips/stm25p
  /trunk/tos/platforms/ucmini/chips/stm25p/HplStm25pPinsC.nc
  /trunk/tos/platforms/ucmini/chips/stm25p/HplStm25pSpiC.nc
  /trunk/tos/platforms/ucmini/chips/stm25p/Stm25pOffC.nc
  /trunk/tos/platforms/ucmini/chips/stm25p/Stm25pOffP.nc
  /trunk/tos/platforms/ucmini/chips/stm25p/Stm25pPowerC.nc
  /trunk/tos/platforms/ucmini/chips/stm25p/Stm25pPowerP.nc
  /trunk/tos/platforms/ucmini/chips/stm25p/Stm25pSectorC.nc
  /trunk/tos/platforms/ucmini/hardware.h
  /trunk/tos/platforms/ucmini/platform.h
  /trunk/tos/platforms/ucmini/platform_message.h

=======================================
--- /dev/null
+++ /trunk/support/make/Makeplatformopts	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,42 @@
+# microcontroller identification
+ATM128_PLATFORMS = iris mica mica2 mica2dot micaz btnode3
+MSP430_PLATFORMS = epic eyesIFX eyesIFXv1 eyesIFXv2 shimmer shimmer2  
shimmer2r span telosa telosb tinynode
+PXA27X_PLATFORMS = intelmote2
+M16C62P_PLATFORMS= mulle
+
+ifneq ($(findstring $(PLATFORM),$(ATM128_PLATFORMS)),)
+	MCU ?= ATM128
+else ifneq ($(findstring $(PLATFORM),$(MSP430_PLATFORMS)),)
+	MCU ?= MSP430
+else ifneq ($(findstring $(PLATFORM),$(PXA27X_PLATFORMS)),)
+	MCU ?= PXA27X
+else ifneq ($(findstring $(PLATFORM),$(M16C62P_PLATFORMS)),)
+	MCU ?= M16C62P
+else
+	MCU ?= UNKNOWN
+endif
+CONTROLLER_$(MCU) = $(MCU)
+CFLAGS += -DCONTROLLER_$(MCU)
+
+# radio chip identification
+RF230_PLATFORMS  = iris mulle
+CC1000_PLATFORMS = mica mica2 mica2dot btnode3
+CC2420_PLATFORMS = micaz telosa telosb shimmer shimmer2 shimmer2r epic  
span intelmote2
+TDA5250_PLATFORMS= eyesIFX eyesIFXv1 eyesIFXv2
+XE1205_PLATFORMS = tinynode
+
+ifneq ($(findstring $(PLATFORM),$(RF230_PLATFORMS)),)
+	RCHIP ?= RF230
+else ifneq ($(findstring $(PLATFORM),$(CC1000_PLATFORMS)),)
+	RCHIP ?= CC1000
+else ifneq ($(findstring $(PLATFORM),$(CC2420_PLATFORMS)),)
+	RCHIP ?= CC2420
+else ifneq ($(findstring $(PLATFORM),$(TDA5250_PLATFORMS)),)
+	RCHIP ?= TDA5250
+else ifneq ($(findstring $(PLATFORM),$(XE1205_PLATFORMS)),)
+	RCHIP ?= XE1205
+else
+	RCHIP ?= UNKNOWN
+endif
+RADIO_$(RCHIP) = $(RCHIP)
+CFLAGS += -DRADIO_$(RCHIP)
=======================================
--- /dev/null
+++ /trunk/support/make/avr/avr109.extra	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,31 @@
+#-*-Makefile-*- vim:syntax=make
+
+ifeq ($(AVR109),)
+$(error AVR109 must be defined, try "make $(TARGETS) help")
+endif
+
+PROGRAM = avr109
+AVR109_BAUDRATE ?= 57600
+
+ifeq ($(PROGRAMMER),avrdude)
+    ifeq ($(shell [ -f /bin/cygwin1.dll ] && echo cygwin),cygwin)
+      AVR109 := '\\.\$(AVR109)'
+    endif
+    ifdef BOOTLOADER_IMG
+      ifeq ($(shell [ -f /bin/cygwin1.dll ] && echo cygwin),cygwin)
+        BOOTLOADER_IMG := $(shell cygpath -m $(BOOTLOADER_IMG))
+      endif
+    endif
+    PROGRAMMER_FLAGS = -cavr109 -P$(AVR109) -b$(AVR109_BAUDRATE)  
$(PROGRAMMER_PART) $(PROGRAMMER_EXTRA_FLAGS)
+    PROGRAMMER_INSTALL_SREC_FLAGS = -U flash:w:$(INSTALL_SREC):a
+    PROGRAMMER_INSTALL_BOOTLOADER_FLAGS = -V -D -U  
flash:w:$(BOOTLOADER_IMG):a
+endif
+
+program: FORCE
+	$(RESET_LINE)
+	$(PROGRAMMER) $(PROGRAMMER_FLAGS) $(PROGRAMMER_INSTALL_SREC_FLAGS)
+
+program_bl: FORCE
+	java org.szte.wsn.zigbit.Programmer -port $(AVR109) -baudrate  
$(BOOTLOADER_BAUDRATE) -reset -askforreset -sleep $(AVR109_SLEEP)
+	$(PROGRAMMER) $(PROGRAMMER_FLAGS) $(PROGRAMMER_INSTALL_BOOTLOADER_FLAGS)
+
=======================================
--- /dev/null
+++ /trunk/support/make/avr/avr109m.extra	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,28 @@
+#-*-Makefile-*- vim:syntax=make
+
+ifeq ($(AVR109M),)
+$(error AVR109M must be defined, try "make $(TARGETS) help")
+endif
+
+PROGRAM = avr109
+AVR109_BAUDRATE ?= 115200
+
+ifeq ($(PROGRAMMER),avrdude)
+    ifeq ($(shell [ -f /bin/cygwin1.dll ] && echo cygwin),cygwin)
+      AVR109 := '\\.\$(AVR109)'
+    endif
+    ifdef BOOTLOADER_IMG
+      ifeq ($(shell [ -f /bin/cygwin1.dll ] && echo cygwin),cygwin)
+        BOOTLOADER_IMG := $(shell cygpath -m $(BOOTLOADER_IMG))
+      endif
+    endif
+    PROGRAMMER_FLAGS = -cavr109 -P$(AVR109M) -b$(AVR109_BAUDRATE)  
$(PROGRAMMER_PART) $(PROGRAMMER_EXTRA_FLAGS)
+    PROGRAMMER_INSTALL_SREC_FLAGS = -U flash:w:$(INSTALL_SREC):a
+    PROGRAMMER_INSTALL_BOOTLOADER_FLAGS = -V -D -U  
flash:w:$(BOOTLOADER_IMG):a
+endif
+
+program: FORCE
+	@echo "Please reset the mote, then press enter" ;
+	@read
+	$(PROGRAMMER) $(PROGRAMMER_FLAGS) $(PROGRAMMER_INSTALL_SREC_FLAGS)
+
=======================================
--- /dev/null
+++ /trunk/support/make/avr/dragonjtag.extra	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,24 @@
+#-*-Makefile-*- vim:syntax=make
+
+DRAGONJTAG?=usb
+
+PROGRAM = dragonjtag
+
+ifeq ($(PROGRAMMER),avrdude)
+    ifeq ($(shell [ -f /bin/cygwin1.dll ] && echo cygwin),cygwin)
+      DRAGONJTAG := '\\.\$(DRAGONJTAG)'
+    endif
+    ifdef BOOTLOADER_IMG
+      ifeq ($(shell [ -f /bin/cygwin1.dll ] && echo cygwin),cygwin)
+        BOOTLOADER_IMG := $(shell cygpath -m $(BOOTLOADER_IMG))
+      endif
+    endif
+    PROGRAMMER_FLAGS = -cdragon_jtag -P$(DRAGONJTAG) $(PROGRAMMER_PART)  
$(PROGRAMMER_EXTRA_FLAGS)
+    PROGRAMMER_INSTALL_SREC_FLAGS = -U flash:w:$(INSTALL_SREC):a
+    PROGRAMMER_INSTALL_BOOTLOADER_FLAGS = -V -D -U  
flash:w:$(BOOTLOADER_IMG):a
+endif
+
+program: FORCE
+	@echo "    installing $(PLATFORM) binary using dragonjtag"
+	$(PROGRAMMER) $(PROGRAMMER_FLAGS) $(PROGRAMMER_INSTALL_SREC_FLAGS)
+
=======================================
--- /dev/null
+++ /trunk/support/make/avr/zbp.extra	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,16 @@
+#-*-Makefile-*- vim:syntax=make
+#$Id: zbp.extra,v 1.2 2010-07-19 08:00:44 mmaroti Exp $
+
+PROGRAM = zbp
+
+ifneq ($(ZBP),)
+ZBP_PORT = $(ZBP)
+endif
+
+ifneq ($(ZBP_BAUDRATE),)
+ZBP_BAUDRATE = " -baudrate $(ZBP_BAUDRATE)"
+endif
+
+program: FORCE
+	@echo "    installing $(PLATFORM) binary using zigbit bootloader"
+	java net.tinyos.util.ZigbitProgrammer -port $(ZBP_PORT)$(ZBP_BAUDRATE)  
-reset -upload $(INSTALL_SREC)
=======================================
--- /dev/null
+++ /trunk/support/make/rst.extra	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,4 @@
+BUILD_DEPS = res
+AVR109=$(RST)
+res:
+	$(RESET_LINE)
=======================================
--- /dev/null
+++ /trunk/support/make/ucmini.target	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,17 @@
+#$Id:
+
+PLATFORM = ucmini
+PROGRAMMER ?= avrdude
+
+PROGRAMMER_PART ?= -pm128rfa1
+
+VOLUMEFILE = volumes-stm25p.xml
+VOLUME_ALLOCATOR ?= tos-storage-stm25p -s32
+
+AVR109_SLEEP ?= 0
+RESET_LINE = java net.tinyos.util.ZigbitProgrammer -port $(AVR109) -reset  
-askforreset -sleep $(AVR109_SLEEP)
+
+$(call TOSMake_include_platform,avr)
+
+ucmini: $(BUILD_DEPS)
+	@:
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/HplAtm128UartC.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,77 @@
+/// $Id: HplAtm128UartC.nc,v 1.6 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+///
+
+#include <Atm128Uart.h>
+
+/**
+ * HPL for the Atmega 128 serial ports.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ * @author David Gay
+ */
+configuration HplAtm128UartC
+{
+  provides {
+    interface StdControl as Uart0TxControl;
+    interface StdControl as Uart0RxControl;
+    interface HplAtm128Uart as HplUart0;
+
+    interface StdControl as Uart1TxControl;
+    interface StdControl as Uart1RxControl;
+    interface HplAtm128Uart as HplUart1;
+  }
+}
+implementation
+{
+  components HplAtm128UartP, PlatformC, McuSleepC;
+
+  Uart0TxControl = HplAtm128UartP.Uart0TxControl;
+  Uart0RxControl = HplAtm128UartP.Uart0RxControl;
+  HplUart0 = HplAtm128UartP.HplUart0;
+
+  Uart1TxControl = HplAtm128UartP.Uart1TxControl;
+  Uart1RxControl = HplAtm128UartP.Uart1RxControl;
+  HplUart1 = HplAtm128UartP.HplUart1;
+
+  HplAtm128UartP.Atm128Calibrate -> PlatformC;
+  HplAtm128UartP.McuPowerState -> McuSleepC;
+
+  components MainC;
+  MainC.SoftwareInit -> HplAtm128UartP.Uart0Init;
+  MainC.SoftwareInit -> HplAtm128UartP.Uart1Init;
+
+	HplAtm128UartP.McuPowerState -> McuSleepC;
+	HplAtm128UartP.McuPowerOverride <- McuSleepC;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/HplAtm128UartP.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2006 Arch Rock Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the Arch Rock Corporation nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
+ * ARCH ROCK OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE
+ */
+
+/**
+ * @author Alec Woo <awoo at archrock.com>
+ * @author Jonathan Hui <jhui at archrock.com>
+ * @version $Revision: 1.1 $ $Date: 2010-10-25 03:23:39 $
+ */
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * Private component of the Atmega1281 serial port HPL.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ * @author David Gay
+ * @author Janos Sallai <janos.sallai at vanderbilt.edu>
+ */
+
+#include <Atm128Uart.h>
+
+module HplAtm128UartP {
+
+  provides interface Init as Uart0Init;
+  provides interface StdControl as Uart0TxControl;
+  provides interface StdControl as Uart0RxControl;
+  provides interface HplAtm128Uart as HplUart0;
+
+  provides interface Init as Uart1Init;
+  provides interface StdControl as Uart1TxControl;
+  provides interface StdControl as Uart1RxControl;
+  provides interface HplAtm128Uart as HplUart1;
+
+	provides interface McuPowerOverride;
+
+  uses interface Atm128Calibrate;
+  uses interface McuPowerState;
+}
+implementation {
+
+  //=== Uart Init Commands. ====================================
+  command error_t Uart0Init.init() {
+    Atm128UartMode_t    mode;
+    Atm128UartStatus_t  stts;
+    Atm128UartControl_t ctrl;
+    uint16_t ubrr0;
+
+    ctrl.bits = (struct Atm128_UCSRB_t) {rxcie:0, txcie:0, rxen:0, txen:0};
+    stts.bits = (struct Atm128_UCSRA_t) {u2x:1};
+    mode.bits = (struct Atm128_UCSRC_t)  
{ucsz:ATM128_UART_DATA_SIZE_8_BITS};
+
+    ubrr0 = call Atm128Calibrate.baudrateRegister(PLATFORM_BAUDRATE);
+    UBRR0L = ubrr0;
+    UBRR0H = ubrr0 >> 8;
+    UCSR0A = stts.flat;
+    UCSR0C = mode.flat;
+    UCSR0B = ctrl.flat;
+
+    return SUCCESS;
+  }
+
+  command error_t Uart0TxControl.start() {
+    SET_BIT(UCSR0B, TXEN0);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  command error_t Uart0TxControl.stop() {
+    CLR_BIT(UCSR0B, TXEN0);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  command error_t Uart0RxControl.start() {
+    SET_BIT(UCSR0B, RXEN0);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  command error_t Uart0RxControl.stop() {
+    CLR_BIT(UCSR0B, RXEN0);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  async command error_t HplUart0.enableTxIntr() {
+    SET_BIT(UCSR0A, TXC0);
+    SET_BIT(UCSR0B, TXCIE0);
+    return SUCCESS;
+  }
+
+  async command error_t HplUart0.disableTxIntr(){
+    CLR_BIT(UCSR0B, TXCIE0);
+    return SUCCESS;
+  }
+
+  async command error_t HplUart0.enableRxIntr(){
+    SET_BIT(UCSR0B, RXCIE0);
+    return SUCCESS;
+  }
+
+  async command error_t HplUart0.disableRxIntr(){
+    CLR_BIT(UCSR0B, RXCIE0);
+    return SUCCESS;
+  }
+
+  async command bool HplUart0.isTxEmpty(){
+    return READ_BIT(UCSR0A, TXC0);
+  }
+
+  async command bool HplUart0.isRxEmpty(){
+    return !READ_BIT(UCSR0A, RXC0);
+  }
+
+  async command uint8_t HplUart0.rx(){
+    return UDR0;
+  }
+
+  async command void HplUart0.tx(uint8_t data) {
+    atomic{
+      UDR0 = data;
+      SET_BIT(UCSR0A, TXC0);
+    }
+  }
+
+  AVR_ATOMIC_HANDLER(USART0_RX_vect) {
+    if (READ_BIT(UCSR0A, RXC0)) {
+      signal HplUart0.rxDone(UDR0);
+    }
+  }
+
+  AVR_NONATOMIC_HANDLER(USART0_TX_vect) {
+    signal HplUart0.txDone();
+  }
+
+  command error_t Uart1Init.init() {
+    Atm128UartMode_t    mode;
+    Atm128UartStatus_t  stts;
+    Atm128UartControl_t ctrl;
+    uint16_t ubrr1;
+
+    ctrl.bits = (struct Atm128_UCSRB_t) {rxcie:0, txcie:0, rxen:0, txen:0};
+    stts.bits = (struct Atm128_UCSRA_t) {u2x:1};
+    mode.bits = (struct Atm128_UCSRC_t)  
{ucsz:ATM128_UART_DATA_SIZE_8_BITS};
+
+    ubrr1 = call Atm128Calibrate.baudrateRegister(PLATFORM_BAUDRATE);
+    UBRR1L = ubrr1;
+    UBRR1H = ubrr1 >> 8;
+    UCSR1A = stts.flat;
+    UCSR1C = mode.flat;
+    UCSR1B = ctrl.flat;
+
+    return SUCCESS;
+  }
+
+  command error_t Uart1TxControl.start() {
+    SET_BIT(UCSR1B, TXEN1);
+    CLR_BIT(UCSR1B, TXCIE1);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  command error_t Uart1TxControl.stop() {
+    CLR_BIT(UCSR1B, TXEN1);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  command error_t Uart1RxControl.start() {
+    SET_BIT(UCSR1B, RXEN1);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  command error_t Uart1RxControl.stop() {
+    CLR_BIT(UCSR1B, RXEN1);
+    call McuPowerState.update();
+    return SUCCESS;
+  }
+
+  async command error_t HplUart1.enableTxIntr() {
+    SET_BIT(UCSR1A, TXC1);
+    SET_BIT(UCSR1B, TXCIE1);
+    return SUCCESS;
+  }
+
+
+
+  async command error_t HplUart1.disableTxIntr(){
+    CLR_BIT(UCSR1B, TXCIE1);
+    return SUCCESS;
+  }
+
+  async command error_t HplUart1.enableRxIntr(){
+    SET_BIT(UCSR1B, RXCIE1);
+    return SUCCESS;
+  }
+
+  async command error_t HplUart1.disableRxIntr(){
+    CLR_BIT(UCSR1B, RXCIE1);
+    return SUCCESS;
+  }
+
+  async command bool HplUart1.isTxEmpty() {
+    return READ_BIT(UCSR1A, TXC1);
+  }
+
+  async command bool HplUart1.isRxEmpty() {
+    return !READ_BIT(UCSR1A, RXC1);
+  }
+
+  async command uint8_t HplUart1.rx(){
+    return UDR1;
+  }
+
+  async command void HplUart1.tx(uint8_t data) {
+    atomic{
+      UDR1 = data;
+      SET_BIT(UCSR1A, TXC1);
+    }
+  }
+
+  AVR_ATOMIC_HANDLER(USART1_RX_vect) {
+    if (READ_BIT(UCSR1A, RXC1))
+      signal HplUart1.rxDone(UDR1);
+  }
+
+  AVR_NONATOMIC_HANDLER(USART1_TX_vect) {
+    signal HplUart1.txDone();
+  }
+
+  async command mcu_power_t McuPowerOverride.lowestState() {
+    if ( (UCSR0B & (1<<TXEN0)) || (UCSR0B & (1<<RXEN0)) || (UCSR1B &  
(1<<TXEN1)) || (UCSR1B & (1<<RXEN1)) )
+      return ATM128_POWER_IDLE;
+    else
+      return ATM128_POWER_DOWN;
+  }
+
+  default async event void HplUart0.txDone() {}
+  default async event void HplUart0.rxDone(uint8_t data) {}
+  default async event void HplUart1.txDone() {}
+  default async event void HplUart1.rxDone(uint8_t data) {}
+
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/McuInitC.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2010, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+configuration McuInitC @safe()
+{
+	provides interface Init;
+
+	uses
+	{
+		interface Init as TimerInit;
+	}
+}
+
+implementation
+{
+	components McuInitP, MeasureClockC;
+
+	Init = McuInitP.Init;
+	TimerInit = McuInitP.TimerInit;
+
+	McuInitP.MeasureClock -> MeasureClockC;
+
+#ifdef TOGGLE_ON_SLEEP
+	// this is a HACK, but becasue of some compiling issues
+	// we cannot make McuInitC into a configuration
+	components McuSleepC, LedsC;
+	McuSleepC.Leds -> LedsC;
+#endif
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/McuInitP.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2010, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+#include "TimerConfig.h"
+module McuInitP @safe()
+{
+	provides interface Init;
+
+	uses
+	{
+		interface Init as MeasureClock;
+		interface Init as TimerInit;
+	}
+}
+
+implementation
+{
+	error_t systemClockInit()
+	{
+		// set the clock prescaler
+		atomic
+		{
+			// enable changing the prescaler
+			CLKPR = 0x80;
+
+#if PLATFORM_MHZ == 16
+			CLKPR = 0x0F;
+#elif PLATFORM_MHZ == 8
+			CLKPR = 0x00;
+#elif PLATFORM_MHZ == 4
+			CLKPR = 0x01;
+#elif PLATFORM_MHZ == 2
+			CLKPR = 0x02;
+#elif PLATFORM_MHZ == 1
+			CLKPR = 0x03;
+#else
+	#error "Unsupported MHZ"
+#endif
+		}
+
+		return SUCCESS;
+	}
+
+	command error_t Init.init()
+	{
+		error_t ok;
+		//workaround for errata 38.5.1 in datasheet
+		if(VERSION_NUM==3){//revision c (1.1)
+			DRTRAM0|=1<<ENDRT;
+			DRTRAM1|=1<<ENDRT;
+			DRTRAM2|=1<<ENDRT;
+			DRTRAM3|=1<<ENDRT;
+		}
+
+		ok = systemClockInit();
+		ok = ecombine(ok, call MeasureClock.init());
+		ok = ecombine(ok, call TimerInit.init());
+
+		return ok;
+	}
+
+	default command error_t TimerInit.init()
+	{
+		return SUCCESS;
+	}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/McuSleepC.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2005 Stanford University. All rights reserved.
+ * Copyright (c) 2007, Vanderbilt University
+ * Copyright (c) 2010, University of Szeged
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holders nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @author Philip Levis
+ * @author Robert Szewczyk
+ * @author Janos Sallai <janos.sallai at vanderbilt.edu>
+ */
+
+module McuSleepC @safe()
+{
+  provides {
+    interface McuSleep;
+    interface McuPowerState;
+  }
+  uses {
+    interface McuPowerOverride;
+    interface Leds @atmostonce();
+  }
+}
+
+implementation
+{
+  /* Note that the power values are maintained in an order
+   * based on their active components, NOT on their values.
+   * Look at atm1281hardware.h and page 54 of the ATmeg1281
+   * manual (Table 25).*/
+  const_uint8_t atm128PowerBits[ATM128_POWER_DOWN + 1] = {
+    0,	//IDLE
+    (1 << SM0),	//ADC_NR
+    (1 << SM2) | (1 << SM1) | (1 << SM0),	//EXT_STDBY
+    (1 << SM1) | (1 << SM0),	//POWER_SAVE
+    (1 << SM2) | (1 << SM1),	//STDBY
+    (1 << SM1)	//POWER_DOWN
+  };
+
+  norace int8_t powerState = -1;
+
+  async command void McuSleep.sleep()
+  {
+    if( powerState < 0 ) {
+      powerState = call McuPowerOverride.lowestState();
+      SMCR = (SMCR & 0xf0) | read_uint8_t(&atm128PowerBits[powerState]);
+    }
+
+#ifdef TOGGLE_ON_SLEEP
+    if( powerState >= ATM128_POWER_SAVE )
+      call Leds.led0Off();
+#endif
+
+    SET_BIT(SMCR, SE);
+
+    sei();
+    // All of memory may change at this point...
+    asm volatile ("sleep" : : : "memory");
+    cli();
+
+    CLR_BIT(SMCR, SE);
+
+#ifdef TOGGLE_ON_SLEEP
+    call Leds.led0On();
+#endif
+  }
+
+  async command void McuPowerState.update()
+  {
+   	powerState = -1;
+  }
+
+  default async command mcu_power_t McuPowerOverride.lowestState()
+  {
+    return ATM128_POWER_DOWN;
+  }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/adc/Atm128Adc.h	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,202 @@
+// $Id: Atm128Adc.h,v 1.2 2010-09-20 08:12:04 szabomeister Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written  
agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL CROSSBOW TECHNOLOGY OR ANY OF ITS LICENSORS BE LIABLE  
TO
+ * ANY PARTY FOR DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
+ * DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION,  
EVEN
+ * IF CROSSBOW OR ITS LICENSOR HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
+ * DAMAGE.
+ *
+ * CROSSBOW TECHNOLOGY AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL  
WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
+ * ON AN "AS IS" BASIS, AND NEITHER CROSSBOW NOR ANY LICENSOR HAS ANY
+ * OBLIGATION TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR
+ * MODIFICATIONS.
+ */
+
+// @author Martin Turon <mturon at xbow.com>
+// @author Hu Siquan <husq at xbow.com>
+
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written  
agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING  
OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE  
VANDERBILT
+ * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER  
IS
+ * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+ *
+ */
+
+// @author Janos Sallai <janos.sallai at vanderbilt.edu>
+
+/*
+   Updated chips/atm128 to include atm1281's ADCSRB register.
+*/
+
+#ifndef _H_Atm128ADC_h
+#define _H_Atm128ADC_h
+
+//================== 8 channel 10-bit ADC ==============================
+
+/* Voltage Reference Settings */
+enum {
+    ATM128_ADC_VREF_OFF = 0, //!< VR+ = AREF         and VR- = GND
+    ATM128_ADC_VREF_AVDD = 1,//!< VR+ = AVDD(1.8V)   and VR- = GND
+    ATM128_ADC_VREF_1_5 = 2, //!< VR+ = 1.5V         and VR- = GND
+    ATM128_ADC_VREF_1_6 = 3, //!< VR+ = 1.6V         and VR- = GND
+    ATM128_ADC_VREF_AVCC = ATM128_ADC_VREF_AVDD,	//backward compatibility
+};
+
+/* Voltage Reference Settings */
+enum {
+    ATM128_ADC_RIGHT_ADJUST = 0,
+    ATM128_ADC_LEFT_ADJUST = 1,
+};
+
+
+/* ADC Multiplexer Settings */
+enum {
+    ATM128_ADC_SNGL_ADC0 = 0,
+    ATM128_ADC_SNGL_ADC1,
+    ATM128_ADC_SNGL_ADC2,
+    ATM128_ADC_SNGL_ADC3,
+    ATM128_ADC_SNGL_ADC4,
+    ATM128_ADC_SNGL_ADC5,
+    ATM128_ADC_SNGL_ADC6,
+    ATM128_ADC_SNGL_ADC7,
+    ATM128_ADC_DIFF_ADC00_10x,
+    ATM128_ADC_DIFF_ADC10_10x,
+    ATM128_ADC_DIFF_ADC00_200x,
+    ATM128_ADC_DIFF_ADC10_200x,
+    ATM128_ADC_DIFF_ADC22_10x,
+    ATM128_ADC_DIFF_ADC32_10x,
+    ATM128_ADC_DIFF_ADC22_200x,
+    ATM128_ADC_DIFF_ADC32_200x,
+    ATM128_ADC_DIFF_ADC01_1x,
+    ATM128_ADC_DIFF_ADC11_1x,
+    ATM128_ADC_DIFF_ADC21_1x,
+    ATM128_ADC_DIFF_ADC31_1x,
+    ATM128_ADC_DIFF_ADC41_1x,
+    ATM128_ADC_DIFF_ADC51_1x,
+    ATM128_ADC_DIFF_ADC61_1x,
+    ATM128_ADC_DIFF_ADC71_1x,
+    ATM128_ADC_DIFF_ADC02_1x,
+    ATM128_ADC_DIFF_ADC12_1x,
+    ATM128_ADC_DIFF_ADC22_1x,
+    ATM128_ADC_DIFF_ADC32_1x,
+    ATM128_ADC_DIFF_ADC42_1x,
+    ATM128_ADC_DIFF_ADC52_1x,
+    ATM128_ADC_SNGL_1_23,
+    ATM128_ADC_SNGL_GND,
+    ATM128_ADC_INT_TEMP = 41,
+    ATM128_ADC_INT_VDRTBBP = 52,
+    ATM128_ADC_INT_VDRTBBN = 61,
+};
+
+/* ADC Multiplexer Selection Register */
+typedef struct
+{
+    uint8_t mux   : 5;  //!< Analog Channel and Gain Selection Bits
+    uint8_t adlar : 1;  //!< ADC Left Adjust Result
+    uint8_t refs  : 2;  //!< Reference Selection Bits
+} Atm128Admux_t;
+
+/* ADC Prescaler Settings */
+/* Note: each platform must define ATM128_ADC_PRESCALE to the smallest
+   prescaler which guarantees full A/D precision. */
+enum {
+    ATM128_ADC_PRESCALE_2 = 0,
+    ATM128_ADC_PRESCALE_2b,
+    ATM128_ADC_PRESCALE_4,
+    ATM128_ADC_PRESCALE_8,
+    ATM128_ADC_PRESCALE_16,
+    ATM128_ADC_PRESCALE_32,
+    ATM128_ADC_PRESCALE_64,
+    ATM128_ADC_PRESCALE_128,
+
+    // This special value is used to ask the platform for the prescaler
+    // which gives full precision.
+    ATM128_ADC_PRESCALE
+};
+
+/* ADC Enable Settings */
+enum {
+    ATM128_ADC_ENABLE_OFF = 0,
+    ATM128_ADC_ENABLE_ON,
+};
+
+/* ADC Start Conversion Settings */
+enum {
+    ATM128_ADC_START_CONVERSION_OFF = 0,
+    ATM128_ADC_START_CONVERSION_ON,
+};
+
+/* ADC Free Running Select Settings */
+enum {
+    ATM128_ADC_FREE_RUNNING_OFF = 0,
+    ATM128_ADC_FREE_RUNNING_ON,
+};
+
+/* ADC Interrupt Flag Settings */
+enum {
+    ATM128_ADC_INT_FLAG_OFF = 0,
+    ATM128_ADC_INT_FLAG_ON,
+};
+
+/* ADC Interrupt Enable Settings */
+enum {
+    ATM128_ADC_INT_ENABLE_OFF = 0,
+    ATM128_ADC_INT_ENABLE_ON,
+};
+
+/* ADC Multiplexer Selection Register */
+typedef struct
+{
+    uint8_t adps  : 3;  //!< ADC Prescaler Select Bits
+    uint8_t adie  : 1;  //!< ADC Interrupt Enable
+    uint8_t adif  : 1;  //!< ADC Interrupt Flag
+    uint8_t adate : 1;  //!< ADC Auto Trigger Enable
+    uint8_t adsc  : 1;  //!< ADC Start Conversion
+    uint8_t aden  : 1;  //!< ADC Enable
+} Atm128Adcsra_t;
+
+/* ADC Multiplexer Selection Register */
+typedef struct
+{
+    uint8_t adts  : 3;  //!< ADC Trigger Select
+    uint8_t mux5  : 1;  //!< Analog Channel and Gain Selection Bit
+    uint8_t acch  : 1;  //!< Analog Channel Change
+    uint8_t refok : 1;  //!< Reference Voltage OK
+    uint8_t acme  : 1;  //!< Analog Comparator Multiplexer Enable
+    uint8_t avddok: 1;  //!< AVDD Supply Voltage OK
+} Atm128Adcsrb_t;
+
+
+typedef uint8_t Atm128_ADCH_t;         //!< ADC data register high
+typedef uint8_t Atm128_ADCL_t;         //!< ADC data register low
+
+// The resource identifier string for the ADC subsystem
+#define UQ_ATM128ADC_RESOURCE "atm128adc.resource"
+
+#endif //_H_Atm128ADC_h
+
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/adc/HplAtm128AdcC.nc	Sun Sep  4 02:04:37  
2011
@@ -0,0 +1,53 @@
+/// $Id: HplAtm128AdcC.nc,v 1.7 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "Atm128Adc.h"
+
+/**
+ * HPL for the Atmega128 A/D conversion susbsystem.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ * @author Hu Siquan <husq at xbow.com>
+ * @author David Gay
+ */
+
+configuration HplAtm128AdcC {
+  provides interface HplAtm128Adc;
+}
+implementation {
+  components HplAtm128AdcP, McuSleepC;
+
+  HplAtm128Adc = HplAtm128AdcP;
+  HplAtm128AdcP.McuPowerState -> McuSleepC;
+	HplAtm128AdcP.McuPowerOverride <- McuSleepC;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/adc/HplAtm128AdcP.nc	Sun Sep  4 02:04:37  
2011
@@ -0,0 +1,158 @@
+/// $Id: HplAtm128AdcP.nc,v 1.1 2010-11-10 11:05:37 andrasbiro Exp $
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holders nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include "Atm128Adc.h"
+
+/**
+ * HPL for the Atmega1281 A/D conversion susbsystem.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ * @author Hu Siquan <husq at xbow.com>
+ * @author David Gay
+ * @author Janos Sallai <janos.sallai at vanderbilt.edu>
+ */
+
+module HplAtm128AdcP @safe() {
+  provides interface HplAtm128Adc;
+	provides interface McuPowerOverride;
+  uses interface McuPowerState;
+}
+implementation {
+  //=== Direct read of HW registers. =================================
+  async command Atm128Admux_t HplAtm128Adc.getAdmux() {
+    return *(Atm128Admux_t*)&ADMUX;
+  }
+  async command Atm128Adcsra_t HplAtm128Adc.getAdcsra() {
+    return *(Atm128Adcsra_t*)&ADCSRA;
+  }
+  async command uint16_t HplAtm128Adc.getValue() {
+    return ADC;
+  }
+
+  DEFINE_UNION_CAST(Admux2int, Atm128Admux_t, uint8_t);
+  DEFINE_UNION_CAST(Adcsra2int, Atm128Adcsra_t, uint8_t);
+
+  //=== Direct write of HW registers. ================================
+  async command void HplAtm128Adc.setAdmux( Atm128Admux_t x ) {
+    ADMUX = Admux2int(x);
+  }
+  async command void HplAtm128Adc.setAdcsra( Atm128Adcsra_t x ) {
+    ADCSRA = Adcsra2int(x);
+  }
+
+  async command void HplAtm128Adc.setPrescaler(uint8_t scale){
+    Atm128Adcsra_t  current_val = call HplAtm128Adc.getAdcsra();
+    current_val.adif = FALSE;
+    current_val.adps = scale;
+    call HplAtm128Adc.setAdcsra(current_val);
+  }
+
+  // Individual bit manipulation. These all clear any pending A/D  
interrupt.
+  // It's not clear these are that useful...
+  async command void HplAtm128Adc.enableAdc() {
+    SET_BIT(ADCSRA, ADEN);
+    call McuPowerState.update();
+  }
+  async command void HplAtm128Adc.disableAdc() {
+    CLR_BIT(ADCSRA, ADEN);
+    call McuPowerState.update();
+  }
+  async command void HplAtm128Adc.enableInterruption() { SET_BIT(ADCSRA,  
ADIE); }
+  async command void HplAtm128Adc.disableInterruption() { CLR_BIT(ADCSRA,  
ADIE); }
+  async command void HplAtm128Adc.setContinuous() {
+    ((Atm128Adcsrb_t*)&ADCSRB)->adts = 0;
+    SET_BIT(ADCSRA, ADATE);
+  }
+  async command void HplAtm128Adc.setSingle() { CLR_BIT(ADCSRA, ADATE); }
+  async command void HplAtm128Adc.resetInterrupt() { SET_BIT(ADCSRA,  
ADIF); }
+  async command void HplAtm128Adc.startConversion() { SET_BIT(ADCSRA,  
ADSC); }
+
+
+  /* A/D status checks */
+  async command bool HplAtm128Adc.isEnabled()     {
+    return (call HplAtm128Adc.getAdcsra()).aden;
+  }
+
+  async command bool HplAtm128Adc.isStarted()     {
+    return (call HplAtm128Adc.getAdcsra()).adsc;
+  }
+
+  async command bool HplAtm128Adc.isComplete()    {
+    return (call HplAtm128Adc.getAdcsra()).adif;
+  }
+
+  /* A/D interrupt handlers. Signals dataReady event with interrupts  
enabled */
+  AVR_ATOMIC_HANDLER(ADC_vect) {
+    uint16_t data = call HplAtm128Adc.getValue();
+
+    __nesc_enable_interrupt();
+    signal HplAtm128Adc.dataReady(data);
+  }
+
+  default async event void HplAtm128Adc.dataReady(uint16_t done) { }
+
+	async command mcu_power_t McuPowerOverride.lowestState() {
+		if(bit_is_set(ADCSRA,ADEN)) {
+			return ATM128_POWER_ADC_NR;
+		}
+		else
+			return ATM128_POWER_DOWN;
+	}
+
+  async command bool HplAtm128Adc.cancel() {
+    /* This is tricky */
+    atomic
+      {
+	Atm128Adcsra_t oldSr = call HplAtm128Adc.getAdcsra(), newSr;
+
+	/* To cancel a conversion, first turn off ADEN, then turn off
+	   ADSC. We also cancel any pending interrupt.
+	   Finally we reenable the ADC.
+	*/
+	newSr = oldSr;
+	newSr.aden = FALSE;
+	newSr.adif = TRUE; /* This clears a pending interrupt... */
+	newSr.adie = FALSE; /* We don't want to start sampling again at the
+			       next sleep */
+	call HplAtm128Adc.setAdcsra(newSr);
+	newSr.adsc = FALSE;
+	call HplAtm128Adc.setAdcsra(newSr);
+	newSr.aden = TRUE;
+	call HplAtm128Adc.setAdcsra(newSr);
+
+	return oldSr.adif || oldSr.adsc;
+      }
+  }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/atm128hardware.h	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,193 @@
+/*
+ *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
+ *  downloading, copying, installing or using the software you agree to
+ *  this license.  If you do not agree to this license, do not download,
+ *  install, copy or use the software.
+ *
+ *  Copyright (c) 2004-2005 Crossbow Technology, Inc.
+ *  Copyright (c) 2002-2003 Intel Corporation.
+ *  Copyright (c) 2000-2003 The Regents of the University  of California.
+ *  All rights reserved.
+ *
+ *  Permission to use, copy, modify, and distribute this software and its
+ *  documentation for any purpose, without fee, and without written
+ *  agreement is hereby granted, provided that the above copyright
+ *  notice, the (updated) modification history and the author appear in
+ *  all copies of this source code.
+ *
+ *  Permission is also granted to distribute this software under the
+ *  standard BSD license as contained in the TinyOS distribution.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ *  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE INTEL OR ITS
+ *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Permission to use, copy, modify, and distribute this software and its
+ * documentation for any purpose, without fee, and without written  
agreement is
+ * hereby granted, provided that the above copyright notice, the following
+ * two paragraphs and the author appear in all copies of this software.
+ *
+ * IN NO EVENT SHALL THE VANDERBILT UNIVERSITY BE LIABLE TO ANY PARTY FOR
+ * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING  
OUT
+ * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE  
VANDERBILT
+ * UNIVERSITY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * THE VANDERBILT UNIVERSITY SPECIFICALLY DISCLAIMS ANY WARRANTIES,
+ * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
+ * AND FITNESS FOR A PARTICULAR PURPOSE.  THE SOFTWARE PROVIDED HEREUNDER  
IS
+ * ON AN "AS IS" BASIS, AND THE VANDERBILT UNIVERSITY HAS NO OBLIGATION TO
+ * PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
+ *
+ */
+
+/*
+ *  Updated chips/atm128/atm128hardware.h with atm1281's MCU status and
+ *  memory control registers.
+ *
+ *  @author Janos Sallai, Martin Turon, Jason Hill, Philip Levis, Nelson  
Lee, David Gay
+ */
+
+
+#ifndef _H_atmega128hardware_H
+#define _H_atmega128hardware_H
+
+#include <avr/io.h>
+#if __AVR_LIBC_VERSION__ >= 10400UL
+#include <avr/interrupt.h>
+#else
+#include <avr/interrupt.h>
+#include <avr/signal.h>
+#endif
+#include <avr/wdt.h>
+#include <avr/pgmspace.h>
+#include "atm128const.h"
+
+/* We need slightly different defs than SIGNAL, INTERRUPT */
+#define AVR_ATOMIC_HANDLER(signame) \
+  void signame() __attribute__ ((signal)) @atomic_hwevent() @C()
+
+#define AVR_NONATOMIC_HANDLER(signame) \
+  void signame() __attribute__ ((interrupt)) @hwevent() @C()
+
+/* Macro to create union casting functions. */
+#define DEFINE_UNION_CAST(func_name, from_type, to_type) \
+  to_type func_name(from_type x) { \
+  union {from_type f; to_type t;} c = {f:x}; return c.t; }
+
+// Bit operators using bit number
+#define SET_BIT(port, bit)    ((port) |= _BV(bit))
+#define CLR_BIT(port, bit)    ((port) &= ~_BV(bit))
+#define READ_BIT(port, bit)   (((port) & _BV(bit)) != 0)
+#define FLIP_BIT(port, bit)   ((port) ^= _BV(bit))
+#define WRITE_BIT(port, bit, value) \
+   if (value) SET_BIT((port), (bit)); \
+   else CLR_BIT((port), (bit))
+
+// Bit operators using bit flag mask
+#define SET_FLAG(port, flag)  ((port) |= (flag))
+#define CLR_FLAG(port, flag)  ((port) &= ~(flag))
+#define READ_FLAG(port, flag) ((port) & (flag))
+
+/* Enables interrupts. */
+inline void __nesc_enable_interrupt() @safe() {
+    sei();
+}
+/* Disables all interrupts. */
+inline void __nesc_disable_interrupt() @safe() {
+    cli();
+}
+
+/* Defines data type for storing interrupt mask state during atomic. */
+typedef uint8_t __nesc_atomic_t;
+__nesc_atomic_t __nesc_atomic_start(void);
+void __nesc_atomic_end(__nesc_atomic_t original_SREG);
+
+#ifndef NESC_BUILD_BINARY
+/* @spontaneous() functions should not be included when NESC_BUILD_BINARY
+   is #defined, to avoid duplicate functions definitions wheb binary
+   components are used. Such functions do need a prototype in all cases,
+   though. */
+
+/* Saves current interrupt mask state and disables interrupts. */
+inline __nesc_atomic_t
+__nesc_atomic_start(void) @spontaneous() @safe()
+{
+    __nesc_atomic_t result = SREG;
+    __nesc_disable_interrupt();
+    asm volatile("" : : : "memory"); /* ensure atomic section effect  
visibility */
+    return result;
+}
+
+/* Restores interrupt mask to original state. */
+inline void
+__nesc_atomic_end(__nesc_atomic_t original_SREG) @spontaneous() @safe()
+{
+  asm volatile("" : : : "memory"); /* ensure atomic section effect  
visibility */
+  SREG = original_SREG;
+}
+#endif
+
+/* Defines the mcu_power_t type for atm128 power management. */
+typedef uint8_t mcu_power_t @combine("mcombine");
+
+
+enum {
+  ATM128_POWER_IDLE        = 0,
+  ATM128_POWER_ADC_NR      = 1,
+  ATM128_POWER_EXT_STANDBY = 2,
+  ATM128_POWER_SAVE        = 3,
+  ATM128_POWER_STANDBY     = 4,
+  ATM128_POWER_DOWN        = 5,
+};
+
+/* Combine function.  */
+mcu_power_t mcombine(mcu_power_t m1, mcu_power_t m2) @safe() {
+  return (m1 < m2)? m1: m2;
+}
+
+/* MCU Status Register*/
+typedef struct
+{
+  uint8_t porf  : 1;    //!< Power-on Reset Flag
+  uint8_t extrf : 1;    //!< External Reset Flag
+  uint8_t borf  : 1;    //!< Brown-out Reset Flag
+  uint8_t wdrf  : 1;    //!< Watchdog Reset Flag
+  uint8_t jtrf  : 1;    //!< JTAG Reset Flag
+  uint8_t resv1 : 3;    //!< Reserved
+} Atm128_MCUSR_t;
+
+
+
+/* Floating-point network-type support.
+   These functions must convert to/from a 32-bit big-endian integer that  
follows
+   the layout of Java's java.lang.float.floatToRawIntBits method.
+   Conveniently, for the AVR family, this is a straight byte copy...
+*/
+
+typedef float nx_float __attribute__((nx_base_be(afloat)));
+
+inline float __nesc_ntoh_afloat(const void *COUNT(sizeof(float)) source)  
@safe() {
+  float f;
+  memcpy(&f, source, sizeof(float));
+  return f;
+}
+
+inline float __nesc_hton_afloat(void *COUNT(sizeof(float)) target, float  
value) @safe() {
+  memcpy(target, &value, sizeof(float));
+  return value;
+}
+
+#endif //_H_atmega128hardware_H
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/i2c/HplAtm128I2CBusC.nc	Sun Sep  4 02:04:37  
2011
@@ -0,0 +1,60 @@
+/// $Id: HplAtm128I2CBusC.nc,v 1.5 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ *  Copyright (c) 2004-2006 Crossbow Technology, Inc.
+ *  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * This driver implements direct I2C register access and a blocking master
+ * controller for the ATmega128 via a Hardware Platform Layer (HPL) to its
+ * two-wire-interface (TWI) hardware subsystem.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ * @author Philip Levis
+ *
+ * @version    $Id: HplAtm128I2CBusC.nc,v 1.5 2010-06-29 22:07:43 scipio  
Exp $
+ */
+
+configuration HplAtm128I2CBusC {
+  provides interface HplAtm128I2CBus as I2C;
+}
+implementation {
+
+  components HplAtm128GeneralIOC as IO, HplAtm128I2CBusP as Bus;
+	components McuSleepC;
+
+  I2C         = Bus.I2C;
+  Bus.I2CClk  -> IO.PortD0;
+  Bus.I2CData -> IO.PortD1;
+
+	Bus.McuPowerState -> McuSleepC;
+	Bus.McuPowerOverride <- McuSleepC;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/i2c/HplAtm128I2CBusP.nc	Sun Sep  4 02:04:37  
2011
@@ -0,0 +1,209 @@
+/// $Id: HplAtm128I2CBusP.nc,v 1.2 2010-11-19 22:55:12 szabomeister Exp $
+
+/*
+ *  Copyright (c) 2004-2005 Crossbow Technology, Inc.
+ *  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef I2C_PRESCALER
+  #define I2C_PRESCALER 0
+#endif
+#ifndef I2C_BITRATE
+  #ifndef I2C_FREQ
+      #define I2C_FREQ	50000U
+  #endif
+  #define TWBR_VALUE(cpu_mhz) ( ((cpu_mhz*500000)/I2C_FREQ)-8 )
+  #define I2C_BITRATE TWBR_VALUE(PLATFORM_MHZ)
+#endif
+
+#include "Atm128I2C.h"
+
+/**
+ * This driver implements direct I2C register access and a blocking master
+ * controller for the ATmega128 via a Hardware Platform Layer (HPL) to its
+ * two-wire-interface (TWI) hardware subsystem.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ * @author Philip Levis
+ *
+ * @version $Id: HplAtm128I2CBusP.nc,v 1.2 2010-11-19 22:55:12  
szabomeister Exp $
+ */
+module HplAtm128I2CBusP {
+  provides interface HplAtm128I2CBus as I2C;
+	provides interface McuPowerOverride;
+
+  uses {
+    interface GeneralIO as I2CClk;
+    interface GeneralIO as I2CData;
+    interface McuPowerState;
+  }
+}
+implementation {
+  uint8_t current;
+
+  async command void I2C.init(bool hasExternalPulldown) {
+    // Set the internal pullup resisters
+    if (hasExternalPulldown) {
+      call I2CClk.set();
+      call I2CData.set();
+    }
+    TWSR=I2C_PRESCALER;
+    TWBR=I2C_BITRATE;
+    TWAR = 0;
+    TWCR = 0;
+  }
+
+  async command void I2C.off() {
+    call I2CClk.clr();
+    call I2CData.clr();
+  }
+
+  async command uint8_t I2C.status() {
+    return TWSR & 0xf8;
+  }
+
+  async command void I2C.sendCommand() {
+    atomic TWCR = current;
+  }
+
+  async command void I2C.readCurrent() {
+    atomic current = TWCR;
+  }
+
+  /** Send START symbol and begin I2C bus transaction. */
+  async command void I2C.setStart(bool on) {
+    if (on) {
+      atomic SET_BIT(current, TWSTA);
+    }
+    else {
+      atomic CLR_BIT(current, TWSTA);
+    }
+  }
+  async command bool I2C.hasStart() {
+    return READ_BIT(current, TWSTA);
+  }
+
+  async command void I2C.setStop(bool on) {
+    if (on) {
+      atomic SET_BIT(current, TWSTO);
+    }
+    else {
+      atomic CLR_BIT(current, TWSTO);
+    }
+  }
+  async command bool I2C.hasStop() {
+    return READ_BIT(current, TWSTO);
+  }
+
+  /** Write a byte to an I2C slave device. */
+  async command void I2C.write(uint8_t data) {
+    TWDR = data;
+  }
+
+  async command uint8_t I2C.read() {
+    return TWDR;
+  }
+
+  async command void I2C.enableAck(bool enable) {
+    if (enable) {
+      atomic SET_BIT(current, TWEA);
+    }
+    else {
+      atomic CLR_BIT(current, TWEA);
+    }
+  }
+
+  async command bool I2C.hasAcks() {
+    return READ_BIT(current, TWEA);
+  }
+
+  async command void I2C.enableInterrupt(bool enable) {
+    if (enable) {
+      atomic SET_BIT(current, TWIE);
+    }
+    else {
+      atomic CLR_BIT(current, TWIE);
+    }
+  }
+
+  async command bool I2C.isInterruptEnabled() {
+    return READ_BIT(current, TWIE);
+  }
+
+  async command bool I2C.isRealInterruptPending() {
+    return READ_BIT(TWCR, TWINT);
+  }
+
+  async command bool I2C.isInterruptPending() {
+    return READ_BIT(current, TWINT);
+  }
+
+  async command void I2C.setInterruptPending(bool on) {
+    if (on) {
+      atomic SET_BIT(current, TWINT);
+    }
+    else {
+      atomic CLR_BIT(current, TWINT);
+    }
+  }
+
+  async command void I2C.enable(bool enable) {
+    if (enable) {
+      atomic SET_BIT(current, TWEN);
+    }
+    else {
+      atomic CLR_BIT(current, TWEN);
+    }
+    call McuPowerState.update();
+  }
+
+  async command bool I2C.isEnabled() {
+    return READ_BIT(current, TWEN);
+  }
+
+  async command bool I2C.hasWriteCollided() {
+    return READ_BIT(current, TWWC);
+  }
+
+  async command mcu_power_t McuPowerOverride.lowestState() {
+    if(bit_is_set(TWCR,TWEN)) {
+      return ATM128_POWER_IDLE;
+    }
+    else
+      return ATM128_POWER_DOWN;
+  }
+
+  default async event void I2C.commandComplete() { }
+
+  AVR_ATOMIC_HANDLER(TWI_vect) {
+    signal I2C.commandComplete();
+  }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/AtmegaExtInterrupt0C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Andras Biro
+ */
+
+configuration AtmegaExtInterrupt0C
+{
+  provides interface GpioInterrupt;
+}
+
+implementation
+{
+  components HplAtmegaExtInterrupt0C, new AtmegaExtInterruptP();
+
+  GpioInterrupt = AtmegaExtInterruptP;
+  AtmegaExtInterruptP.HplAtmegaExtInterrupt -> HplAtmegaExtInterrupt0C;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/AtmegaExtInterruptP.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Andras Biro
+ */
+
+#include "HplAtmegaExtInterrupt.h"
+
+generic module AtmegaExtInterruptP(){
+  uses interface HplAtmegaExtInterrupt;
+  provides interface GpioInterrupt;
+}
+implementation{
+
+  async command error_t GpioInterrupt.enableRisingEdge(){
+    atomic{
+      call HplAtmegaExtInterrupt.setMode(ATMEGA_EXTINT_RISING_EDGE);
+      call HplAtmegaExtInterrupt.enable();
+      call HplAtmegaExtInterrupt.reset();
+    }
+    return SUCCESS;
+  }
+
+  async command error_t GpioInterrupt.enableFallingEdge(){
+    atomic{
+      call HplAtmegaExtInterrupt.setMode(ATMEGA_EXTINT_FALLING_EDGE);
+      call HplAtmegaExtInterrupt.enable();
+      call HplAtmegaExtInterrupt.reset();
+    }
+    return SUCCESS;
+  }
+
+  async command error_t GpioInterrupt.disable(){
+    call HplAtmegaExtInterrupt.disable();
+    return SUCCESS;
+  }
+
+  async event void HplAtmegaExtInterrupt.fired(){
+    signal GpioInterrupt.fired();
+  }
+
+  default async event void GpioInterrupt.fired(){}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/AtmegaPinChange0C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+configuration AtmegaPinChange0C
+{
+	provides interface GpioInterrupt[uint8_t pin];
+}
+
+implementation
+{
+	components HplAtmegaPinChange0C, new AtmegaPinChangeP();
+
+	GpioInterrupt = AtmegaPinChangeP;
+	AtmegaPinChangeP.HplAtmegaPinChange -> HplAtmegaPinChange0C;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/AtmegaPinChange1C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+configuration AtmegaPinChange1C
+{
+	provides interface GpioInterrupt[uint8_t pin];
+}
+
+implementation
+{
+	components HplAtmegaPinChange1C, new AtmegaPinChangeP();
+
+	GpioInterrupt = AtmegaPinChangeP;
+	AtmegaPinChangeP.HplAtmegaPinChange -> HplAtmegaPinChange1C;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/AtmegaPinChangeP.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Andras Biro
+ */
+
+generic module AtmegaPinChangeP(){
+  uses interface HplAtmegaPinChange;
+  provides interface GpioInterrupt[uint8_t pin];
+}
+implementation{
+  uint8_t isFalling;
+
+  /* Enables the interrupt */
+  async command error_t GpioInterrupt.enableRisingEdge[uint8_t pin](){
+    atomic{
+      isFalling &= ~(1<<pin);
+      call HplAtmegaPinChange.setMask(call HplAtmegaPinChange.getMask() |  
(1<<pin));
+      call HplAtmegaPinChange.enable();
+    }
+    return SUCCESS;
+  }
+
+  async command error_t GpioInterrupt.enableFallingEdge[uint8_t pin](){
+    atomic {
+      isFalling |= 1<<pin;
+      call HplAtmegaPinChange.setMask(call HplAtmegaPinChange.getMask() |  
(1<<pin));
+      call HplAtmegaPinChange.enable();
+    }
+    return SUCCESS;
+  }
+
+  /* Disables the interrupt */
+  async command error_t GpioInterrupt.disable[uint8_t pin](){
+    atomic {
+      uint8_t mask = call HplAtmegaPinChange.getMask() & ~(1<<pin);
+      call HplAtmegaPinChange.setMask(mask);
+      if(mask==0)
+        call HplAtmegaPinChange.disable();
+    }
+    return SUCCESS;
+  }
+
+  /* Signalled when any of the enabled pins changed */
+  async event void HplAtmegaPinChange.fired(){
+    uint8_t pins=call HplAtmegaPinChange.getMask() & ( call  
HplAtmegaPinChange.getPins() ^ isFalling );
+    if( pins & (1<<0) )
+      signal GpioInterrupt.fired[0]();
+    if( pins & (1<<1) )
+      signal GpioInterrupt.fired[1]();
+    if( pins & (1<<2) )
+      signal GpioInterrupt.fired[2]();
+    if( pins & (1<<3) )
+      signal GpioInterrupt.fired[3]();
+    if( pins & (1<<4) )
+      signal GpioInterrupt.fired[4]();
+    if( pins & (1<<5) )
+      signal GpioInterrupt.fired[5]();
+    if( pins & (1<<6) )
+      signal GpioInterrupt.fired[6]();
+    if( pins & (1<<7) )
+      signal GpioInterrupt.fired[7]();
+
+  }
+
+  default async event void GpioInterrupt.fired[uint8_t pin]() {}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtm128GeneralIOC.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,199 @@
+/// $Id: HplAtm128GeneralIOC.nc,v 1.5 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atm128hardware.h>
+
+/**
+ * Provide GeneralIO interfaces for all of the ATmega128's pins.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ */
+
+configuration HplAtm128GeneralIOC
+{
+  // provides all the ports as raw ports
+  provides {
+    interface GeneralIO as PortA0;
+    interface GeneralIO as PortA1;
+    interface GeneralIO as PortA2;
+    interface GeneralIO as PortA3;
+    interface GeneralIO as PortA4;
+    interface GeneralIO as PortA5;
+    interface GeneralIO as PortA6;
+    interface GeneralIO as PortA7;
+
+    interface GeneralIO as PortB0;
+    interface GeneralIO as PortB1;
+    interface GeneralIO as PortB2;
+    interface GeneralIO as PortB3;
+    interface GeneralIO as PortB4;
+    interface GeneralIO as PortB5;
+    interface GeneralIO as PortB6;
+    interface GeneralIO as PortB7;
+
+    interface GeneralIO as PortC0;
+    interface GeneralIO as PortC1;
+    interface GeneralIO as PortC2;
+    interface GeneralIO as PortC3;
+    interface GeneralIO as PortC4;
+    interface GeneralIO as PortC5;
+    interface GeneralIO as PortC6;
+    interface GeneralIO as PortC7;
+
+    interface GeneralIO as PortD0;
+    interface GeneralIO as PortD1;
+    interface GeneralIO as PortD2;
+    interface GeneralIO as PortD3;
+    interface GeneralIO as PortD4;
+    interface GeneralIO as PortD5;
+    interface GeneralIO as PortD6;
+    interface GeneralIO as PortD7;
+
+    interface GeneralIO as PortE0;
+    interface GeneralIO as PortE1;
+    interface GeneralIO as PortE2;
+    interface GeneralIO as PortE3;
+    interface GeneralIO as PortE4;
+    interface GeneralIO as PortE5;
+    interface GeneralIO as PortE6;
+    interface GeneralIO as PortE7;
+
+    interface GeneralIO as PortF0;
+    interface GeneralIO as PortF1;
+    interface GeneralIO as PortF2;
+    interface GeneralIO as PortF3;
+    interface GeneralIO as PortF4;
+    interface GeneralIO as PortF5;
+    interface GeneralIO as PortF6;
+    interface GeneralIO as PortF7;
+
+    interface GeneralIO as PortG0;
+    interface GeneralIO as PortG1;
+    interface GeneralIO as PortG2;
+    interface GeneralIO as PortG3;
+    interface GeneralIO as PortG4;
+    interface GeneralIO as PortG5;
+  }
+}
+
+implementation
+{
+  components
+  new HplAtm128GeneralIOPortP((uint8_t)&PORTA, (uint8_t)&DDRA,  
(uint8_t)&PINA) as PortA,
+    new HplAtm128GeneralIOPortP((uint8_t)&PORTB, (uint8_t)&DDRB,  
(uint8_t)&PINB) as PortB,
+    new HplAtm128GeneralIOPortP((uint8_t)&PORTC, (uint8_t)&DDRC,  
(uint8_t)&PINC) as PortC,
+    new HplAtm128GeneralIOPortP((uint8_t)&PORTD, (uint8_t)&DDRD,  
(uint8_t)&PIND) as PortD,
+    new HplAtm128GeneralIOPortP((uint8_t)&PORTE, (uint8_t)&DDRE,  
(uint8_t)&PINE) as PortE,
+    new HplAtm128GeneralIOPortP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF) as PortF,
+
+  // PortF cannot use sbi, cbi
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 0) as F0,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 1) as F1,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 2) as F2,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 3) as F3,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 4) as F4,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 5) as F5,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 6) as F6,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTF, (uint8_t)&DDRF,  
(uint8_t)&PINF, 7) as F7,
+
+
+  // PortG only exposes 5 bits and cannot use sbi, cbi
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTG, (uint8_t)&DDRG,  
(uint8_t)&PING, 0) as G0,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTG, (uint8_t)&DDRG,  
(uint8_t)&PING, 1) as G1,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTG, (uint8_t)&DDRG,  
(uint8_t)&PING, 2) as G2,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTG, (uint8_t)&DDRG,  
(uint8_t)&PING, 3) as G3,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTG, (uint8_t)&DDRG,  
(uint8_t)&PING, 4) as G4,
+    new HplAtm128GeneralIOSlowPinP((uint8_t)&PORTG, (uint8_t)&DDRG,  
(uint8_t)&PING, 4) as G5
+    ;
+
+  PortA0 = PortA.Pin0;
+  PortA1 = PortA.Pin1;
+  PortA2 = PortA.Pin2;
+  PortA3 = PortA.Pin3;
+  PortA4 = PortA.Pin4;
+  PortA5 = PortA.Pin5;
+  PortA6 = PortA.Pin6;
+  PortA7 = PortA.Pin7;
+
+  PortB0 = PortB.Pin0;
+  PortB1 = PortB.Pin1;
+  PortB2 = PortB.Pin2;
+  PortB3 = PortB.Pin3;
+  PortB4 = PortB.Pin4;
+  PortB5 = PortB.Pin5;
+  PortB6 = PortB.Pin6;
+  PortB7 = PortB.Pin7;
+
+  PortC0 = PortC.Pin0;
+  PortC1 = PortC.Pin1;
+  PortC2 = PortC.Pin2;
+  PortC3 = PortC.Pin3;
+  PortC4 = PortC.Pin4;
+  PortC5 = PortC.Pin5;
+  PortC6 = PortC.Pin6;
+  PortC7 = PortC.Pin7;
+
+  PortD0 = PortD.Pin0;
+  PortD1 = PortD.Pin1;
+  PortD2 = PortD.Pin2;
+  PortD3 = PortD.Pin3;
+  PortD4 = PortD.Pin4;
+  PortD5 = PortD.Pin5;
+  PortD6 = PortD.Pin6;
+  PortD7 = PortD.Pin7;
+
+  PortE0 = PortE.Pin0;
+  PortE1 = PortE.Pin1;
+  PortE2 = PortE.Pin2;
+  PortE3 = PortE.Pin3;
+  PortE4 = PortE.Pin4;
+  PortE5 = PortE.Pin5;
+  PortE6 = PortE.Pin6;
+  PortE7 = PortE.Pin7;
+
+  PortF0 = PortF.Pin0;
+  PortF1 = PortF.Pin1;
+  PortF2 = PortF.Pin2;
+  PortF3 = PortF.Pin3;
+  PortF4 = PortF.Pin4;
+  PortF5 = PortF.Pin5;
+  PortF6 = PortF.Pin6;
+  PortF7 = PortF.Pin7;
+
+  PortG0 = G0;
+  PortG1 = G1;
+  PortG2 = G2;
+  PortG3 = G3;
+  PortG4 = G4;
+  PortG5 = G5;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtm128InterruptC.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,154 @@
+/// $Id: HplAtm128InterruptC.nc,v 1.5 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <atm128hardware.h>
+
+/**
+ * Component providing access to all external interrupt pins on ATmega128.
+ * @author Martin Turon <mturon at xbow.com>
+ */
+
+configuration HplAtm128InterruptC
+{
+  // provides all the ports as raw ports
+  provides {
+    interface HplAtm128Interrupt as Int0;
+    interface HplAtm128Interrupt as Int1;
+    interface HplAtm128Interrupt as Int2;
+    interface HplAtm128Interrupt as Int3;
+    interface HplAtm128Interrupt as Int4;
+    interface HplAtm128Interrupt as Int5;
+    interface HplAtm128Interrupt as Int6;
+    interface HplAtm128Interrupt as Int7;
+    interface GpioPCInterrupt as PCInt0;
+    interface GpioPCInterrupt as PCInt1;
+    interface GpioPCInterrupt as PCInt2;
+    interface GpioPCInterrupt as PCInt3;
+    interface GpioPCInterrupt as PCInt4;
+    interface GpioPCInterrupt as PCInt5;
+    interface GpioPCInterrupt as PCInt6;
+    interface GpioPCInterrupt as PCInt7;
+    interface GpioPCInterrupt as PCInt8;
+  }
+}
+implementation
+{
+#define IRQ_PORT_D_PIN(bit) (uint8_t)&EICRA, ISC##bit##0, ISC##bit##1, bit
+#define IRQ_PORT_E_PIN(bit) (uint8_t)&EICRB, ISC##bit##0, ISC##bit##1, bit
+
+
+  components
+    HplAtm128InterruptSigP as IrqVector, HplAtm128GeneralIOC as IO,
+    new HplAtm128InterruptPinP(IRQ_PORT_D_PIN(0)) as IntPin0,
+    new HplAtm128InterruptPinP(IRQ_PORT_D_PIN(1)) as IntPin1,
+    new HplAtm128InterruptPinP(IRQ_PORT_D_PIN(2)) as IntPin2,
+    new HplAtm128InterruptPinP(IRQ_PORT_D_PIN(3)) as IntPin3,
+    new HplAtm128InterruptPinP(IRQ_PORT_E_PIN(4)) as IntPin4,
+    new HplAtm128InterruptPinP(IRQ_PORT_E_PIN(5)) as IntPin5,
+    new HplAtm128InterruptPinP(IRQ_PORT_E_PIN(6)) as IntPin6,
+    new HplAtm128InterruptPinP(IRQ_PORT_E_PIN(7)) as IntPin7,
+    new HplAtm1281PCInterruptP(PCIE0, (uint8_t)&PCMSK0) as PCIntVect0,
+    new HplAtm1281PCInterruptP(PCIE1, (uint8_t)&PCMSK1) as PCIntVect1,
+    new NoPinC() as NoPin1, new NoPinC() as NoPin2, new NoPinC() as NoPin3,
+    new NoPinC() as NoPin4, new NoPinC() as NoPin5, new NoPinC() as NoPin6,
+    new NoPinC() as NoPin7,
+    McuSleepC;
+
+
+  Int0 = IntPin0;
+  Int1 = IntPin1;
+  Int2 = IntPin2;
+  Int3 = IntPin3;
+  Int4 = IntPin4;
+  Int5 = IntPin5;
+  Int6 = IntPin6;
+  Int7 = IntPin7;
+  PCInt0 = PCIntVect0.GpioPCInterrupt0;
+  PCInt1 = PCIntVect0.GpioPCInterrupt1;
+  PCInt2 = PCIntVect0.GpioPCInterrupt2;
+  PCInt3 = PCIntVect0.GpioPCInterrupt3;
+  PCInt4 = PCIntVect0.GpioPCInterrupt4;
+  PCInt5 = PCIntVect0.GpioPCInterrupt5;
+  PCInt6 = PCIntVect0.GpioPCInterrupt6;
+  PCInt7 = PCIntVect0.GpioPCInterrupt7;
+  PCInt8 = PCIntVect1.GpioPCInterrupt0;
+
+  IntPin0.IrqSignal -> IrqVector.IntSig0;
+  IntPin1.IrqSignal -> IrqVector.IntSig1;
+  IntPin2.IrqSignal -> IrqVector.IntSig2;
+  IntPin3.IrqSignal -> IrqVector.IntSig3;
+  IntPin4.IrqSignal -> IrqVector.IntSig4;
+  IntPin5.IrqSignal -> IrqVector.IntSig5;
+  IntPin6.IrqSignal -> IrqVector.IntSig6;
+  IntPin7.IrqSignal -> IrqVector.IntSig7;
+  PCIntVect0.IrqSignal -> IrqVector.PCIntSig0;
+  PCIntVect1.IrqSignal -> IrqVector.PCIntSig1;
+
+  PCIntVect0.Pin0 -> IO.PortB0;
+  PCIntVect0.Pin1 -> IO.PortB1;
+  PCIntVect0.Pin2 -> IO.PortB2;
+  PCIntVect0.Pin3 -> IO.PortB3;
+  PCIntVect0.Pin4 -> IO.PortB4;
+  PCIntVect0.Pin5 -> IO.PortB5;
+  PCIntVect0.Pin6 -> IO.PortB6;
+  PCIntVect0.Pin7 -> IO.PortB7;
+
+  PCIntVect1.Pin0 -> IO.PortE0;
+  PCIntVect1.Pin1 -> NoPin1;
+  PCIntVect1.Pin2 -> NoPin2;
+  PCIntVect1.Pin3 -> NoPin3;
+  PCIntVect1.Pin4 -> NoPin4;
+  PCIntVect1.Pin5 -> NoPin5;
+  PCIntVect1.Pin6 -> NoPin6;
+  PCIntVect1.Pin7 -> NoPin7;
+
+
+  IntPin0.McuPowerState -> McuSleepC;
+  IntPin1.McuPowerState -> McuSleepC;
+  IntPin2.McuPowerState -> McuSleepC;
+  IntPin3.McuPowerState -> McuSleepC;
+  IntPin4.McuPowerState -> McuSleepC;
+  IntPin5.McuPowerState -> McuSleepC;
+  IntPin6.McuPowerState -> McuSleepC;
+  IntPin7.McuPowerState -> McuSleepC;
+
+  IntPin0.McuPowerOverride <- McuSleepC;
+  IntPin1.McuPowerOverride <- McuSleepC;
+  IntPin2.McuPowerOverride <- McuSleepC;
+  IntPin3.McuPowerOverride <- McuSleepC;
+  IntPin4.McuPowerOverride <- McuSleepC;
+  IntPin5.McuPowerOverride <- McuSleepC;
+  IntPin6.McuPowerOverride <- McuSleepC;
+  IntPin7.McuPowerOverride <- McuSleepC;
+}
+
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtm128InterruptPinP.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,84 @@
+/// $Id: HplAtm128InterruptPinP.nc,v 1.7 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * Interrupt interface access for interrupt capable GPIO pins.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ */
+generic module HplAtm128InterruptPinP (uint8_t ctrl_addr,
+  uint8_t edge0bit,
+  uint8_t edge1bit,
+  uint8_t bit) @safe()
+{
+  provides interface HplAtm128Interrupt as Irq;
+  uses interface HplAtm128InterruptSig as IrqSignal;
+  provides interface McuPowerOverride;
+  uses interface McuPowerState;
+}
+implementation
+{
+  inline async command bool Irq.getValue() { return (EIFR & (1 << bit)) !=  
0; }
+  inline async command void Irq.clear()    { EIFR = 1 << bit; }
+  inline async command void Irq.enable()   { EIMSK |= 1 << bit; call  
McuPowerState.update(); }
+  inline async command void Irq.disable()  { EIMSK &= ~(1 << bit); call  
McuPowerState.update(); }
+
+#define ctrl  (*TCAST(volatile uint8_t * ONE, ctrl_addr))
+
+  inline async command void Irq.edge(bool low_to_high) {
+    ctrl |= 1 << edge1bit; // use edge mode
+    // and select rising vs falling
+    if (low_to_high)
+      ctrl |= 1 << edge0bit;
+    else
+      ctrl &= ~(1 << edge0bit);
+  }
+
+  async command mcu_power_t McuPowerOverride.lowestState() {
+    if(bit >= 4&&EIMSK&(1<<bit)) {
+      return ATM128_POWER_SAVE;
+    }
+    else {
+      return ATM128_POWER_DOWN;
+    }
+  }
+
+  /**
+   * Forward the external interrupt event.  This ties the statically
+   * allocated interrupt vector SIG_INTERRUPT##bit to a particular
+   * pin passed in via the generic component instantiation.
+   */
+  async event void IrqSignal.fired() { signal Irq.fired(); }
+
+  default async event void Irq.fired() { }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtm128InterruptSigP.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,93 @@
+/// $Id: HplAtm128InterruptSigP.nc,v 1.6 2010-06-29 22:07:43 scipio Exp $
+
+/*
+ * Copyright (c) 2004-2005 Crossbow Technology, Inc.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of Crossbow Technology nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * Interrupt interface access for interrupt capable GPIO pins.
+ * Exposes just the interrupt vector routine for
+ * easy linking to generic components.
+ *
+ * @author Martin Turon <mturon at xbow.com>
+ */
+module HplAtm128InterruptSigP @safe()
+{
+  provides interface HplAtm128InterruptSig as IntSig0;
+  provides interface HplAtm128InterruptSig as IntSig1;
+  provides interface HplAtm128InterruptSig as IntSig2;
+  provides interface HplAtm128InterruptSig as IntSig3;
+  provides interface HplAtm128InterruptSig as IntSig4;
+  provides interface HplAtm128InterruptSig as IntSig5;
+  provides interface HplAtm128InterruptSig as IntSig6;
+  provides interface HplAtm128InterruptSig as IntSig7;
+}
+implementation
+{
+  default async event void IntSig0.fired() { }
+  AVR_ATOMIC_HANDLER( INT0_vect ) {
+    signal IntSig0.fired();
+  }
+
+  default async event void IntSig1.fired() { }
+  AVR_ATOMIC_HANDLER( INT1_vect ) {
+    signal IntSig1.fired();
+  }
+
+  default async event void IntSig2.fired() { }
+  AVR_ATOMIC_HANDLER( INT2_vect ) {
+    signal IntSig2.fired();
+  }
+
+  default async event void IntSig3.fired() { }
+  AVR_ATOMIC_HANDLER( INT3_vect ) {
+    signal IntSig3.fired();
+  }
+
+  default async event void IntSig4.fired() { }
+  AVR_ATOMIC_HANDLER( INT4_vect ) {
+    signal IntSig4.fired();
+  }
+
+  default async event void IntSig5.fired() { }
+  AVR_ATOMIC_HANDLER( INT5_vect ) {
+    signal IntSig5.fired();
+  }
+
+  default async event void IntSig6.fired() { }
+  AVR_ATOMIC_HANDLER( INT6_vect ) {
+    signal IntSig6.fired();
+  }
+
+  default async event void IntSig7.fired() { }
+  AVR_ATOMIC_HANDLER( INT7_vect ) {
+    signal IntSig7.fired();
+  }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt.h	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+#ifndef __HPLATMEGAEXTINTERRUPT_H__
+#define __HPLATMEGAEXTINTERRUPT_H__
+
+enum
+{
+	ATMEGA_EXTINT_LOW_LEVEL = 0,
+	ATMEGA_EXTINT_ANY_EDGE = 1,
+	ATMEGA_EXTINT_FALLING_EDGE = 2,
+	ATMEGA_EXTINT_RISING_EDGE = 3,
+};
+
+#endif//__HPLATMEGAEXTINTERRUPT_H__
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+interface HplAtmegaExtInterrupt
+{
+// ----- external interrupt flag register (EIFR)
+
+	/* Signalled when any of the enabled pins changed */
+	async event void fired();
+
+	/* Tests if an interrupt is pending */
+	async command bool test();
+
+	/* Resets a pending interrupt */
+	async command void reset();
+
+// ----- external interrupt mask register (EIMSK)
+
+	/* Enables the interrupt */
+	async command void enable();
+
+	/* Disables the interrupt */
+	async command void disable();
+
+	/* Checks if the interrupt is enabled */
+	async command bool isEnabled();
+
+// ----- external interrupt control register (EICR)
+
+	/* Selects the operation mode. Must be called in atomic context
+	   and the interrupt flag should be cleared afterwards*/
+	async command void setMode(uint8_t mode);
+
+	/* Returns the operation mode */
+	async command uint8_t getMode();
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt0C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+module HplAtmegaExtInterrupt0C
+{
+	provides interface HplAtmegaExtInterrupt;
+}
+
+#define INT_VECT	INT0_vect
+#define EIFR_REG	EIFR
+#define EIFR_PIN	INTF0
+#define EIMSK_REG	EIMSK
+#define EIMSK_PIN	INT0
+#define EICR_REG	EICRA
+#define EICR_PIN	ISC00
+
+implementation
+{
+// ----- external interrupt flag register (EIFR)
+
+	AVR_ATOMIC_HANDLER( INT_VECT )	{
+		signal HplAtmegaExtInterrupt.fired();
+	}
+
+	default async event void HplAtmegaExtInterrupt.fired() {}
+
+	async command bool HplAtmegaExtInterrupt.test() {
+		return (EIFR_REG & (1<<EIFR_PIN)) != 0;
+	}
+
+	async command void HplAtmegaExtInterrupt.reset() {
+		EIFR_REG = 1<<EIFR_PIN;
+	}
+
+// ----- external interrupt mask register (EIMSK)
+
+	async command void HplAtmegaExtInterrupt.enable() {
+		EIMSK_REG |= 1<<EIMSK_PIN;
+	}
+
+	async command void HplAtmegaExtInterrupt.disable() {
+		EIMSK_REG &= ~(1<<EIMSK_PIN);
+	}
+
+	async command bool HplAtmegaExtInterrupt.isEnabled() {
+		return (EIMSK_REG & (1<<EIMSK_PIN)) != 0;
+	}
+
+// ----- external interrupt control register (EICR)
+
+	inline async command void HplAtmegaExtInterrupt.setMode(uint8_t mode) {
+		uint8_t a = EICR_REG & ~(3 << EICR_PIN);
+		EICR_REG = a | ((mode & 3) << EICR_PIN);
+	}
+
+	async command uint8_t HplAtmegaExtInterrupt.getMode() {
+		return (EICR_REG >> EICR_PIN) & 3;
+	}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt1C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+module HplAtmegaExtInterrupt1C
+{
+	provides interface HplAtmegaExtInterrupt;
+}
+
+#define INT_VECT	INT1_vect
+#define EIFR_REG	EIFR
+#define EIFR_PIN	INTF1
+#define EIMSK_REG	EIMSK
+#define EIMSK_PIN	INT1
+#define EICR_REG	EICRA
+#define EICR_PIN	ISC10
+
+implementation
+{
+// ----- external interrupt flag register (EIFR)
+
+	AVR_ATOMIC_HANDLER( INT_VECT )	{
+		signal HplAtmegaExtInterrupt.fired();
+	}
+
+	default async event void HplAtmegaExtInterrupt.fired() {}
+
+	async command bool HplAtmegaExtInterrupt.test() {
+		return (EIFR_REG & (1<<EIFR_PIN)) != 0;
+	}
+
+	async command void HplAtmegaExtInterrupt.reset() {
+		EIFR_REG = 1<<EIFR_PIN;
+	}
+
+// ----- external interrupt mask register (EIMSK)
+
+	async command void HplAtmegaExtInterrupt.enable() {
+		EIMSK_REG |= 1<<EIMSK_PIN;
+	}
+
+	async command void HplAtmegaExtInterrupt.disable() {
+		EIMSK_REG &= ~(1<<EIMSK_PIN);
+	}
+
+	async command bool HplAtmegaExtInterrupt.isEnabled() {
+		return (EIMSK_REG & (1<<EIMSK_PIN)) != 0;
+	}
+
+// ----- external interrupt control register (EICR)
+
+	inline async command void HplAtmegaExtInterrupt.setMode(uint8_t mode) {
+		uint8_t a = EICR_REG & ~(3 << EICR_PIN);
+		EICR_REG = a | ((mode & 3) << EICR_PIN);
+	}
+
+	async command uint8_t HplAtmegaExtInterrupt.getMode() {
+		return (EICR_REG >> EICR_PIN) & 3;
+	}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt2C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+module HplAtmegaExtInterrupt2C
+{
+	provides interface HplAtmegaExtInterrupt;
+}
+
+#define INT_VECT	INT2_vect
+#define EIFR_REG	EIFR
+#define EIFR_PIN	INTF2
+#define EIMSK_REG	EIMSK
+#define EIMSK_PIN	INT2
+#define EICR_REG	EICRA
+#define EICR_PIN	ISC20
+
+implementation
+{
+// ----- external interrupt flag register (EIFR)
+
+	AVR_ATOMIC_HANDLER( INT_VECT )	{
+		signal HplAtmegaExtInterrupt.fired();
+	}
+
+	default async event void HplAtmegaExtInterrupt.fired() {}
+
+	async command bool HplAtmegaExtInterrupt.test() {
+		return (EIFR_REG & (1<<EIFR_PIN)) != 0;
+	}
+
+	async command void HplAtmegaExtInterrupt.reset() {
+		EIFR_REG = 1<<EIFR_PIN;
+	}
+
+// ----- external interrupt mask register (EIMSK)
+
+	async command void HplAtmegaExtInterrupt.enable() {
+		EIMSK_REG |= 1<<EIMSK_PIN;
+	}
+
+	async command void HplAtmegaExtInterrupt.disable() {
+		EIMSK_REG &= ~(1<<EIMSK_PIN);
+	}
+
+	async command bool HplAtmegaExtInterrupt.isEnabled() {
+		return (EIMSK_REG & (1<<EIMSK_PIN)) != 0;
+	}
+
+// ----- external interrupt control register (EICR)
+
+	inline async command void HplAtmegaExtInterrupt.setMode(uint8_t mode) {
+		uint8_t a = EICR_REG & ~(3 << EICR_PIN);
+		EICR_REG = a | ((mode & 3) << EICR_PIN);
+	}
+
+	async command uint8_t HplAtmegaExtInterrupt.getMode() {
+		return (EICR_REG >> EICR_PIN) & 3;
+	}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaExtInterrupt3C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+module HplAtmegaExtInterrupt3C
+{
+	provides interface HplAtmegaExtInterrupt;
+}
+
+#define INT_VECT	INT3_vect
+#define EIFR_REG	EIFR
+#define EIFR_PIN	INTF3
+#define EIMSK_REG	EIMSK
+#define EIMSK_PIN	INT3
+#define EICR_REG	EICRA
+#define EICR_PIN	ISC30
+
+implementation
+{
+// ----- external interrupt flag register (EIFR)
+
+	AVR_ATOMIC_HANDLER( INT_VECT )	{
+		signal HplAtmegaExtInterrupt.fired();
+	}
+
+	default async event void HplAtmegaExtInterrupt.fired() {}
+
+	async command bool HplAtmegaExtInterrupt.test() {
+		return (EIFR_REG & (1<<EIFR_PIN)) != 0;
+	}
+
+	async command void HplAtmegaExtInterrupt.reset() {
+		EIFR_REG = 1<<EIFR_PIN;
+	}
+
+// ----- external interrupt mask register (EIMSK)
+
+	async command void HplAtmegaExtInterrupt.enable() {
+		EIMSK_REG |= 1<<EIMSK_PIN;
+	}
+
+	async command void HplAtmegaExtInterrupt.disable() {
+		EIMSK_REG &= ~(1<<EIMSK_PIN);
+	}
+
+	async command bool HplAtmegaExtInterrupt.isEnabled() {
+		return (EIMSK_REG & (1<<EIMSK_PIN)) != 0;
+	}
+
+// ----- external interrupt control register (EICR)
+
+	inline async command void HplAtmegaExtInterrupt.setMode(uint8_t mode) {
+		uint8_t a = EICR_REG & ~(3 << EICR_PIN);
+		EICR_REG = a | ((mode & 3) << EICR_PIN);
+	}
+
+	async command uint8_t HplAtmegaExtInterrupt.getMode() {
+		return (EICR_REG >> EICR_PIN) & 3;
+	}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaPinChange.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2010, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ */
+
+interface HplAtmegaPinChange
+{
+// ----- pin change interrupt flag register (PCIFR)
+
+	/* Signalled when any of the enabled pins changed */
+	async event void fired();
+
+	/* Tests if an interrupt is pending */
+	async command bool test();
+
+	/* Resets a pending interrupt */
+	async command void reset();
+
+// ----- pin change control register (PCICR)
+
+	/* Enables the interrupt */
+	async command void enable();
+
+	/* Disables the interrupt */
+	async command void disable();
+
+	/* Checks if the interrupt is enabled */
+	async command bool isEnabled();
+
+// ----- pin change mask register (PCMSK)
+
+	/* Reads the mask register */
+	async command uint8_t getMask();
+
+	/* Sets the mask register */
+	async command void setMask(uint8_t value);
+
+// ----- pin register (PIN)
+
+	/* Reads the current pin values */
+	async command uint8_t getPins();
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaPinChange0C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Andras Biro
+ */
+
+/*
+ * Pin change interrupt HPL for atmega128rfa1 PCINT0:7 (PORTB0:7)
+ */
+module HplAtmegaPinChange0C
+{
+  provides interface HplAtmegaPinChange;
+}
+implementation
+{
+// ----- pin change interrupt flag register (PCIFR)
+
+  /* Tests if an interrupt is pending */
+  async command bool HplAtmegaPinChange.test(){
+    return (PCIFR&(1<<PCIF0))!=0;
+  }
+
+  /* Resets a pending interrupt */
+  async command void HplAtmegaPinChange.reset(){
+    PCIFR|=1<<PCIF0;
+  }
+
+// ----- pin change control register (PCICR)
+
+  /* Enables the interrupt */
+  async command void HplAtmegaPinChange.enable(){
+    PCICR|=1<<PCIE0;
+  }
+
+  /* Disables the interrupt */
+  async command void HplAtmegaPinChange.disable(){
+    PCICR&=~(1<<PCIE0);
+  }
+
+  /* Checks if the interrupt is enabled */
+  async command bool HplAtmegaPinChange.isEnabled(){
+    return (PCICR&(1<<PCIE0))!=0;
+  }
+
+// ----- pin change mask register (PCMSK)
+
+  /* Reads the mask register */
+  async command uint8_t HplAtmegaPinChange.getMask(){
+    return PCMSK0;
+  }
+
+  /* Sets the mask register */
+  async command void HplAtmegaPinChange.setMask(uint8_t value){
+    PCMSK0=value;
+  }
+
+// ----- pin register (PIN)
+
+  /* Reads the current pin values */
+  async command uint8_t HplAtmegaPinChange.getPins(){
+    return PINB;
+  }
+
+  /* Signalled when any of the enabled pins changed */
+  AVR_ATOMIC_HANDLER( PCINT0_vect ) {
+    signal HplAtmegaPinChange.fired();
+  }
+
+  default async event void HplAtmegaPinChange.fired(){}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/pins/HplAtmegaPinChange1C.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2011, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Andras Biro
+ */
+
+/*
+ * Pin change interrupt HPL for atmega128rfa1 PCINT8 (PORTE0)
+ */
+module HplAtmegaPinChange1C
+{
+  provides interface HplAtmegaPinChange;
+}
+implementation
+{
+// ----- pin change interrupt flag register (PCIFR)
+
+  /* Tests if an interrupt is pending */
+  async command bool HplAtmegaPinChange.test(){
+    return (PCIFR&(1<<PCIF1))!=0;
+  }
+
+  /* Resets a pending interrupt */
+  async command void HplAtmegaPinChange.reset(){
+    PCIFR|=1<<PCIF1;
+  }
+
+// ----- pin change control register (PCICR)
+
+  /* Enables the interrupt */
+  async command void HplAtmegaPinChange.enable(){
+    PCICR|=1<<PCIE1;
+  }
+
+  /* Disables the interrupt */
+  async command void HplAtmegaPinChange.disable(){
+    PCICR&=~(1<<PCIE1);
+  }
+
+  /* Checks if the interrupt is enabled */
+  async command bool HplAtmegaPinChange.isEnabled(){
+    return (PCICR&(1<<PCIE1))!=0;
+  }
+
+// ----- pin change mask register (PCMSK)
+
+  /* Reads the mask register */
+  async command uint8_t HplAtmegaPinChange.getMask(){
+    return PCMSK1;
+  }
+
+  /* Sets the mask register */
+  async command void HplAtmegaPinChange.setMask(uint8_t value){
+    PCMSK1=value;
+  }
+
+// ----- pin register (PIN)
+
+  /* Reads the current pin values */
+  async command uint8_t HplAtmegaPinChange.getPins(){
+    return PINE&0x01;
+  }
+
+  /* Signalled when any of the enabled pins changed */
+  AVR_ATOMIC_HANDLER( PCINT1_vect ) {
+    signal HplAtmegaPinChange.fired();
+  }
+
+  default async event void HplAtmegaPinChange.fired(){}
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1ActiveMessageC.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+#include <RadioConfig.h>
+
+#ifdef IEEE154FRAMES_ENABLED
+#error "You cannot use ActiveMessageC with IEEE154FRAMES_ENABLED defined"
+#endif
+
+configuration RFA1ActiveMessageC
+{
+	provides
+	{
+		interface SplitControl;
+
+		interface AMSend[am_id_t id];
+		interface Receive[am_id_t id];
+		interface Receive as Snoop[am_id_t id];
+		interface SendNotifier[am_id_t id];
+
+		// for TOSThreads
+		interface Receive as ReceiveDefault[am_id_t id];
+		interface Receive as SnoopDefault[am_id_t id];
+
+		interface Packet;
+		interface AMPacket;
+
+		interface PacketAcknowledgements;
+		interface LowPowerListening;
+#ifdef PACKET_LINK
+		interface PacketLink;
+#endif
+
+		interface RadioChannel;
+
+		interface PacketField<uint8_t> as PacketLinkQuality;
+		interface PacketField<uint8_t> as PacketTransmitPower;
+		interface PacketField<uint8_t> as PacketRSSI;
+		interface LinkPacketMetadata;
+
+		interface LocalTime<TRadio> as LocalTimeRadio;
+		interface PacketTimeStamp<TRadio, uint32_t> as PacketTimeStampRadio;
+		interface PacketTimeStamp<TMilli, uint32_t> as PacketTimeStampMilli;
+	}
+}
+
+implementation
+{
+	components RFA1RadioC as RadioC;
+
+	SplitControl = RadioC;
+
+	AMSend = RadioC;
+	Receive = RadioC.Receive;
+	Snoop = RadioC.Snoop;
+	SendNotifier = RadioC;
+
+	ReceiveDefault = RadioC.ReceiveDefault;
+	SnoopDefault = RadioC.SnoopDefault;
+
+	Packet = RadioC.PacketForActiveMessage;
+	AMPacket = RadioC;
+
+	PacketAcknowledgements = RadioC;
+	LowPowerListening = RadioC;
+#ifdef PACKET_LINK
+	PacketLink = RadioC;
+#endif
+
+	RadioChannel = RadioC;
+
+	PacketLinkQuality = RadioC.PacketLinkQuality;
+	PacketTransmitPower = RadioC.PacketTransmitPower;
+	PacketRSSI = RadioC.PacketRSSI;
+	LinkPacketMetadata = RadioC;
+
+	LocalTimeRadio = RadioC;
+	PacketTimeStampMilli = RadioC;
+	PacketTimeStampRadio = RadioC;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1DriverConfig.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+interface RFA1DriverConfig
+{
+	/**
+	 * Returns the length of a dummy header to align the payload properly.
+	 */
+	async command uint8_t headerLength(message_t* msg);
+
+	/**
+	 * Returns the maximum length of the PHY payload including the
+	 * length field but not counting the FCF field.
+	 */
+	async command uint8_t maxPayloadLength();
+
+	/**
+	 * Returns the length of a dummy metadata section to align the
+	 * metadata section properly.
+	 */
+	async command uint8_t metadataLength(message_t* msg);
+
+	/**
+	 * Returns TRUE if before sending this message we should make sure that
+	 * the channel is clear via a very basic (and quick) RSSI check.
+	 */
+	async command bool requiresRssiCca(message_t* msg);
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1DriverLayer.h	Sun Sep  4 02:04:37  
2011
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+#ifndef __RFA1DRIVERLAYER_H__
+#define __RFA1DRIVERLAYER_H__
+
+typedef nx_struct rfa1_header_t
+{
+	nxle_uint8_t length;
+} rfa1_header_t;
+
+typedef struct rfa1_metadata_t
+{
+	uint8_t lqi;
+	union
+	{
+		uint8_t power;
+		uint8_t rssi;
+	};
+} rfa1_metadata_t;
+
+
+
+#endif//__RFA1DRIVERLAYER_H__
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1DriverLayerC.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+#include <RadioConfig.h>
+#include <RFA1DriverLayer.h>
+
+configuration RFA1DriverLayerC
+{
+	provides
+	{
+		interface RadioState;
+		interface RadioSend;
+		interface RadioReceive;
+		interface RadioCCA;
+		interface RadioPacket;
+
+		interface PacketField<uint8_t> as PacketTransmitPower;
+		interface PacketField<uint8_t> as PacketRSSI;
+		interface PacketField<uint8_t> as PacketTimeSyncOffset;
+		interface PacketField<uint8_t> as PacketLinkQuality;
+		interface LinkPacketMetadata;
+
+		interface LocalTime<TRadio> as LocalTimeRadio;
+		interface Alarm<TRadio, tradio_size>;
+	}
+
+	uses
+	{
+		interface RFA1DriverConfig as Config;
+		interface PacketTimeStamp<TRadio, uint32_t>;
+
+		interface PacketFlag as TransmitPowerFlag;
+		interface PacketFlag as RSSIFlag;
+		interface PacketFlag as TimeSyncFlag;
+	}
+}
+
+implementation
+{
+	components RFA1DriverLayerP, BusyWaitMicroC, TaskletC,
+		LocalTime62khzC, new Alarm62khz32C(), HplAtmRfa1TimerMacC;
+
+	RadioState = RFA1DriverLayerP;
+	RadioSend = RFA1DriverLayerP;
+	RadioReceive = RFA1DriverLayerP;
+	RadioCCA = RFA1DriverLayerP;
+	RadioPacket = RFA1DriverLayerP;
+
+	LocalTimeRadio = LocalTime62khzC;
+
+	Config = RFA1DriverLayerP;
+
+	PacketTransmitPower = RFA1DriverLayerP.PacketTransmitPower;
+	TransmitPowerFlag = RFA1DriverLayerP.TransmitPowerFlag;
+
+	PacketRSSI = RFA1DriverLayerP.PacketRSSI;
+	RSSIFlag = RFA1DriverLayerP.RSSIFlag;
+
+	PacketTimeSyncOffset = RFA1DriverLayerP.PacketTimeSyncOffset;
+	TimeSyncFlag = RFA1DriverLayerP.TimeSyncFlag;
+
+	PacketLinkQuality = RFA1DriverLayerP.PacketLinkQuality;
+	PacketTimeStamp = RFA1DriverLayerP.PacketTimeStamp;
+	LinkPacketMetadata = RFA1DriverLayerP;
+
+	RFA1DriverLayerP.LocalTime -> LocalTime62khzC;
+	RFA1DriverLayerP.SfdCapture -> HplAtmRfa1TimerMacC.SfdCapture;
+
+	Alarm = Alarm62khz32C;
+
+	RFA1DriverLayerP.Tasklet -> TaskletC;
+	RFA1DriverLayerP.BusyWait -> BusyWaitMicroC;
+
+#ifdef RADIO_DEBUG
+	components DiagMsgC;
+	RFA1DriverLayerP.DiagMsg -> DiagMsgC;
+#endif
+
+	components MainC, RealMainP;
+	RealMainP.PlatformInit -> RFA1DriverLayerP.PlatformInit;
+	MainC.SoftwareInit -> RFA1DriverLayerP.SoftwareInit;
+
+	components McuSleepC;
+	RFA1DriverLayerP.McuPowerState -> McuSleepC;
+	RFA1DriverLayerP.McuPowerOverride <- McuSleepC;
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1DriverLayerP.nc	Sun Sep  4  
02:04:37 2011
@@ -0,0 +1,892 @@
+/*
+* Copyright (c) 2007, Vanderbilt University
+* Copyright (c) 2010, University of Szeged
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* - Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* - Redistributions in binary form must reproduce the above
+* copyright notice, this list of conditions and the following
+* disclaimer in the documentation and/or other materials provided
+* with the distribution.
+* - Neither the name of University of Szeged nor the names of its
+* contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+* OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+* Author: Miklos Maroti
+* Author:Andras Biro
+*/
+
+#include <RFA1DriverLayer.h>
+#include <Tasklet.h>
+#include <RadioAssert.h>
+#include <TimeSyncMessageLayer.h>
+#include <RadioConfig.h>
+
+module RFA1DriverLayerP
+{
+  provides
+  {
+    interface Init as PlatformInit @exactlyonce();
+    interface Init as SoftwareInit @exactlyonce();
+
+    interface RadioState;
+    interface RadioSend;
+    interface RadioReceive;
+    interface RadioCCA;
+    interface RadioPacket;
+
+    interface PacketField<uint8_t> as PacketTransmitPower;
+    interface PacketField<uint8_t> as PacketRSSI;
+    interface PacketField<uint8_t> as PacketTimeSyncOffset;
+    interface PacketField<uint8_t> as PacketLinkQuality;
+    interface LinkPacketMetadata;
+
+    interface McuPowerOverride;
+  }
+
+  uses
+  {
+    interface BusyWait<TMicro, uint16_t>;
+    interface LocalTime<TRadio>;
+    interface AtmegaCapture<uint32_t> as SfdCapture;
+
+    interface RFA1DriverConfig as Config;
+
+    interface PacketFlag as TransmitPowerFlag;
+    interface PacketFlag as RSSIFlag;
+    interface PacketFlag as TimeSyncFlag;
+
+    interface PacketTimeStamp<TRadio, uint32_t>;
+
+    interface Tasklet;
+    interface McuPowerState;
+
+#ifdef RADIO_DEBUG
+    interface DiagMsg;
+#endif
+  }
+}
+
+implementation
+{
+  rfa1_header_t* getHeader(message_t* msg)
+  {
+    return ((void*)msg) + call Config.headerLength(msg);
+  }
+
+  void* getPayload(message_t* msg)
+  {
+    return ((void*)msg) + call RadioPacket.headerLength(msg);
+  }
+
+  rfa1_metadata_t* getMeta(message_t* msg)
+  {
+    return ((void*)msg) + sizeof(message_t) - call  
RadioPacket.metadataLength(msg);
+  }
+
+  /*----------------- STATE -----------------*/
+
+  tasklet_norace uint8_t state;
+  enum
+  {
+    STATE_P_ON = 0,
+    STATE_SLEEP = 1,
+    STATE_SLEEP_2_TRX_OFF = 2,
+    STATE_TRX_OFF = 3,
+    STATE_TRX_OFF_2_RX_ON = 4,
+    STATE_RX_ON = 5,
+    STATE_BUSY_TX_2_RX_ON = 6,
+    STATE_PLL_ON_2_RX_ON = 7,
+  };
+
+  tasklet_norace uint8_t cmd;
+  enum
+  {
+    CMD_NONE = 0,    // the state machine has stopped
+    CMD_TURNOFF = 1,    // goto SLEEP state
+    CMD_STANDBY = 2,    // goto TRX_OFF state
+    CMD_TURNON = 3,    // goto RX_ON state
+    CMD_TRANSMIT = 4,    // currently transmitting a message
+    CMD_RECEIVE = 5,    // currently receiving a message
+    CMD_CCA = 6,    // performing clear channel assessment
+    CMD_CHANNEL = 7,    // changing the channel
+    CMD_SIGNAL_DONE = 8,  // signal the end of the state transition
+    CMD_DOWNLOAD = 9,    // download the received message
+  };
+
+  enum {
+    IRQ_NONE=0,
+    IRQ_AWAKE=1,
+    IRQ_TX_END=2,
+    IRQ_XAH_AMI=4,
+    IRQ_CCA_ED_DONE=8,
+    IRQ_RX_END=16,
+    IRQ_RX_START=32,
+    IRQ_PLL_UNLOCK=64,
+    IRQ_PLL_LOCK=128,
+  };
+
+  enum {
+    // this disables the RFA1RadioOffP component
+    RFA1RADIOON = unique("RFA1RadioOn"),
+  };
+
+  norace uint8_t radioIrq;
+
+  tasklet_norace uint8_t txPower;
+  tasklet_norace uint8_t channel;
+
+  tasklet_norace message_t* rxMsg;
+  message_t rxMsgBuffer;
+
+  tasklet_norace uint8_t rssiClear;
+  tasklet_norace uint8_t rssiBusy;
+
+  /*----------------- INIT -----------------*/
+
+  command error_t PlatformInit.init()
+  {
+    rxMsg = &rxMsgBuffer;
+
+    // these are just good approximates
+    rssiClear = 0;
+    rssiBusy = 90;
+
+    return SUCCESS;
+  }
+
+  command error_t SoftwareInit.init()
+  {
+    CCA_THRES=RFA1_CCA_THRES_VALUE;
+
+    //TODO PA_EXT settings with defines
+    PHY_TX_PWR=RFA1_PA_BUF_LT | RFA1_PA_LT |  
(RFA1_DEF_RFPOWER&RFA1_TX_PWR_MASK)<<TX_PWR0;
+
+    txPower = RFA1_DEF_RFPOWER & RFA1_TX_PWR_MASK;
+    channel = RFA1_DEF_CHANNEL & RFA1_CHANNEL_MASK;
+    TRX_CTRL_1 |= 1<<TX_AUTO_CRC_ON;
+    PHY_CC_CCA=RFA1_CCA_MODE_VALUE|channel;
+
+    SET_BIT(TRXPR,SLPTR);
+
+    call SfdCapture.setMode(ATMRFA1_CAPSC_ON);
+
+    state = STATE_SLEEP;
+
+    return SUCCESS;
+  }
+
+  /*----------------- CHANNEL -----------------*/
+
+  tasklet_async command uint8_t RadioState.getChannel()
+  {
+    return channel;
+  }
+
+  tasklet_async command error_t RadioState.setChannel(uint8_t c)
+  {
+    c &= RFA1_CHANNEL_MASK;
+
+    if( cmd != CMD_NONE )
+      return EBUSY;
+    else if( channel == c )
+      return EALREADY;
+
+    channel = c;
+    cmd = CMD_CHANNEL;
+    call Tasklet.schedule();
+
+    return SUCCESS;
+  }
+
+  inline void changeChannel()
+  {
+    RADIO_ASSERT( cmd == CMD_CHANNEL );
+    RADIO_ASSERT( state == STATE_SLEEP || state == STATE_TRX_OFF || state  
== STATE_RX_ON );
+
+
+    PHY_CC_CCA=RFA1_CCA_MODE_VALUE|channel;
+
+    if( state == STATE_RX_ON )
+      state = STATE_TRX_OFF_2_RX_ON;
+    else
+      cmd = CMD_SIGNAL_DONE;
+  }
+
+  /*----------------- TURN ON/OFF -----------------*/
+
+  inline void changeState()
+  {
+    if( (cmd == CMD_STANDBY || cmd == CMD_TURNON) && state == STATE_SLEEP )
+    {
+      RADIO_ASSERT( ! radioIrq );
+
+      IRQ_STATUS = 0xFF;
+      IRQ_MASK = 1<<AWAKE_EN;
+      CLR_BIT(TRXPR,SLPTR);
+      call McuPowerState.update();
+
+      state = STATE_SLEEP_2_TRX_OFF;
+    }
+    else if( cmd == CMD_TURNON && state == STATE_TRX_OFF )
+    {
+      RADIO_ASSERT( ! radioIrq );
+
+      IRQ_MASK = 1<<PLL_LOCK_EN | 1<<TX_END_EN | 1<<RX_END_EN | 1<<  
RX_START_EN | 1<<CCA_ED_DONE_EN;
+      call McuPowerState.update();
+
+      // setChannel was ignored in SLEEP because the SPI was not working,  
so do it here
+      PHY_CC_CCA = RFA1_CCA_MODE_VALUE | channel;
+
+      TRX_STATE = CMD_RX_ON;
+      state = STATE_TRX_OFF_2_RX_ON;
+    }
+    else if( (cmd == CMD_TURNOFF || cmd == CMD_STANDBY) && state ==  
STATE_RX_ON )
+    {
+      TRX_STATE = CMD_FORCE_TRX_OFF;
+
+      IRQ_MASK = 0;
+      call McuPowerState.update();
+
+      state = STATE_TRX_OFF;
+    }
+
+    if( cmd == CMD_TURNOFF && state == STATE_TRX_OFF )
+    {
+      SET_BIT(TRXPR,SLPTR);
+      state = STATE_SLEEP;
+      cmd = CMD_SIGNAL_DONE;
+    }
+    else if( cmd == CMD_STANDBY && state == STATE_TRX_OFF )
+    {
+      IRQ_MASK = 0;
+      call McuPowerState.update();
+
+      cmd = CMD_SIGNAL_DONE;
+    }
+  }
+
+  tasklet_async command error_t RadioState.turnOff()
+  {
+    if( cmd != CMD_NONE )
+      return EBUSY;
+    else if( state == STATE_SLEEP )
+      return EALREADY;
+
+    cmd = CMD_TURNOFF;
+    call Tasklet.schedule();
+
+    return SUCCESS;
+  }
+
+  tasklet_async command error_t RadioState.standby()
+  {
+    if( cmd != CMD_NONE  )
+      return EBUSY;
+    else if( state == STATE_TRX_OFF )
+      return EALREADY;
+
+    cmd = CMD_STANDBY;
+    call Tasklet.schedule();
+
+    return SUCCESS;
+  }
+
+  tasklet_async command error_t RadioState.turnOn()
+  {
+    if( cmd != CMD_NONE )
+      return EBUSY;
+    else if( state == STATE_RX_ON )
+      return EALREADY;
+    cmd = CMD_TURNON;
+    call Tasklet.schedule();
+
+    return SUCCESS;
+  }
+
+  default tasklet_async event void RadioState.done() { }
+
+  /*----------------- TRANSMIT -----------------*/
+
+  enum {
+    // 16 us delay (1 tick), 4 bytes preamble (2 ticks each), 1 byte SFD  
(2 ticks)
+    TX_SFD_DELAY = 11,
+  };
+
+  tasklet_async command error_t RadioSend.send(message_t* msg)
+  {
+    uint32_t time;
+    uint8_t length;
+    uint8_t* data;
+    void* timesync;
+
+    if( cmd != CMD_NONE || state != STATE_RX_ON || radioIrq )
+      return EBUSY;
+
+    length = (call PacketTransmitPower.isSet(msg) ?
+        call PacketTransmitPower.get(msg) : RFA1_DEF_RFPOWER) &  
RFA1_TX_PWR_MASK;
+
+    if( length != txPower )
+    {
+      txPower = length;
+      PHY_TX_PWR=RFA1_PA_BUF_LT | RFA1_PA_LT | txPower<<TX_PWR0;
+    }
+
+    if( call Config.requiresRssiCca(msg)
+          && (PHY_RSSI & RFA1_RSSI_MASK) > ((rssiClear + rssiBusy) >> 3) )
+      return EBUSY;
+
+    TRX_STATE = CMD_PLL_ON;
+
+    // do something useful, just to wait a little
+    timesync = call PacketTimeSyncOffset.isSet(msg) ? ((void*)msg) + call  
PacketTimeSyncOffset.get(msg) : 0;
+
+    data = getPayload(msg);
+    length = getHeader(msg)->length;
+
+    // length | data[0] ... data[length-3] | automatically generated FCS
+    TRXFBST = length;
+
+    // the FCS is atomatically generated (2 bytes) (TX_AUTO_CRC_ON==1 by  
default)
+    length -= 2;
+
+    // we have missed an incoming message in this short amount of time
+    if( (TRX_STATUS & RFA1_TRX_STATUS_MASK) != PLL_ON )
+    {
+      RADIO_ASSERT( (TRX_STATUS & RFA1_TRX_STATUS_MASK) == BUSY_RX );
+
+      state = STATE_PLL_ON_2_RX_ON;
+      return EBUSY;
+    }
+
+    atomic
+    {
+        time = call LocalTime.get();
+        TRX_STATE = CMD_TX_START;
+    }
+
+    time += TX_SFD_DELAY;
+
+    RADIO_ASSERT( ! radioIrq );
+
+    // fix the time stamp
+    if( timesync != 0 )
+      *(timesync_relative_t*)timesync = (*(timesync_absolute_t*)timesync)  
- time;
+
+    // then upload the whole payload
+    memcpy((void*)(&TRXFBST+1), data, length);
+
+    // go back to RX_ON state when finished
+    TRX_STATE=CMD_RX_ON;
+
+    if( timesync != 0 )
+      *(timesync_absolute_t*)timesync = (*(timesync_relative_t*)timesync)  
+ time;
+
+    call PacketTimeStamp.set(msg, time);
+
+#ifdef RADIO_DEBUG_MESSAGES
+    if( call DiagMsg.record() )
+    {
+      length = getHeader(msg)->length;
+
+      call DiagMsg.chr('t');
+      call DiagMsg.uint32(call PacketTimeStamp.isValid(rxMsg) ? call  
PacketTimeStamp.timestamp(rxMsg) : 0);
+      call DiagMsg.uint16(call LocalTime.get());
+      call DiagMsg.int8(length);
+      call DiagMsg.hex8s(getPayload(msg), length - 2);
+      call DiagMsg.send();
+    }
+#endif
+
+    // wait for the TRX_END interrupt
+    state = STATE_BUSY_TX_2_RX_ON;
+    cmd = CMD_TRANSMIT;
+
+    return SUCCESS;
+  }
+
+  default tasklet_async event void RadioSend.sendDone(error_t error) { }
+  default tasklet_async event void RadioSend.ready() { }
+
+  /*----------------- CCA -----------------*/
+
+  tasklet_async command error_t RadioCCA.request()
+  {
+    if( cmd != CMD_NONE || state != STATE_RX_ON )
+      return EBUSY;
+
+    // see Errata 38.5.5 datasheet
+    TRX_STATE=CMD_PLL_ON;
+    //TODO: test&optimize this
+    call BusyWait.wait(1);
+    if( (TRX_STATUS & RFA1_TRX_STATUS_MASK) != PLL_ON )
+        return EBUSY;
+    SET_BIT(RX_SYN,RX_PDT_DIS);
+    TRX_STATE=CMD_RX_ON;
+    //end of workaround
+
+    cmd = CMD_CCA;
+    PHY_CC_CCA = 1 << CCA_REQUEST | RFA1_CCA_MODE_VALUE | channel;
+
+    return SUCCESS;
+  }
+
+  default tasklet_async event void RadioCCA.done(error_t error) { }
+
+  /*----------------- RECEIVE -----------------*/
+
+  //TODO: RX_SAFE_MODE with define
+  inline void downloadMessage()
+  {
+    uint8_t length;
+    bool sendSignal = FALSE;
+
+    length = TST_RX_LENGTH;
+
+    if( (PHY_RSSI & (1<<RX_CRC_VALID)) && length >= 3 && length <= call  
RadioPacket.maxPayloadLength() + 2 )
+    {
+      uint8_t* data;
+
+      data = getPayload(rxMsg);
+      getHeader(rxMsg)->length = length;
+
+      // we do not store the CRC field
+      length -= 2;
+
+      // memory is fast, no point optimizing header check
+      memcpy(data,(void*)&TRXFBST,length);
+
+      if( signal RadioReceive.header(rxMsg) )
+      {
+        call PacketLinkQuality.set(rxMsg,  
(uint8_t)*(&TRXFBST+TST_RX_LENGTH));
+        sendSignal = TRUE;
+      }
+    }
+
+    state = STATE_RX_ON;
+
+#ifdef RADIO_DEBUG_MESSAGES
+    if( call DiagMsg.record() )
+    {
+      length = getHeader(rxMsg)->length;
+
+      call DiagMsg.chr('r');
+      call DiagMsg.uint32(call PacketTimeStamp.isValid(rxMsg) ? call  
PacketTimeStamp.timestamp(rxMsg) : 0);
+      call DiagMsg.uint16(call LocalTime.get());
+      call DiagMsg.int8(sendSignal ? length : -length);
+      call DiagMsg.hex8s(getPayload(rxMsg), length - 2);
+      call DiagMsg.int8(call PacketRSSI.isSet(rxMsg) ? call  
PacketRSSI.get(rxMsg) : -1);
+      call DiagMsg.uint8(call PacketLinkQuality.isSet(rxMsg) ? call  
PacketLinkQuality.get(rxMsg) : 0);
+      call DiagMsg.send();
+    }
+#endif
+
+    cmd = CMD_NONE;
+
+    // signal only if it has passed the CRC check
+    if( sendSignal )
+      rxMsg = signal RadioReceive.receive(rxMsg);
+  }
+
+  default tasklet_async event bool RadioReceive.header(message_t* msg)
+  {
+    return TRUE;
+  }
+
+  default tasklet_async event message_t* RadioReceive.receive(message_t*  
msg)
+  {
+    return msg;
+  }
+
+  /*----------------- IRQ -----------------*/
+
+  void serviceRadio()
+  {
+    uint32_t time;
+    uint8_t irq;
+    uint8_t temp;
+
+    atomic
+    {
+      time = call SfdCapture.get();
+      irq = radioIrq;
+      radioIrq = IRQ_NONE;
+    }
+
+    if( irq & IRQ_PLL_LOCK )
+    {
+      if( cmd == CMD_TURNON || cmd == CMD_CHANNEL )
+      {
+        RADIO_ASSERT( state == STATE_TRX_OFF_2_RX_ON );
+
+        state = STATE_RX_ON;
+        cmd = CMD_SIGNAL_DONE;
+      }
+      else if( cmd == CMD_TRANSMIT )
+        RADIO_ASSERT( state == STATE_BUSY_TX_2_RX_ON );
+      else
+        RADIO_ASSERT(FALSE);
+    }
+
+    if( irq & IRQ_RX_START )
+    {
+      if( cmd == CMD_CCA )
+      {
+        signal RadioCCA.done(FAIL);
+        cmd = CMD_NONE;
+      }
+
+      if( cmd == CMD_NONE )
+      {
+        RADIO_ASSERT( state == STATE_RX_ON || state ==  
STATE_PLL_ON_2_RX_ON );
+
+        // the most likely place for busy channel, with no TRX_END  
interrupt
+        if( irq == IRQ_RX_START )
+        {
+          temp = PHY_RSSI & RFA1_RSSI_MASK;
+          rssiBusy += temp - (rssiBusy >> 2);
+#ifndef RFA1_RSSI_ENERGY
+          call PacketRSSI.set(rxMsg, temp);
+        }
+        else
+        {
+          call PacketRSSI.clear(rxMsg);
+#endif
+        }
+
+        if( irq == IRQ_RX_START ) // just to be cautious
+          call PacketTimeStamp.set(rxMsg, time);
+        else
+          call PacketTimeStamp.clear(rxMsg);
+
+        cmd = CMD_RECEIVE;
+      }
+      else
+        RADIO_ASSERT( cmd == CMD_TURNOFF );
+    }
+
+    if( irq & IRQ_TX_END )
+    {
+      RADIO_ASSERT( state == STATE_BUSY_TX_2_RX_ON );
+
+      state = STATE_RX_ON;
+      cmd = CMD_NONE;
+      signal RadioSend.sendDone(SUCCESS);
+
+      // TODO: we could have missed a received message
+      RADIO_ASSERT( ! (irq & IRQ_RX_START) );
+    }
+
+    if( irq & IRQ_RX_END )
+    {
+#ifdef RFA1_RSSI_ENERGY
+      if( irq == IRQ_RX_END && cmd == CMD_NONE )
+              call PacketRSSI.set(rxMsg, PHY_ED_LEVEL);
+            else
+              call PacketRSSI.clear(rxMsg);
+#endif
+
+      RADIO_ASSERT( state == STATE_RX_ON || state == STATE_PLL_ON_2_RX_ON  
);
+
+      if( state == STATE_PLL_ON_2_RX_ON )
+      {
+        RADIO_ASSERT( (TRX_STATUS & RFA1_TRX_STATUS_MASK) == PLL_ON );
+
+        TRX_STATE = CMD_RX_ON;
+        state = STATE_RX_ON;
+      }
+      else
+      {
+        // the most likely place for clear channel (hope to avoid acks)
+        rssiClear += (PHY_RSSI & RFA1_RSSI_MASK) - (rssiClear >> 2);
+      }
+
+      cmd = CMD_DOWNLOAD;
+    }
+
+    if( irq & IRQ_AWAKE ){
+      if( state == STATE_SLEEP_2_TRX_OFF && (cmd==CMD_STANDBY ||  
cmd==CMD_TURNON) )
+        state = STATE_TRX_OFF;
+      else
+        RADIO_ASSERT(FALSE);
+    }
+
+    if ( irq & IRQ_CCA_ED_DONE ){
+      if( cmd == CMD_CCA )
+      {
+        // workaround, see Errata 38.5.5 datasheet
+        CLR_BIT(RX_SYN,RX_PDT_DIS);
+
+
+        cmd = CMD_NONE;
+
+        RADIO_ASSERT( state == STATE_RX_ON );
+        RADIO_ASSERT( (TRX_STATUS & RFA1_TRX_STATUS_MASK) == RX_ON );
+
+        signal RadioCCA.done( (TRX_STATUS & CCA_DONE) ? ((TRX_STATUS &  
CCA_STATUS) ? SUCCESS : EBUSY) : FAIL );
+      } else
+        RADIO_ASSERT(FALSE);
+    }
+
+  }
+
+  /**
+   * Indicates the completion of a frame transmission
+   */
+  AVR_NONATOMIC_HANDLER(TRX24_TX_END_vect){
+    RADIO_ASSERT( ! radioIrq );
+
+    atomic radioIrq |= IRQ_TX_END;
+    call Tasklet.schedule();
+  }
+
+  /**
+   * Indicates the completion of a frame reception
+   */
+  AVR_NONATOMIC_HANDLER(TRX24_RX_END_vect){
+    RADIO_ASSERT( ! radioIrq );
+
+    atomic radioIrq |= IRQ_RX_END;
+    call Tasklet.schedule();
+  }
+
+  /**
+   * Indicates the start of a PSDU reception. The TRX_STATE changes
+   * to BUSY_RX, the PHR is ready to be read from Frame Buffer
+   */
+  AVR_NONATOMIC_HANDLER(TRX24_RX_START_vect){
+    RADIO_ASSERT( ! radioIrq );
+
+    atomic radioIrq |= IRQ_RX_START;
+    call Tasklet.schedule();
+  }
+
+  /**
+   * Indicates PLL lock
+   */
+  AVR_NONATOMIC_HANDLER(TRX24_PLL_LOCK_vect){
+    RADIO_ASSERT( ! radioIrq );
+
+    atomic radioIrq |= IRQ_PLL_LOCK;
+    call Tasklet.schedule();
+  }
+
+  /**
+   * indicates sleep/reset->trx_off mode change
+   */
+  AVR_NONATOMIC_HANDLER(TRX24_AWAKE_vect){
+    RADIO_ASSERT( ! radioIrq );
+
+    atomic radioIrq |= IRQ_AWAKE;
+    call Tasklet.schedule();
+  }
+
+  /**
+   * indicates CCA ED done
+   */
+  AVR_NONATOMIC_HANDLER(TRX24_CCA_ED_DONE_vect){
+    RADIO_ASSERT( ! radioIrq );
+
+    atomic radioIrq |= IRQ_CCA_ED_DONE;
+    call Tasklet.schedule();
+  }
+
+  // never called, we have the RX_START interrupt instead
+  async event void SfdCapture.fired() { }
+
+  /*----------------- TASKLET -----------------*/
+
+  tasklet_async event void Tasklet.run()
+  {
+    if( radioIrq != IRQ_NONE )
+      serviceRadio();
+
+    if( cmd != CMD_NONE )
+    {
+      if( cmd == CMD_DOWNLOAD )
+        downloadMessage();
+      else if( CMD_TURNOFF <= cmd && cmd <= CMD_TURNON )
+        changeState();
+      else if( cmd == CMD_CHANNEL )
+        changeChannel();
+
+      if( cmd == CMD_SIGNAL_DONE )
+      {
+        cmd = CMD_NONE;
+        signal RadioState.done();
+      }
+    }
+
+    if( cmd == CMD_NONE && state == STATE_RX_ON && ! radioIrq )
+      signal RadioSend.ready();
+
+  }
+
+  /*----------------- McuPower -----------------*/
+
+   async command mcu_power_t McuPowerOverride.lowestState()
+   {
+      if( (IRQ_MASK & 1<<AWAKE_EN) != 0 )
+         return ATM128_POWER_EXT_STANDBY;
+      else
+         return ATM128_POWER_DOWN;
+   }
+
+  /*----------------- RadioPacket -----------------*/
+
+  async command uint8_t RadioPacket.headerLength(message_t* msg)
+  {
+
+    return call Config.headerLength(msg) + sizeof(rfa1_header_t);
+  }
+
+  async command uint8_t RadioPacket.payloadLength(message_t* msg)
+  {
+    return getHeader(msg)->length - 2;
+  }
+
+  async command void RadioPacket.setPayloadLength(message_t* msg, uint8_t  
length)
+  {
+    RADIO_ASSERT( 1 <= length && length <= 125 );
+    RADIO_ASSERT( call RadioPacket.headerLength(msg) + length + call  
RadioPacket.metadataLength(msg) <= sizeof(message_t) );
+    // we add the length of the CRC, which is automatically generated
+    getHeader(msg)->length = length + 2;
+  }
+
+  async command uint8_t RadioPacket.maxPayloadLength()
+  {
+    RADIO_ASSERT( call Config.maxPayloadLength() - sizeof(rfa1_header_t)  
<= 125 );
+
+    return call Config.maxPayloadLength() - sizeof(rfa1_header_t);
+  }
+
+  async command uint8_t RadioPacket.metadataLength(message_t* msg)
+  {
+    return call Config.metadataLength(msg) + sizeof(rfa1_metadata_t);
+  }
+
+  async command void RadioPacket.clear(message_t* msg)
+  {
+    // all flags are automatically cleared
+  }
+
+  /*----------------- PacketTransmitPower -----------------*/
+
+  async command bool PacketTransmitPower.isSet(message_t* msg)
+  {
+    return call TransmitPowerFlag.get(msg);
+  }
+
+  async command uint8_t PacketTransmitPower.get(message_t* msg)
+  {
+    return getMeta(msg)->power;
+  }
+
+  async command void PacketTransmitPower.clear(message_t* msg)
+  {
+    call TransmitPowerFlag.clear(msg);
+  }
+
+  async command void PacketTransmitPower.set(message_t* msg, uint8_t value)
+  {
+    call TransmitPowerFlag.set(msg);
+    getMeta(msg)->power = value;
+  }
+
+  /*----------------- PacketRSSI -----------------*/
+
+  async command bool PacketRSSI.isSet(message_t* msg)
+  {
+    return call RSSIFlag.get(msg);
+  }
+
+  async command uint8_t PacketRSSI.get(message_t* msg)
+  {
+    return getMeta(msg)->rssi;
+  }
+
+  async command void PacketRSSI.clear(message_t* msg)
+  {
+    call RSSIFlag.clear(msg);
+  }
+
+  async command void PacketRSSI.set(message_t* msg, uint8_t value)
+  {
+    // just to be safe if the user fails to clear the packet
+    call TransmitPowerFlag.clear(msg);
+
+    call RSSIFlag.set(msg);
+    getMeta(msg)->rssi = value;
+  }
+
+  /*----------------- PacketTimeSyncOffset -----------------*/
+
+  async command bool PacketTimeSyncOffset.isSet(message_t* msg)
+  {
+    return call TimeSyncFlag.get(msg);
+  }
+
+  async command uint8_t PacketTimeSyncOffset.get(message_t* msg)
+  {
+    return call RadioPacket.headerLength(msg) + call  
RadioPacket.payloadLength(msg) - sizeof(timesync_absolute_t);
+  }
+
+  async command void PacketTimeSyncOffset.clear(message_t* msg)
+  {
+    call TimeSyncFlag.clear(msg);
+  }
+
+  async command void PacketTimeSyncOffset.set(message_t* msg, uint8_t  
value)
+  {
+    // we do not store the value, the time sync field is always the last 4  
bytes
+    RADIO_ASSERT( call PacketTimeSyncOffset.get(msg) == value );
+
+    call TimeSyncFlag.set(msg);
+  }
+
+  /*----------------- PacketLinkQuality -----------------*/
+
+  async command bool PacketLinkQuality.isSet(message_t* msg)
+  {
+    return TRUE;
+  }
+
+  async command uint8_t PacketLinkQuality.get(message_t* msg)
+  {
+    return getMeta(msg)->lqi;
+  }
+
+  async command void PacketLinkQuality.clear(message_t* msg)
+  {
+  }
+
+  async command void PacketLinkQuality.set(message_t* msg, uint8_t value)
+  {
+    getMeta(msg)->lqi = value;
+  }
+
+/*----------------- LinkPacketMetadata -----------------*/
+
+  async command bool LinkPacketMetadata.highChannelQuality(message_t* msg)
+  {
+    return call PacketLinkQuality.get(msg) > 200;
+  }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1Radio.h	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+#ifndef __RFA1RADIO_H__
+#define __RFA1RADIO_H__
+
+#include <RadioConfig.h>
+#include <TinyosNetworkLayer.h>
+#include <Ieee154PacketLayer.h>
+#include <ActiveMessageLayer.h>
+#include <MetadataFlagsLayer.h>
+#include <RFA1DriverLayer.h>
+#include <TimeStampingLayer.h>
+#include <LowPowerListeningLayer.h>
+#include <PacketLinkLayer.h>
+
+typedef nx_struct rfa1packet_header_t
+{
+	rfa1_header_t rfa1;
+	ieee154_simple_header_t ieee154;
+#ifndef TFRAMES_ENABLED
+	network_header_t network;
+#endif
+#ifndef IEEE154FRAMES_ENABLED
+	activemessage_header_t am;
+#endif
+} rfa1packet_header_t;
+
+typedef nx_struct rfa1packet_footer_t
+{
+	// the time stamp is not recorded here, time stamped messaged cannot have  
max length
+} rfa1packet_footer_t;
+
+typedef struct rfa1packet_metadata_t
+{
+#ifdef LOW_POWER_LISTENING
+	lpl_metadata_t lpl;
+#endif
+#ifdef PACKET_LINK
+	link_metadata_t link;
+#endif
+	timestamp_metadata_t timestamp;
+	flags_metadata_t flags;
+	rfa1_metadata_t rfa1;
+} rfa1packet_metadata_t;
+
+enum//masks for easyer handling
+{
+	RFA1_TX_PWR_MASK=0x0F,
+	RFA1_CHANNEL_MASK=0x1F,
+	RFA1_TRX_STATUS_MASK=0x1F,
+	RFA1_RSSI_MASK=0x1F,
+};
+
+#endif//__RFA1RADIO_H__
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1RadioC.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+#include <RadioConfig.h>
+
+configuration RFA1RadioC
+{
+	provides
+	{
+		interface SplitControl;
+
+#ifndef IEEE154FRAMES_ENABLED
+		interface AMSend[am_id_t id];
+		interface Receive[am_id_t id];
+		interface Receive as Snoop[am_id_t id];
+		interface SendNotifier[am_id_t id];
+
+		// for TOSThreads
+		interface Receive as ReceiveDefault[am_id_t id];
+		interface Receive as SnoopDefault[am_id_t id];
+
+		interface AMPacket;
+		interface Packet as PacketForActiveMessage;
+#endif
+
+#ifndef TFRAMES_ENABLED
+		interface Ieee154Send;
+		interface Receive as Ieee154Receive;
+		interface SendNotifier as Ieee154Notifier;
+
+		interface Resource as SendResource[uint8_t clint];
+
+		interface Ieee154Packet;
+		interface Packet as PacketForIeee154Message;
+#endif
+
+		interface PacketAcknowledgements;
+		interface LowPowerListening;
+
+#ifdef PACKET_LINK
+		interface PacketLink;
+#endif
+#ifdef TRAFFIC_MONITOR
+		interface TrafficMonitor;
+#endif
+
+		interface RadioChannel;
+
+		interface PacketField<uint8_t> as PacketLinkQuality;
+		interface PacketField<uint8_t> as PacketTransmitPower;
+		interface PacketField<uint8_t> as PacketRSSI;
+		interface LinkPacketMetadata;
+
+		interface LocalTime<TRadio> as LocalTimeRadio;
+		interface PacketTimeStamp<TRadio, uint32_t> as PacketTimeStampRadio;
+		interface PacketTimeStamp<TMilli, uint32_t> as PacketTimeStampMilli;
+	}
+}
+
+implementation
+{
+	#define UQ_METADATA_FLAGS	"UQ_RFA1_METADATA_FLAGS"
+	#define UQ_RADIO_ALARM		"UQ_RFA1_RADIO_ALARM"
+
+// -------- RadioP
+
+	components RFA1RadioP as RadioP;
+
+#ifdef RADIO_DEBUG
+	components AssertC;
+#endif
+
+	RadioP.Ieee154PacketLayer -> Ieee154PacketLayerC;
+	RadioP.RadioAlarm -> RadioAlarmC.RadioAlarm[unique(UQ_RADIO_ALARM)];
+	RadioP.PacketTimeStamp -> TimeStampingLayerC;
+	RadioP.RFA1Packet -> RadioDriverLayerC;
+
+// -------- RadioAlarm
+
+	components new RadioAlarmC();
+	RadioAlarmC.Alarm -> RadioDriverLayerC;
+
+// -------- Active Message
+
+#ifndef IEEE154FRAMES_ENABLED
+	components new ActiveMessageLayerC();
+	ActiveMessageLayerC.Config -> RadioP;
+	ActiveMessageLayerC.SubSend -> AutoResourceAcquireLayerC;
+	ActiveMessageLayerC.SubReceive -> TinyosNetworkLayerC.TinyosReceive;
+	ActiveMessageLayerC.SubPacket -> TinyosNetworkLayerC.TinyosPacket;
+
+	AMSend = ActiveMessageLayerC;
+	Receive = ActiveMessageLayerC.Receive;
+	Snoop = ActiveMessageLayerC.Snoop;
+	SendNotifier = ActiveMessageLayerC;
+	AMPacket = ActiveMessageLayerC;
+	PacketForActiveMessage = ActiveMessageLayerC;
+
+	ReceiveDefault = ActiveMessageLayerC.ReceiveDefault;
+	SnoopDefault = ActiveMessageLayerC.SnoopDefault;
+#endif
+
+// -------- Automatic RadioSend Resource
+
+#ifndef IEEE154FRAMES_ENABLED
+#ifndef TFRAMES_ENABLED
+	components new AutoResourceAcquireLayerC();
+	AutoResourceAcquireLayerC.Resource ->  
SendResourceC.Resource[unique(RADIO_SEND_RESOURCE)];
+#else
+	components new DummyLayerC() as AutoResourceAcquireLayerC;
+#endif
+	AutoResourceAcquireLayerC -> TinyosNetworkLayerC.TinyosSend;
+#endif
+
+// -------- RadioSend Resource
+
+#ifndef TFRAMES_ENABLED
+	components new SimpleFcfsArbiterC(RADIO_SEND_RESOURCE) as SendResourceC;
+	SendResource = SendResourceC;
+
+// -------- Ieee154 Message
+
+	components new Ieee154MessageLayerC();
+	Ieee154MessageLayerC.Ieee154PacketLayer -> Ieee154PacketLayerC;
+	Ieee154MessageLayerC.SubSend -> TinyosNetworkLayerC.Ieee154Send;
+	Ieee154MessageLayerC.SubReceive -> TinyosNetworkLayerC.Ieee154Receive;
+	Ieee154MessageLayerC.RadioPacket -> TinyosNetworkLayerC.Ieee154Packet;
+
+	Ieee154Send = Ieee154MessageLayerC;
+	Ieee154Receive = Ieee154MessageLayerC;
+	Ieee154Notifier = Ieee154MessageLayerC;
+	Ieee154Packet = Ieee154PacketLayerC;
+	PacketForIeee154Message = Ieee154MessageLayerC;
+#endif
+
+// -------- Tinyos Network
+
+	components new TinyosNetworkLayerC();
+
+	TinyosNetworkLayerC.SubSend -> UniqueLayerC;
+	TinyosNetworkLayerC.SubReceive -> PacketLinkLayerC;
+	TinyosNetworkLayerC.SubPacket -> Ieee154PacketLayerC;
+
+// -------- IEEE 802.15.4 Packet
+
+	components new Ieee154PacketLayerC();
+	Ieee154PacketLayerC.SubPacket -> PacketLinkLayerC;
+
+// -------- UniqueLayer Send part (wired twice)
+
+	components new UniqueLayerC();
+	UniqueLayerC.Config -> RadioP;
+	UniqueLayerC.SubSend -> PacketLinkLayerC;
+
+// -------- Packet Link
+
+#ifdef PACKET_LINK
+	components new PacketLinkLayerC();
+	PacketLink = PacketLinkLayerC;
+	PacketLinkLayerC.PacketAcknowledgements -> SoftwareAckLayerC;
+#else
+	components new DummyLayerC() as PacketLinkLayerC;
+#endif
+	PacketLinkLayerC -> LowPowerListeningLayerC.Send;
+	PacketLinkLayerC -> LowPowerListeningLayerC.Receive;
+	PacketLinkLayerC -> LowPowerListeningLayerC.RadioPacket;
+
+// -------- Low Power Listening
+
+#ifdef LOW_POWER_LISTENING
+	#warning "*** USING LOW POWER LISTENING LAYER"
+	components new LowPowerListeningLayerC();
+	LowPowerListeningLayerC.Config -> RadioP;
+	LowPowerListeningLayerC.PacketAcknowledgements -> SoftwareAckLayerC;
+#else
+	components new LowPowerListeningDummyC() as LowPowerListeningLayerC;
+#endif
+	LowPowerListeningLayerC.SubControl -> MessageBufferLayerC;
+	LowPowerListeningLayerC.SubSend -> MessageBufferLayerC;
+	LowPowerListeningLayerC.SubReceive -> MessageBufferLayerC;
+	LowPowerListeningLayerC.SubPacket -> TimeStampingLayerC;
+	SplitControl = LowPowerListeningLayerC;
+	LowPowerListening = LowPowerListeningLayerC;
+
+// -------- MessageBuffer
+
+	components new MessageBufferLayerC();
+	MessageBufferLayerC.RadioSend -> CollisionAvoidanceLayerC;
+	MessageBufferLayerC.RadioReceive -> UniqueLayerC;
+	MessageBufferLayerC.RadioState -> TrafficMonitorLayerC;
+	RadioChannel = MessageBufferLayerC;
+
+// -------- UniqueLayer receive part (wired twice)
+
+	UniqueLayerC.SubReceive -> CollisionAvoidanceLayerC;
+
+// -------- CollisionAvoidance
+
+#ifdef SLOTTED_MAC
+	components new SlottedCollisionLayerC() as CollisionAvoidanceLayerC;
+#else
+	components new RandomCollisionLayerC() as CollisionAvoidanceLayerC;
+#endif
+	CollisionAvoidanceLayerC.Config -> RadioP;
+	CollisionAvoidanceLayerC.SubSend -> SoftwareAckLayerC;
+	CollisionAvoidanceLayerC.SubReceive -> SoftwareAckLayerC;
+	CollisionAvoidanceLayerC.RadioAlarm ->  
RadioAlarmC.RadioAlarm[unique(UQ_RADIO_ALARM)];
+
+// -------- SoftwareAcknowledgement
+
+	components new SoftwareAckLayerC();
+	SoftwareAckLayerC.AckReceivedFlag ->  
MetadataFlagsLayerC.PacketFlag[unique(UQ_METADATA_FLAGS)];
+	SoftwareAckLayerC.RadioAlarm ->  
RadioAlarmC.RadioAlarm[unique(UQ_RADIO_ALARM)];
+	PacketAcknowledgements = SoftwareAckLayerC;
+	SoftwareAckLayerC.Config -> RadioP;
+	SoftwareAckLayerC.SubSend -> CsmaLayerC;
+	SoftwareAckLayerC.SubReceive -> CsmaLayerC;
+
+// -------- Carrier Sense
+
+	components new DummyLayerC() as CsmaLayerC;
+	CsmaLayerC.Config -> RadioP;
+	CsmaLayerC -> TrafficMonitorLayerC.RadioSend;
+	CsmaLayerC -> TrafficMonitorLayerC.RadioReceive;
+	CsmaLayerC -> RadioDriverLayerC.RadioCCA;
+
+// -------- TimeStamping
+
+	components new TimeStampingLayerC();
+	TimeStampingLayerC.LocalTimeRadio -> RadioDriverLayerC;
+	TimeStampingLayerC.SubPacket -> MetadataFlagsLayerC;
+	PacketTimeStampRadio = TimeStampingLayerC;
+	PacketTimeStampMilli = TimeStampingLayerC;
+	TimeStampingLayerC.TimeStampFlag ->  
MetadataFlagsLayerC.PacketFlag[unique(UQ_METADATA_FLAGS)];
+
+// -------- MetadataFlags
+
+	components new MetadataFlagsLayerC();
+	MetadataFlagsLayerC.SubPacket -> RadioDriverLayerC;
+
+// -------- Traffic Monitor
+
+#ifdef TRAFFIC_MONITOR
+	components new TrafficMonitorLayerC();
+	TrafficMonitor = TrafficMonitorLayerC;
+#else
+	components new DummyLayerC() as TrafficMonitorLayerC;
+#endif
+	TrafficMonitorLayerC.Config -> RadioP;
+	TrafficMonitorLayerC -> RadioDriverDebugLayerC.RadioSend;
+	TrafficMonitorLayerC -> RadioDriverLayerC.RadioReceive;
+	TrafficMonitorLayerC -> RadioDriverDebugLayerC.RadioState;
+
+// -------- Debug
+
+#ifdef RADIO_DEBUG
+	components new DebugLayerC("driver") as RadioDriverDebugLayerC;
+#else
+	components new DummyLayerC() as RadioDriverDebugLayerC;
+#endif
+	RadioDriverDebugLayerC.SubState -> RadioDriverLayerC;
+	RadioDriverDebugLayerC.SubSend -> RadioDriverLayerC;
+
+// -------- Driver
+
+	components RFA1DriverLayerC as RadioDriverLayerC;
+	RadioDriverLayerC.Config -> RadioP;
+	RadioDriverLayerC.PacketTimeStamp -> TimeStampingLayerC;
+	PacketTransmitPower = RadioDriverLayerC.PacketTransmitPower;
+	PacketLinkQuality = RadioDriverLayerC.PacketLinkQuality;
+	PacketRSSI = RadioDriverLayerC.PacketRSSI;
+	LinkPacketMetadata = RadioDriverLayerC;
+	LocalTimeRadio = RadioDriverLayerC;
+
+	RadioDriverLayerC.TransmitPowerFlag ->  
MetadataFlagsLayerC.PacketFlag[unique(UQ_METADATA_FLAGS)];
+	RadioDriverLayerC.RSSIFlag ->  
MetadataFlagsLayerC.PacketFlag[unique(UQ_METADATA_FLAGS)];
+	RadioDriverLayerC.TimeSyncFlag ->  
MetadataFlagsLayerC.PacketFlag[unique(UQ_METADATA_FLAGS)];
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1RadioOffP.nc	Sun Sep  4 02:04:37  
2011
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2010, University of Szeged
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Zsolt Szabo
+ */
+module RFA1RadioOffP {
+  provides interface Init as RFA1RadioOff;
+}
+implementation {
+  command error_t RFA1RadioOff.init() {
+    if(!uniqueCount("RFA1RadioOn")) {
+      TRXPR |= (1<<SLPTR);
+    }
+  return SUCCESS;
+  }
+}
=======================================
--- /dev/null
+++ /trunk/tos/chips/atm128rfa1/radio/RFA1RadioP.nc	Sun Sep  4 02:04:37 2011
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2007, Vanderbilt University
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * - Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * - Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the
+ *   distribution.
+ * - Neither the name of the copyright holder nor the names of
+ *   its contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
+ * OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Author: Miklos Maroti
+ * Author: Andras Biro
+ */
+
+#include <RFA1Radio.h>
+#include <RadioConfig.h>
+#include <Tasklet.h>
+
+module RFA1RadioP
+{
+	provides
+	{
+		interface RFA1DriverConfig;
+		interface SoftwareAckConfig;
+		interface UniqueConfig;
+		interface CsmaConfig;
+		interface TrafficMonitorConfig;
+		interface RandomCollisionConfig;
+		interface SlottedCollisionConfig;
+		interface ActiveMessageConfig;
+		interface DummyConfig;
+
+#ifdef LOW_POWER_LISTENING
+		interface LowPowerListeningConfig;
+#endif
+	}
+
+	uses
+	{
+		interface Ieee154PacketLayer;
+		interface RadioAlarm;
+		interface RadioPacket as RFA1Packet;
+
+		interface PacketTimeStamp<TRadio, uint32_t>;
+	}
+}
+
+implementation
+{
+
+/*----------------- RFA1DriverConfig -----------------*/
+
+	async command uint8_t RFA1DriverConfig.headerLength(message_t* msg)
+	{
+		return offsetof(message_t, data) - sizeof(rfa1packet_header_t);
+	}
+
+	async command uint8_t RFA1DriverConfig.maxPayloadLength()
+	{
+		return sizeof(rfa1packet_header_t) + TOSH_DATA_LENGTH;
+	}
+
+	async command uint8_t RFA1DriverConfig.metadataLength(message_t* msg)
+	{
+		return 0;
+	}
+
+	async command bool RFA1DriverConfig.requiresRssiCca(message_t* msg)
+	{
+		return call Ieee154PacketLayer.isDataFrame(msg);
+	}
+
+/*----------------- SoftwareAckConfig -----------------*/
+
+	async command bool SoftwareAckConfig.requiresAckWait(message_t* msg)
+	{
+		return call Ieee154PacketLayer.requiresAckWait(msg);
+	}
+
+	async command bool SoftwareAckConfig.isAckPacket(message_t* msg)
+	{
+		return call Ieee154PacketLayer.isAckFrame(msg);
+	}
+
+	async command bool SoftwareAckConfig.verifyAckPacket(message_t* data,  
message_t* ack)
+	{
+		return call Ieee154PacketLayer.verifyAckReply(data, ack);
+	}
+
+	async command void SoftwareAckConfig.setAckRequired(message_t* msg, bool  
ack)
+	{
+		call Ieee154PacketLayer.setAckRequired(msg, ack);
+	}
+
+	async command bool SoftwareAckConfig.requiresAckReply(message_t* msg)
+	{
+		return call Ieee154PacketLayer.requiresAckReply(msg);
+	}
+
+	async command void SoftwareAckConfig.createAckPacket(message_t* data,  
message_t* ack)
+	{
+		call Ieee154PacketLayer.createAckReply(data, ack);
+	}
+
+#ifndef SOFTWAREACK_TIMEOUT
+#define SOFTWAREACK_TIMEOUT	1000
+#endif
+
+	async command uint16_t SoftwareAckConfig.getAckTimeout()
+	{
+		return (uint16_t)(SOFTWAREACK_TIMEOUT * RADIO_ALARM_MICROSEC);
+	}
+
+	tasklet_async command void SoftwareAckConfig.reportChannelError()
+	{
+#ifdef TRAFFIC_MONITOR
+//		signal TrafficMonitorConfig.channelError();
+#endif
+	}
+
+/*----------------- UniqueConfig -----------------*/
+
+	async command uint8_t UniqueConfig.getSequenceNumber(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getDSN(msg);
+	}
+
+	async command void UniqueConfig.setSequenceNumber(message_t* msg, uint8_t  
dsn)
+	{
+		call Ieee154PacketLayer.setDSN(msg, dsn);
+	}
+
+	async command am_addr_t UniqueConfig.getSender(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getSrcAddr(msg);
+	}
+
+	tasklet_async command void UniqueConfig.reportChannelError()
+	{
+#ifdef TRAFFIC_MONITOR
+//		signal TrafficMonitorConfig.channelError();
+#endif
+	}
+
+/*----------------- ActiveMessageConfig -----------------*/
+
+	command am_addr_t ActiveMessageConfig.destination(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getDestAddr(msg);
+	}
+
+	command void ActiveMessageConfig.setDestination(message_t* msg, am_addr_t  
addr)
+	{
+		call Ieee154PacketLayer.setDestAddr(msg, addr);
+	}
+
+	command am_addr_t ActiveMessageConfig.source(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getSrcAddr(msg);
+	}
+
+	command void ActiveMessageConfig.setSource(message_t* msg, am_addr_t addr)
+	{
+		call Ieee154PacketLayer.setSrcAddr(msg, addr);
+	}
+
+	command am_group_t ActiveMessageConfig.group(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getDestPan(msg);
+	}
+
+	command void ActiveMessageConfig.setGroup(message_t* msg, am_group_t grp)
+	{
+		call Ieee154PacketLayer.setDestPan(msg, grp);
+	}
+
+	command error_t ActiveMessageConfig.checkFrame(message_t* msg)
+	{
+		if( ! call Ieee154PacketLayer.isDataFrame(msg) )
+			call Ieee154PacketLayer.createDataFrame(msg);
+
+		return SUCCESS;
+	}
+
+/*----------------- CsmaConfig -----------------*/
+
+	async command bool CsmaConfig.requiresSoftwareCCA(message_t* msg)
+	{
+		return call Ieee154PacketLayer.isDataFrame(msg);
+	}
+
+/*----------------- TrafficMonitorConfig -----------------*/
+
+	async command uint16_t TrafficMonitorConfig.getBytes(message_t* msg)
+	{
+		// pure airtime: preable (4 bytes), SFD (1 byte), length (1 byte),  
payload + CRC (len bytes)
+
+		return call RFA1Packet.payloadLength(msg) + 6;
+	}
+
+/*----------------- RandomCollisionConfig -----------------*/
+
+	/*
+	 * We try to use the same values as in CC2420
+	 *
+	 * CC2420_MIN_BACKOFF = 10 jiffies = 320 microsec
+	 * CC2420_BACKOFF_PERIOD = 10 jiffies
+	 * initial backoff = 0x1F * CC2420_BACKOFF_PERIOD = 310 jiffies = 9920  
microsec
+	 * congestion backoff = 0x7 * CC2420_BACKOFF_PERIOD = 70 jiffies = 2240  
microsec
+	 */
+
+#ifndef LOW_POWER_LISTENING
+
+#ifndef RFA1_BACKOFF_MIN
+#define RFA1_BACKOFF_MIN 320
+#endif
+
+	async command uint16_t RandomCollisionConfig.getMinimumBackoff()
+	{
+		return (uint16_t)(RFA1_BACKOFF_MIN * RADIO_ALARM_MICROSEC);
+	}
+
+#ifndef RFA1_BACKOFF_INIT
+#define RFA1_BACKOFF_INIT 4960		// instead of 9920
+#endif
+
+	async command uint16_t RandomCollisionConfig.getInitialBackoff(message_t*  
msg)
+	{
+		return (uint16_t)(RFA1_BACKOFF_INIT * RADIO_ALARM_MICROSEC);
+	}
+
+#ifndef RFA1_BACKOFF_CONG
+#define RFA1_BACKOFF_CONG 2240
+#endif
+
+	async command uint16_t  
RandomCollisionConfig.getCongestionBackoff(message_t* msg)
+	{
+		return (uint16_t)(RFA1_BACKOFF_CONG * RADIO_ALARM_MICROSEC);
+	}
+
+#endif
+
+	async command uint16_t  
RandomCollisionConfig.getTransmitBarrier(message_t* msg)
+	{
+		uint16_t time;
+
+		// TODO: maybe we should use the embedded timestamp of the message
+		time = call RadioAlarm.getNow();
+
+		// estimated response time (download the message, etc) is 5-8 bytes
+		if( call Ieee154PacketLayer.requiresAckReply(msg) )
+			time += (uint16_t)(32 * (-5 + 16 + 11 + 5) * RADIO_ALARM_MICROSEC);
+		else
+			time += (uint16_t)(32 * (-5 + 5) * RADIO_ALARM_MICROSEC);
+
+		return time;
+	}
+
+	tasklet_async event void RadioAlarm.fired()
+	{
+	}
+
+/*----------------- SlottedCollisionConfig -----------------*/
+
+	async command uint16_t SlottedCollisionConfig.getInitialDelay()
+	{
+		return 300;
+	}
+
+	async command uint8_t SlottedCollisionConfig.getScheduleExponent()
+	{
+		return 1 + RADIO_ALARM_MILLI_EXP;
+	}
+
+	async command uint16_t SlottedCollisionConfig.getTransmitTime(message_t*  
msg)
+	{
+		// TODO: check if the timestamp is correct
+		return call PacketTimeStamp.timestamp(msg);
+	}
+
+	async command uint16_t  
SlottedCollisionConfig.getCollisionWindowStart(message_t* msg)
+	{
+		// the preamble (4 bytes), SFD (1 byte), plus two extra for safety
+		return (call PacketTimeStamp.timestamp(msg)) - (uint16_t)(7 * 32 *  
RADIO_ALARM_MICROSEC);
+	}
+
+	async command uint16_t  
SlottedCollisionConfig.getCollisionWindowLength(message_t* msg)
+	{
+		return (uint16_t)(2 * 7 * 32 * RADIO_ALARM_MICROSEC);
+	}
+
+/*----------------- Dummy -----------------*/
+
+	async command void DummyConfig.nothing()
+	{
+	}
+
+/*----------------- LowPowerListening -----------------*/
+
+#ifdef LOW_POWER_LISTENING
+
+	command bool LowPowerListeningConfig.needsAutoAckRequest(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getDestAddr(msg) != TOS_BCAST_ADDR;
+	}
+
+	command bool LowPowerListeningConfig.ackRequested(message_t* msg)
+	{
+		return call Ieee154PacketLayer.getAckRequired(msg);
+	}
+
+	command uint16_t LowPowerListeningConfig.getListenLength()
+	{
+		return 5;
+	}
+
+	async command uint16_t RandomCollisionConfig.getMinimumBackoff()
+	{
+		return (uint16_t)(320 * RADIO_ALARM_MICROSEC);
+	}
+
+	async command uint16_t RandomCollisionConfig.getInitialBackoff(message_t*  
msg)
+	{
+		return (uint16_t)(1600 * RADIO_ALARM_MICROSEC);
+	}
+
+	async command uint16_t  
RandomCollisionConfig.getCongestionBackoff(message_t* msg)
+	{
+		return (uint16_t)(3200 * RADIO_ALARM_MICROSEC);
+	}
+
+#endif
+
+}
=======================================
***Additional files exist in this changeset.***


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