[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2 AM.h,
NONE, 1.1 HPLCC2420C.nc, NONE, 1.1 HPLCC2420M.nc, NONE,
1.1 HPLUART0M.nc, NONE, 1.1 HPLUARTC.nc, NONE, 1.1 README.txt,
NONE, 1.1 TimerJiffyAsyncC.nc, NONE, 1.1 TimerJiffyAsyncM.nc,
NONE, 1.1 bare.x, NONE, 1.1 barecrt.o, NONE, 1.1 barecrt.s,
NONE, 1.1 hardware.h, NONE, 1.1
Philip Buonadonna
philipb at users.sourceforge.net
Fri Nov 12 17:11:47 PST 2004
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HPLClock.nc, NONE, 1.1 HPLInit.nc, NONE, 1.1 HPLPotC.nc, NONE,
1.1 HPLPowerManagementM.nc, NONE, 1.1 PXA27XClockM.nc, NONE,
1.1 PXA27XGPIOInt.nc, NONE, 1.1 PXA27XGPIOIntM.nc, NONE,
1.1 PXA27XInterrupt.nc, NONE, 1.1 PXA27XInterruptM.nc, NONE,
1.1 README.txt, NONE, 1.1 arm_defs.h, NONE, 1.1 inttypes.h,
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Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv30900
Added Files:
AM.h HPLCC2420C.nc HPLCC2420M.nc HPLUART0M.nc HPLUARTC.nc
README.txt TimerJiffyAsyncC.nc TimerJiffyAsyncM.nc bare.x
barecrt.o barecrt.s hardware.h
Log Message:
- Initial import of imote2 support (beta)
--- NEW FILE: AM.h ---
// $Id: AM.h,v 1.1 2004/11/13 01:11:44 philipb Exp $
/* tab:4
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2003 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*/
/*
*
* Authors: Joe Polastre
* Date last modified: 4/19/2004
*
*/
// Message format
/**
* @author Joe Polastre
*/
#ifndef AM_H_INCLUDED
#define AM_H_INCLUDED
enum {
TOS_BCAST_ADDR = 0xffff,
TOS_UART_ADDR = 0x007e,
};
#ifndef DEF_TOS_AM_GROUP
#define DEF_TOS_AM_GROUP 0x7d
#endif
enum {
TOS_DEFAULT_AM_GROUP = DEF_TOS_AM_GROUP
};
uint8_t TOS_AM_GROUP = TOS_DEFAULT_AM_GROUP;
// TOSH_DATA_LENGTH *must* be an even number for the structure to be
// correctly word aligned!
#ifndef TOSH_DATA_LENGTH
#define TOSH_DATA_LENGTH 28
#endif
#ifndef TOSH_AM_LENGTH
#define TOSH_AM_LENGTH 1
#endif
typedef struct TOS_Msg
{
/* The following fields are transmitted/received on the radio. */
uint8_t length;
uint8_t fcfhi;
uint8_t fcflo;
uint8_t dsn;
uint16_t destpan;
uint16_t addr;
uint8_t type;
uint8_t group;
int8_t data[TOSH_DATA_LENGTH];
/* The following fields are not actually transmitted or received
* on the radio! They are used for internal accounting only.
* The reason they are in this structure is that the AM interface
* requires them to be part of the TOS_Msg that is passed to
* send/receive operations.
*/
uint8_t strength;
uint8_t lqi;
bool crc;
bool ack;
uint16_t time;
} __attribute((packed)) TOS_Msg;
enum {
// size of the header not including the length byte
MSG_HEADER_SIZE = offsetof(struct TOS_Msg, data) - 1,
// size of the footer
MSG_FOOTER_SIZE = 2,
// size of the full packet
MSG_DATA_SIZE = offsetof(struct TOS_Msg, strength) + sizeof(uint16_t),
// size of the data length
DATA_LENGTH = TOSH_DATA_LENGTH,
// position of the length byte
LENGTH_BYTE_NUMBER = offsetof(struct TOS_Msg, length) + 1,
};
typedef TOS_Msg *TOS_MsgPtr;
uint8_t TOS_MsgLength(uint8_t type)
{
#if 0
uint8_t i;
for (i = 0; i < MSGLEN_TABLE_SIZE; i++)
if (msgTable[i].handler == type)
return msgTable[i].length;
#endif
return offsetof(TOS_Msg, strength);
}
#endif
--- NEW FILE: HPLCC2420C.nc ---
// $Id: HPLCC2420C.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
/* tab:4
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2003 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*/
/*
*
* Authors: Joe Polastre
* Date last modified: $Revision: 1.1 $
*
*/
/**
* Low level hardware access to the CC2420
* @author Joe Polastre
*/
configuration HPLCC2420C {
provides {
interface StdControl;
interface HPLCC2420;
interface HPLCC2420RAM;
interface HPLCC2420FIFO;
interface HPLCC2420Interrupt as InterruptFIFOP;
interface HPLCC2420Interrupt as InterruptFIFO;
interface HPLCC2420Interrupt as InterruptCCA;
interface HPLCC2420Capture as CaptureSFD;
}
}
implementation
{
components HPLCC2420M, PXA27XGPIOIntM, PXA27XInterruptM;
StdControl = HPLCC2420M;
HPLCC2420 = HPLCC2420M;
HPLCC2420RAM = HPLCC2420M;
HPLCC2420FIFO = HPLCC2420M;
InterruptFIFOP = HPLCC2420M.InterruptFIFOP;
InterruptFIFO = HPLCC2420M.InterruptFIFO;
InterruptCCA = HPLCC2420M.InterruptCCA;
CaptureSFD = HPLCC2420M.CaptureSFD;
HPLCC2420M.GPIOControl -> PXA27XGPIOIntM.StdControl;
HPLCC2420M.FIFOP_GPIOInt -> PXA27XGPIOIntM.PXA27XGPIOInt[115];
HPLCC2420M.FIFO_GPIOInt -> PXA27XGPIOIntM.PXA27XGPIOInt[114];
HPLCC2420M.CCA_GPIOInt -> PXA27XGPIOIntM.PXA27XGPIOInt[116];
HPLCC2420M.SFD_GPIOInt -> PXA27XGPIOIntM.PXA27XGPIOInt[16];
PXA27XGPIOIntM.GPIOIrq0 -> PXA27XInterruptM.PXA27XIrq[PPID_GPIO_0];
PXA27XGPIOIntM.GPIOIrq1 -> PXA27XInterruptM.PXA27XIrq[PPID_GPIO_1];
PXA27XGPIOIntM.GPIOIrq -> PXA27XInterruptM.PXA27XIrq[PPID_GPIO_X];
HPLCC2420M.DMAInterrupt -> PXA27XInterruptM.PXA27XIrq[PPID_DMAC];
}
--- NEW FILE: HPLCC2420M.nc ---
// $Id: HPLCC2420M.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
/* tab:4
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2003 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*/
/*
*
* Authors: Phil Buonadonna
* Date last modified: $Revision: 1.1 $
*
*/
/**
* @author Phil Buonadonna
*/
module HPLCC2420M {
provides {
interface StdControl;
interface HPLCC2420;
interface HPLCC2420RAM;
interface HPLCC2420FIFO;
interface HPLCC2420Interrupt as InterruptFIFOP;
interface HPLCC2420Interrupt as InterruptFIFO;
interface HPLCC2420Interrupt as InterruptCCA;
interface HPLCC2420Capture as CaptureSFD;
}
uses {
interface StdControl as GPIOControl;
interface PXA27XGPIOInt as FIFOP_GPIOInt;
interface PXA27XGPIOInt as FIFO_GPIOInt;
interface PXA27XGPIOInt as CCA_GPIOInt;
interface PXA27XGPIOInt as SFD_GPIOInt;
interface PXA27XInterrupt as DMAInterrupt;
}
}
implementation
{
enum {
HPLCC2420_STATE_IDLE,
HPLCC2420_STATE_CMD,
HPLCC2420_STATE_WRITE,
HPLCC2420_STATE_READ,
HPLCC2420_STATE_RAMWR,
HPLCC2420_STATE_RAMRD,
HPLCC2420_STATE_FIFORD,
HPLCC2420_STATE_FIFOWR
};
enum {
PXA27X_SSP_FIFOMAXLEN = 13
};
uint8_t gIFState;
norace uint8_t* rxbuf;
norace uint8_t* txbuf;
norace uint8_t* txrambuf;
norace uint8_t* rxrambuf;
norace uint8_t txlen;
norace uint8_t rxlen;
norace uint8_t txramlen;
norace uint8_t rxramlen;
norace uint8_t rxdummy,txdummy;
norace uint16_t txramaddr;
norace uint16_t rxramaddr;
command result_t StdControl.init() {
atomic gIFState = HPLCC2420_STATE_IDLE;
// Set the appropriate GPIO bits
_GPDR(34) |= _GPIO_bit(34); // SSP3SCLK
_GPDR(35) |= _GPIO_bit(35); // SSP3TXD
_GPDR(41) &= ~(_GPIO_bit(41)); //SSP3RXD
_GPIO_setaltfn(34,3);
_GPIO_setaltfn(35,3);
_GPIO_setaltfn(41,3);
DRCMR(66) = ((1 << 7) | (0 & 0x1f)); // SSP3 Rx = DMA CH0
DRCMR(67) = ((1 << 7) | (1 & 0x1f)); // SSP3 Tx = DMA CH1
DALGN = (1 << 0); // Align Channel 0 for byte operations
call DMAInterrupt.allocate();
call GPIOControl.init();
return SUCCESS;
}
command result_t StdControl.start() {
CKEN |= (CKEN4_SSP3);
// Serial Clock Rate = 6.5 MHz, Frame Format = SPI, Data Size = 8-bit
SSCR0_3 = (SSCR0_SCR(1) | SSCR0_FRF(0) | SSCR0_DSS(0x7));
// RX&TX
SSCR1_3 = (SSCR1_TRAIL | SSCR1_TSRE | SSCR1_RSRE | SSCR1_RFT(8) | SSCR1_TFT(1));
SSTO_3 = 0;
SSCR0_3 |= SSCR0_SSE; // Enable SSP1 port
call DMAInterrupt.enable();
call GPIOControl.start();
return SUCCESS;
}
command result_t StdControl.stop() {
call DMAInterrupt.disable();
call GPIOControl.stop();
SSCR0_3 &= ~(SSCR0_SSE); // Disable SSP3 port
CKEN &= ~(CKEN4_SSP3);
return SUCCESS;
}
/**
* Send a command strobe
*
* @return status byte from the chipcon
*/
async command uint8_t HPLCC2420.cmd(uint8_t addr) {
uint8_t status = 0;
uint8_t tmp;
TOSH_CLR_CC_CSN_PIN();
// Empty the PXA recieve fifo...
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
SSDR_3 = addr;
while (SSSR_3 & SSSR_BSY);
TOSH_SET_CC_CSN_PIN();
status = SSDR_3;
return status;
}
/**
* Transmit 16-bit data
*
* @return status byte from the chipcon. 0xff is return of command failed.
*/
async command uint8_t HPLCC2420.write(uint8_t addr, uint16_t data) {
uint8_t status = 0;
uint8_t tmp;
TOSH_CLR_CC_CSN_PIN();
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
SSDR_3 = addr;
SSDR_3 = ((data >> 8) & 0xFF);
SSDR_3 = (data & 0xFF);
while (SSSR_3 & SSSR_BSY);
TOSH_SET_CC_CSN_PIN();
status = SSDR_3;
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
return status;
}
/**
* Read 16-bit data
*
* @return 16-bit register value
*/
async command uint16_t HPLCC2420.read(uint8_t addr) {
uint16_t data = 0;
uint8_t tmp;
TOSH_CLR_CC_CSN_PIN();
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
SSDR_3 = (addr | 0x40);
SSDR_3 = 0;
SSDR_3 = 0;
while (SSSR_3 & SSSR_BSY);
TOSH_SET_CC_CSN_PIN();
tmp = SSDR_3;
data = SSDR_3;
data = ((data << 8 ) & 0xFF00);
data |= SSDR_3;
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
return data;
}
task void signalRAMRd() {
signal HPLCC2420RAM.readDone(rxramaddr, rxramlen, rxrambuf);
}
async command result_t HPLCC2420RAM.read(uint16_t addr, uint8_t length, uint8_t* buffer) {
uint8_t i = 0, tmp;
// XXX - To simplify things, this only supports 11 byte reads. Longer would be
// signficantly more complicated.
if (length < 12) {
TOSH_CLR_CC_CSN_PIN();
atomic {
rxramaddr = addr;
rxramlen = length;
rxrambuf = buffer;
}
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
SSDR_3 = ((rxramaddr & 0x7F) | 0x80);
SSDR_3 = (((rxramaddr >> 1) & 0xC0) | 0x20);
for (i = 0; i < rxramlen; i++) {
SSDR_3 = 0;
}
while (SSSR_3 & SSSR_BSY);
TOSH_SET_CC_CSN_PIN();
tmp = SSDR_3;
tmp = SSDR_3;
for (i = 0; i < rxramlen; i++) {
rxrambuf[i] = SSDR_3;
}
return post signalRAMRd();
}
return FAIL;
}
task void signalRAMWr() {
signal HPLCC2420RAM.writeDone(txramaddr, txramlen, txrambuf);
}
async command result_t HPLCC2420RAM.write(uint16_t addr, uint8_t length, uint8_t* buffer) {
uint8_t i = 0, tmp;
if (length < 12) {
TOSH_CLR_CC_CSN_PIN();
atomic {
txramaddr = addr;
txramlen = length;
txrambuf = buffer;
}
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
SSDR_3 = ((txramaddr & 0x7F) | 0x80);
SSDR_3 = ((txramaddr >> 1) & 0xC0);
for (i = 0; i < txramlen; i++) {
SSDR_3 = txrambuf[i];
}
while (SSSR_3 & SSSR_BSY);
TOSH_SET_CC_CSN_PIN();
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
return post signalRAMWr();
}
return FAIL;
}
task void signalRXFIFO() {
signal HPLCC2420FIFO.RXFIFODone(rxlen, rxbuf);
}
/**
* Read from the RX FIFO queue. Will read bytes from the queue
* until the length is reached (determined by the first byte read).
* RXFIFODone() is signalled when all bytes have been read or the
* end of the packet has been reached.
*
* @param length number of bytes requested from the FIFO
* @param data buffer bytes should be placed into
*
* @return SUCCESS if the bus is free to read from the FIFO
*/
async command result_t HPLCC2420FIFO.readRXFIFO(uint8_t length, uint8_t *data) {
uint8_t tmp;
uint8_t pktlen;
result_t result = SUCCESS;
atomic {
rxbuf = data;
gIFState = HPLCC2420_STATE_FIFORD;
}
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
TOSH_CLR_CC_CSN_PIN();
DCSR(0) = (DCSR_NODESCFETCH);
DSADR(0) = ((uint32_t) &SSDR_3);
DTADR(0) = (uint32_t) &rxbuf[1];
DCSR(1) = (DCSR_NODESCFETCH);
DSADR(1) = (uint32_t) &txdummy;
DTADR(1) = ((uint32_t) &SSDR_3);
SSDR_3 = (CC2420_RXFIFO | 0x40);
SSDR_3 = 0;
while (SSSR_3 & SSSR_BSY);
tmp = SSDR_3;
pktlen = SSDR_3;
rxbuf[0] = pktlen;
if (pktlen > 0) {
//rxbuf = data;
pktlen++;
rxlen = (pktlen < length) ? pktlen : length;
DCMD(0) = (DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_LENGTH(rxlen-1));
DCMD(1) = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_LENGTH(rxlen-1));
DCSR(0) = (DCSR_RUN | DCSR_NODESCFETCH | DCSR_STOPIRQEN);
DCSR(1) = (DCSR_RUN | DCSR_NODESCFETCH);
SSTO_3 = (96*8);
}
else {
TOSH_SET_CC_CSN_PIN();
atomic gIFState = HPLCC2420_STATE_IDLE;
result = FAIL;
}
return result;
}
task void signalTXFIFO() {
signal HPLCC2420FIFO.TXFIFODone(txlen, txbuf);
}
/**
* Writes a series of bytes to the transmit FIFO.
*
* @param length length of data to be written
* @param data the first byte of data
*
* @return SUCCESS if the bus is free to write to the FIFO
*/
async command result_t HPLCC2420FIFO.writeTXFIFO(uint8_t length, uint8_t *data) {
atomic {
txbuf = data;
txlen = length;
gIFState = HPLCC2420_STATE_FIFOWR;
}
TOSH_CLR_CC_CSN_PIN();
DCSR(1) = (DCSR_NODESCFETCH);
DSADR(1) = (uint32_t) txbuf;
DTADR(1) = ((uint32_t) &SSDR_3);
DCMD(1) = (DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_LENGTH(txlen));
SSDR_3 = (CC2420_TXFIFO);
DCSR(1) = (DCSR_RUN | DCSR_NODESCFETCH | DCSR_STOPIRQEN);
return SUCCESS;
}
async command result_t InterruptFIFOP.startWait(bool low_to_high){
// set FIFOP to a rising edge interrupt
atomic {
call FIFOP_GPIOInt.disable();
call FIFOP_GPIOInt.clear();
if (low_to_high) {
call FIFOP_GPIOInt.enable(TOSH_RISING_EDGE);
}
else {
call FIFOP_GPIOInt.enable(TOSH_FALLING_EDGE);
}
}
return SUCCESS;
}
async command result_t InterruptFIFO.startWait(bool low_to_high){
// set FIFOP to a rising edge interrupt
atomic {
call FIFO_GPIOInt.disable();
call FIFO_GPIOInt.clear();
if (low_to_high) {
call FIFO_GPIOInt.enable(TOSH_RISING_EDGE);
}
else {
call FIFO_GPIOInt.enable(TOSH_FALLING_EDGE);
}
}
return SUCCESS;
}
async command result_t InterruptCCA.startWait(bool low_to_high){
// set FIFOP to a rising edge interrupt
atomic {
call CCA_GPIOInt.disable();
call CCA_GPIOInt.clear();
if (low_to_high) {
call CCA_GPIOInt.enable(TOSH_RISING_EDGE);
}
else {
call CCA_GPIOInt.enable(TOSH_FALLING_EDGE);
}
}
return SUCCESS;
}
async command result_t CaptureSFD.enableCapture(bool low_to_high){
// set FIFOP to a rising edge interrupt
atomic {
//call SFD_GPIOInt.disable();
// call SFD_GPIOInt.clear();
call SFD_GPIOInt.enable(TOSH_BOTH_EDGE);
#if 0
if (low_to_high) {
call SFD_GPIOInt.enable(TOSH_RISING_EDGE);
}
else {
call SFD_GPIOInt.enable(TOSH_FALLING_EDGE);
}
#endif
}
return SUCCESS;
}
async command result_t InterruptFIFOP.disable(){
// disable FIFOP interrupt
call FIFOP_GPIOInt.disable();
return SUCCESS;
}
async command result_t InterruptFIFO.disable(){
// disable FIFOP interrupt
call FIFO_GPIOInt.disable();
return SUCCESS;
}
async command result_t InterruptCCA.disable(){
// disable FIFOP interrupt
call CCA_GPIOInt.disable();
return SUCCESS;
}
async command result_t CaptureSFD.disable(){
// disable FIFOP interrupt
call SFD_GPIOInt.disable();
return SUCCESS;
}
async event void FIFOP_GPIOInt.fired() {
result_t result;
call FIFOP_GPIOInt.clear();
result = signal InterruptFIFOP.fired();
if (FAIL == result) {
call InterruptFIFOP.disable();
}
return;
}
async event void FIFO_GPIOInt.fired() {
result_t result;
call FIFO_GPIOInt.clear();
result = signal InterruptFIFO.fired();
if (FAIL == result) {
call InterruptFIFO.disable();
}
return;
}
async event void CCA_GPIOInt.fired() {
result_t result;
call CCA_GPIOInt.clear();
result = signal InterruptCCA.fired();
if (FAIL == result) {
call InterruptCCA.disable();
}
return;
}
async event void SFD_GPIOInt.fired() {
result_t result;
call SFD_GPIOInt.clear();
result = signal CaptureSFD.captured(0);
if (result == FAIL) {
call CaptureSFD.disable();
}
return;
}
async event void DMAInterrupt.fired() {
uint8_t i,tmp;
switch (gIFState) {
case HPLCC2420_STATE_IDLE:
break;
case HPLCC2420_STATE_FIFORD:
TOSH_SET_CC_CSN_PIN();
DCSR(0) = (DCSR_NODESCFETCH);
DCSR(1) = (DCSR_NODESCFETCH);
SSTO_3 = 0;
SSSR_3 |= (SSSR_TINT);
gIFState = HPLCC2420_STATE_IDLE;
post signalRXFIFO();
break;
case HPLCC2420_STATE_FIFOWR:
DCSR(1) = (DCSR_NODESCFETCH); // Clear the STOPPED interrupt
// Drain the RXFIFO
for (i = 0; i < 17; i++) {
tmp = SSDR_3;
}
TOSH_SET_CC_CSN_PIN();
gIFState = HPLCC2420_STATE_IDLE;
post signalTXFIFO();
break;
default:
break;
}
}
default async event result_t InterruptFIFOP.fired() {
return FAIL;
}
default async event result_t InterruptFIFO.fired() {
return FAIL;
}
default async event result_t InterruptCCA.fired() {
return FAIL;
}
default async event result_t CaptureSFD.captured(uint16_t val) {
return FAIL;
}
default async event result_t HPLCC2420FIFO.RXFIFODone(uint8_t length, uint8_t *data) {
return SUCCESS;
}
default async event result_t HPLCC2420FIFO.TXFIFODone(uint8_t length, uint8_t *data) {
return SUCCESS;
}
default async event result_t HPLCC2420RAM.readDone(uint16_t addr, uint8_t length, uint8_t *data) {
return SUCCESS;
}
default async event result_t HPLCC2420RAM.writeDone(uint16_t addr, uint8_t length, uint8_t *data) {
return SUCCESS;
}
}
--- NEW FILE: HPLUART0M.nc ---
// $Id: HPLUART0M.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
/* tab:4
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2003 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*/
/*
*
* Authors: Jason Hill, David Gay, Philip Levis, Phil Buonadonna, Joe Polastre
* Date last modified: $Revision: 1.1 $
*
*/
// The hardware presentation layer. See hpl.h for the C side.
// Note: there's a separate C side (hpl.h) to get access to the avr macros
// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component
/**
* @author Jason Hill
* @author David Gay
* @author Philip Levis
* @author Phil Buonadonna
* @author Joe Polastre
*/
module HPLUART0M {
provides interface HPLUART as UART;
}
implementation
{
task void SimPut() {
signal UART.putDone();
}
async command result_t UART.init() {
return SUCCESS;
}
async command result_t UART.stop() {
return SUCCESS;
}
default async event result_t UART.get(uint8_t data) { return SUCCESS; }
default async event result_t UART.putDone() { return SUCCESS; }
command async result_t UART.put(uint8_t data) {
post SimPut();
return SUCCESS;
}
}
--- NEW FILE: HPLUARTC.nc ---
// $Id: HPLUARTC.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
/* tab:4
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2003 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*/
/*
*
* Authors: Jason Hill, David Gay, Philip Levis
* Date last modified: $Id: HPLUARTC.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
*
*/
// The hardware presentation layer. See hpl.h for the C side.
// Note: there's a separate C side (hpl.h) to get access to the avr macros
// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component
/**
* @author Jason Hill
* @author David Gay
* @author Philip Levis
*/
configuration HPLUARTC {
provides interface HPLUART as UART;
}
implementation
{
components HPLUART0M;
UART = HPLUART0M;
}
--- NEW FILE: README.txt ---
Project: imote2 & pxa27x platform support beta
Description: TinyOS support files for the imote2 platform using the Intel PXA27X processor with
the CC2420 Radio.
Team Members:
- Philip Buonadonna (phil.buonadonna at intel.com)
- Ralph Kling (ralph.kling. at intel.com)
- Lama Nachman (lama.nachman at intel.com)
- Robert Adler (robert.p.adler at intel.com)
- Vincent Hummel (vincent.hummel at intel.com)
--- NEW FILE: TimerJiffyAsyncC.nc ---
//$Id: TimerJiffyAsyncC.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
// @author Cory Sharp <cssharp at eecs.berkeley.edu>
configuration TimerJiffyAsyncC
{
provides interface StdControl;
provides interface TimerJiffyAsync;
}
implementation
{
components TimerJiffyAsyncM, PXA27XInterruptM;
StdControl = TimerJiffyAsyncM;
TimerJiffyAsync = TimerJiffyAsyncM;
TimerJiffyAsyncM.OSTIrq -> PXA27XInterruptM.PXA27XIrq[PPID_OST_4_11];
}
--- NEW FILE: TimerJiffyAsyncM.nc ---
//$Id: TimerJiffyAsyncM.nc,v 1.1 2004/11/13 01:11:44 philipb Exp $
// @author Joe Polastre
/*****************************************************************************
Provides a highresolution (32uSec interval) timer for CC2420Radio stack
Uses ATMega128 Timer2 via HPLTimer2
*****************************************************************************/
module TimerJiffyAsyncM
{
provides interface StdControl;
provides interface TimerJiffyAsync;
uses interface PXA27XInterrupt as OSTIrq;
}
implementation
{
#define JIFFY_MAX ((1 << 27) -1)
uint32_t jiffy;
bool bSet;
void StartTimer(uint32_t interval) {
OSMR6 = (interval << 5);
atomic {
OIER |= (OIER_E6);
}
OSCR6 = 0x0UL;
}
command result_t StdControl.init()
{
// call Alarm.setControlAsTimer();
call OSTIrq.allocate();
OMCR6 = (OMCR_C | OMCR_R | OMCR_CRES(0x4)); // Aperiodic, 1us increment
return SUCCESS;
}
command result_t StdControl.start()
{
atomic bSet = FALSE;
return SUCCESS;
}
command result_t StdControl.stop()
{
atomic {
bSet = FALSE;
atomic {
OIER &= ~(OIER_E6);
}
//call Timer.intDisable();
}
return SUCCESS;
}
// async event void Alarm.fired()
async event void OSTIrq.fired() {
uint32_t localjiffy;
atomic localjiffy = jiffy;
if (OSSR & OIER_E6) {
OSSR = OIER_E6; // reset status bit
if (localjiffy < JIFFY_MAX) {
atomic {
OIER &= ~(OIER_E6); //call Timer.intDisable();
}
atomic bSet = FALSE;
signal TimerJiffyAsync.fired(); //finished!
}
else {
localjiffy = localjiffy - JIFFY_MAX;
//atomic jiffy = localjiffy;
call TimerJiffyAsync.setOneShot(localjiffy);
}
}
return;
}
async command result_t TimerJiffyAsync.setOneShot( uint32_t _jiffy )
{
atomic {
jiffy = _jiffy;
bSet = TRUE;
}
if (_jiffy > JIFFY_MAX) {
StartTimer(JIFFY_MAX);
}
else {
StartTimer(_jiffy);
}
return SUCCESS;
}
async command bool TimerJiffyAsync.isSet( )
{
bool val;
atomic val = bSet;
return val;
}
async command result_t TimerJiffyAsync.stop()
{
atomic {
bSet = FALSE;
atomic {
OIER &= ~(OIER_E6);//call Timer.intDisable();
}
}
return SUCCESS;
}
}//TimerJiffyAsync
--- NEW FILE: bare.x ---
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
"elf32-littlearm")
OUTPUT_ARCH(arm)
MEMORY
{
text (rx) : ORIGIN = 0, LENGTH = 64M
data (rw!x) : ORIGIN = 0x5c000000, LENGTH = 256K
}
SECTIONS
{
.text :
{
*(.vectors)
*(.text .stub .text.* .gnu.linkonce.t.*)
*(.rodata.*)
*(.rodata)
/* .gnu.warning sections are handled specially by elf32.em. */
*(.gnu.warning)
*(.glue_7t) *(.glue_7)
KEEP (*(.fini))
} >text
PROVIDE (__etext = .);
PROVIDE (_etext = .);
PROVIDE (etext = .);
.data : AT (ADDR(.text) + SIZEOF(.text))
{
__data_start = . ;
*(.data .data.* .gnu.linkonce.d.*)
*(.gnu.linkonce.d*)
_edata = .;
PROVIDE (edata = .);
} > data
.bss SIZEOF(.data) + ADDR(.data) :
{
__bss_start = .;
__bss_start__ = .;
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);
} >data
__data_load_start = LOADADDR(.data);
__data_load_end = __data_load_start + SIZEOF(.data);
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.stack 0x80000 :
{
_stack = .;
*(.stack)
}
/DISCARD/ : { *(.note.GNU-stack) }
}
--- NEW FILE: barecrt.o ---
ELFa
0Ðä0Âä
Àä#
--- NEW FILE: barecrt.s ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
*
* Authors: Phil Buonadonna,David Gay
* Date last modified: $Revision: 1.1 $
*
*/
.equ ARM_CPSR_MODE_MASK,(0x0000001F)
.equ ARM_CPSR_INT_MASK,(0x000000C0)
.equ ARM_CPSR_COND_MASK,(0xF8000000)
.equ ARM_CPSR_MODE_USR,(0x10)
.equ ARM_CPSR_MODE_FIQ,(0x11)
.equ ARM_CPSR_MODE_IRQ,(0x12)
.equ ARM_CPSR_MODE_SVC,(0x13)
.equ ARM_CPSR_MODE_ABT,(0x17)
.equ ARM_CPSR_MODE_UND,(0x1B)
.equ ARM_CPSR_MODE_SYS,(0x1F)
.equ ARM_CPSR_BIT_N,(0x80000000)
.equ ARM_CPSR_BIT_Z,(0x40000000)
.equ ARM_CPSR_BIT_C,(0x20000000)
.equ ARM_CPSR_BIT_V,(0x10000000)
.equ ARM_CPSR_BIT_Q,(0x08000000)
.equ ARM_CPSR_BIT_I,(0x00000080)
.equ ARM_CPSR_BIT_F,(0x00000040)
.equ ARM_CPRS_BIT_T,(0x00000020)
.equ _TOS_STACK_SIZE,(0x400) @ TinyOS Exception stack sizes
.equ _TOS_ISRAM_PHYSBASE,(0x5C000000) @ Internal SRAM on PXA27X
.text
.globl start
start:
mrs r0, CPSR
bic r0, r0, #ARM_CPSR_MODE_MASK
orr r0, r0, #(ARM_CPSR_MODE_SVC | ARM_CPSR_INT_MASK)
msr cpsr_cf, r0
/* Initialize the stack pointers for all modes */
mov r0,#_TOS_ISRAM_PHYSBASE
ldr r2, =(256*1024 - 4) @ and go to the last slot (256K - 4)
add r2,r2,r0
mov r0, #ARM_CPSR_MODE_ABT
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #_TOS_STACK_SIZE
mov r0, #ARM_CPSR_MODE_UND
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #_TOS_STACK_SIZE
mov r0, #ARM_CPSR_MODE_FIQ
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #_TOS_STACK_SIZE
mov r0, #ARM_CPSR_MODE_IRQ
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #(_TOS_STACK_SIZE * 2)
mov r0, #ARM_CPSR_MODE_SVC
msr CPSR_c, R0
mov sp, r2
/* copy data */
ldr r0, =__data_load_start
ldr r1, =__data_load_end
ldr r2, =__data_start
.Lcopy:
cmp r0, r1
beq .Lcopydone
ldrb r3, [r0], #1
strb r3, [r2], #1
b .Lcopy
.Lcopydone:
/* clear bss */
ldr r0, =__bss_start__
ldr r1, =__bss_end__
mov r2, #0
.Lclear:
cmp r0, r1
beq .Lcleardone
strb r2, [r0], #1
b .Lclear
.Lcleardone:
mov r0, #0 /* argc? */
mov r1, #0 /* argv? */
bl main
.L1:
nop
b .L1
hplarmv_undef:
b start
hplarmv_swi:
b start
hplarmv_pabort:
b start
hplarmv_dabort:
b start
hplarmv_reserved:
b start
hplarmv_irq:
hplarmv_fiq:
b start
.weak hplarmv_undef, hplarmv_swi, hplarmv_pabort, hplarmv_dabort, hplarmv_reserved, hplarmv_irq, hplarmv_fiq
.section .vectors
b start
b hplarmv_undef
b hplarmv_swi
b hplarmv_pabort
b hplarmv_dabort
b hplarmv_reserved
b hplarmv_irq
b hplarmv_fiq
--- NEW FILE: hardware.h ---
/* tab:4
*
*
* "Copyright (c) 2000-2002 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
*/
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
*
* Authors: Philip Buonadonna
*
*
*/
#ifndef TOSH_HARDWARE_H
#define TOSH_HARDWARE_H
#include "pxa27xhardware.h"
#include "CC2420Const.h"
#include "AM.h"
#define MIN(a,b) ((a) < (b) ? (a) : (b))
/* Watchdog Prescaler
*/
enum {
TOSH_period16 = 0x00, // 47ms
TOSH_period32 = 0x01, // 94ms
TOSH_period64 = 0x02, // 0.19s
TOSH_period128 = 0x03, // 0.38s
TOSH_period256 = 0x04, // 0.75s
TOSH_period512 = 0x05, // 1.5s
TOSH_period1024 = 0x06, // 3.0s
TOSH_period2048 = 0x07 // 6.0s
};
/* Global interrupt priority table.
* Table is indexed by the Peripheral ID (PPID). Priorities are 0 - 39
* where 0 is the highest. Priorities MUST be unique. 0XFF = invalid/unassigned
*/
const uint8_t TOSH_IRP_TABLE[] = { 0xFF, // PPID 0 SSP_3 Service Req
0xFF, // PPID 1 MSL
0xFF, // PPID 2 USBH2
0xFF, // PPID 3 USBH1
0xFF, // PPID 4 Keypad
0xFF, // PPID 5 Memory Stick
0xFF, // PPID 6 Power I2C
0x00, // PPID 7 OST match Register 4-11
0x01, // PPID 8 GPIO_0
0x02, // PPID 9 GPIO_1
0x03, // PPID 10 GPIO_x
0xFF, // PPID 11 USBC
0xFF, // PPID 12 PMU
0xFF, // PPID 13 I2S
0xFF, // PPID 14 AC '97
0xFF, // PPID 15 SIM status/error
0xFF, // PPID 16 SSP_2 Service Req
0xFF, // PPID 17 LCD Controller Service Req
0xFF, // PPID 18 I2C Service Req
0xFF, // PPID 19 TX/RX ERROR IRDA
0xFF, // PPID 20 TX/RX ERROR STUART
0xFF, // PPID 21 TX/RX ERROR BTUART
0xFF, // PPID 22 TX/RX ERROR FFUART
0xFF, // PPID 23 Flash Card status/Error Detect
0xFF, // PPID 24 SSP_1 Service Req
0x04, // PPID 25 DMA Channel Service Req
0xFF, // PPID 26 OST equals Match Register 0
0xFF, // PPID 27 OST equals Match Register 1
0xFF, // PPID 28 OST equals Match Register 2
0xFF, // PPID 29 OST equals Match Register 3
0xFF, // PPID 30 RTC One HZ TIC
0xFF, // PPID 31 RTC equals Alarm
0xFF, // PPID 32
0xFF, // PPID 33 Quick Capture Interface
0xFF, // PPID 34
0xFF, // PPID 35
0xFF, // PPID 36
0xFF, // PPID 37
0xFF, // PPID 38
0xFF // PPID 39
};
// LED assignments
TOSH_ASSIGN_PIN(RED_LED, A, 95);
TOSH_ASSIGN_PIN(GREEN_LED, A, 102);
TOSH_ASSIGN_PIN(YELLOW_LED, A, 93);
// CC2420 RADIO #defines
TOSH_ASSIGN_PIN(CC_VREN,A,40); // Dummy for Mainstone devel kit
TOSH_ASSIGN_PIN(CC_RSTN,A,22);
TOSH_ASSIGN_PIN(CC_FIFO,A,114);
TOSH_ASSIGN_PIN(RADIO_CCA,A,116);
TOSH_ASSIGN_PIN(CC_FIFOP,A,115);
TOSH_ASSIGN_PIN(CC_SFD,A,16);
TOSH_ASSIGN_PIN(CC_CSN,A,39)
void TOSH_SET_PIN_DIRECTIONS(void)
{
PSSR = (PSSR_RDH | PSSR_PH); // Renalbe the GPIO buffers (needed out of reset)
TOSH_CLR_CC_RSTN_PIN();
TOSH_MAKE_CC_RSTN_OUTPUT();
TOSH_CLR_CC_VREN_PIN();
TOSH_MAKE_CC_VREN_OUTPUT();
TOSH_SET_CC_CSN_PIN();
TOSH_MAKE_CC_CSN_OUTPUT();
TOSH_MAKE_CC_FIFOP_INPUT();
TOSH_MAKE_CC_FIFO_INPUT();
TOSH_MAKE_CC_SFD_INPUT();
TOSH_MAKE_RADIO_CCA_INPUT();
}
#endif //TOSH_HARDWARE_H
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- Next message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
HPLClock.nc, NONE, 1.1 HPLInit.nc, NONE, 1.1 HPLPotC.nc, NONE,
1.1 HPLPowerManagementM.nc, NONE, 1.1 PXA27XClockM.nc, NONE,
1.1 PXA27XGPIOInt.nc, NONE, 1.1 PXA27XGPIOIntM.nc, NONE,
1.1 PXA27XInterrupt.nc, NONE, 1.1 PXA27XInterruptM.nc, NONE,
1.1 README.txt, NONE, 1.1 arm_defs.h, NONE, 1.1 inttypes.h,
NONE, 1.1 pxa27x_registers.h, NONE, 1.1 pxa27xhardware.h, NONE, 1.1
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