[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
barecrt.s, NONE, 1.1 mmu_table.s, NONE, 1.1 util.s, NONE,
1.1 HPLInit.nc, 1.3, 1.4
Robbie Adler
radler at users.sourceforge.net
Thu Aug 4 15:34:28 PDT 2005
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AccelDriverM.nc, 1.3, 1.4 Mic.h, 1.1, 1.2 MicDriverC.nc, 1.2,
1.3 MicDriverM.nc, 1.2, 1.3 PhotoDriverM.nc, 1.2, 1.3
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pxa27x_registers.h, 1.5, 1.6
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Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv2724
Modified Files:
HPLInit.nc
Added Files:
barecrt.s mmu_table.s util.s
Log Message:
added: MMU intialization, page table initialization, cache/tlb init (defaults to WT mode instead of WB), Memory Controller initialization to synchronous burst of 16 mode
eliminated improper 13M mode setting
--- NEW FILE: barecrt.s ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
*
* Authors: Phil Buonadonna,David Gay
* Date last modified: $Revision: 1.1 $
*
*/
.equ ARM_CPSR_MODE_MASK,(0x0000001F)
.equ ARM_CPSR_INT_MASK,(0x000000C0)
.equ ARM_CPSR_COND_MASK,(0xF8000000)
.equ ARM_CPSR_MODE_USR,(0x10)
.equ ARM_CPSR_MODE_FIQ,(0x11)
.equ ARM_CPSR_MODE_IRQ,(0x12)
.equ ARM_CPSR_MODE_SVC,(0x13)
.equ ARM_CPSR_MODE_ABT,(0x17)
.equ ARM_CPSR_MODE_UND,(0x1B)
.equ ARM_CPSR_MODE_SYS,(0x1F)
.equ ARM_CPSR_BIT_N,(0x80000000)
.equ ARM_CPSR_BIT_Z,(0x40000000)
.equ ARM_CPSR_BIT_C,(0x20000000)
.equ ARM_CPSR_BIT_V,(0x10000000)
.equ ARM_CPSR_BIT_Q,(0x08000000)
.equ ARM_CPSR_BIT_I,(0x00000080)
.equ ARM_CPSR_BIT_F,(0x00000040)
.equ ARM_CPRS_BIT_T,(0x00000020)
.equ _TOS_STACK_SIZE,(0x400) @ TinyOS Exception stack sizes
.equ _TOS_ISRAM_PHYSBASE,(0x5C000000) @ Internal SRAM on PXA27X
.text
.globl start
start:
mrs r0, CPSR
bic r0, r0, #ARM_CPSR_MODE_MASK
orr r0, r0, #(ARM_CPSR_MODE_SVC | ARM_CPSR_INT_MASK)
msr cpsr_cf, r0
/* Initialize the stack pointers for all modes */
mov r0,#_TOS_ISRAM_PHYSBASE
ldr r2, =(256*1024 - 4) @ and go to the last slot (256K - 4)
add r2,r2,r0
mov r0, #ARM_CPSR_MODE_ABT
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #_TOS_STACK_SIZE
mov r0, #ARM_CPSR_MODE_UND
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #_TOS_STACK_SIZE
mov r0, #ARM_CPSR_MODE_FIQ
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #_TOS_STACK_SIZE
mov r0, #ARM_CPSR_MODE_IRQ
msr CPSR_c, R0
mov sp, r2
sub r2, r2, #(_TOS_STACK_SIZE * 2)
mov r0, #ARM_CPSR_MODE_SVC
msr CPSR_c, R0
mov sp, r2
/* copy data */
ldr r0, =__data_load_start
ldr r1, =__data_load_end
ldr r2, =__data_start
.Lcopy:
cmp r0, r1
beq .Lcopydone
ldrb r3, [r0], #1
strb r3, [r2], #1
b .Lcopy
.Lcopydone:
/* clear bss */
ldr r0, =__bss_start__
ldr r1, =__bss_end__
mov r2, #0
.Lclear:
cmp r0, r1
beq .Lcleardone
strb r2, [r0], #1
b .Lclear
.Lcleardone:
mov r0, #0 /* argc? */
mov r1, #0 /* argv? */
bl main
.L1:
nop
b .L1
hplarmv_undef:
b start
hplarmv_swi:
b start
hplarmv_pabort:
b start
hplarmv_dabort:
b start
hplarmv_reserved:
b start
hplarmv_irq:
hplarmv_fiq:
b start
.weak hplarmv_undef, hplarmv_swi, hplarmv_pabort, hplarmv_dabort, hplarmv_reserved, hplarmv_irq, hplarmv_fiq
.section .vectors
b start
b hplarmv_undef
b hplarmv_swi
b hplarmv_pabort
b hplarmv_dabort
b hplarmv_reserved
b hplarmv_irq
b hplarmv_fiq
--- NEW FILE: mmu_table.s ---
@/*********************************************************************
@Copyright: (c) Intel Corporation, 2002, 2003
@
@INTEL MAKES NO WARRANTY OF ANY KIND REGARDING THE CODE. THIS CODE IS
@LICENSED ON AN "AS IS" BASIS AND INTEL WILL NOT PROVIDE ANY SUPPORT,
@ASSISTANCE, INSTALLATION, TRAINING OR OTHER SERVICES. INTEL DOES NOT
@PROVIDE ANY UPDATES ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY
@DISCLAIMS ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS
@FOR ANY PARTICULAR PURPOSE, OR ANY OTHER WARRANTY. INTEL DISCLAIMS
@ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGMENT OF ANY PROPRIETARY
@RIGHTS, RELATING TO USE OF THE CODE. NO LICENSE, EXPRESS OR IMPLIED,
@BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS
@GRANTED HEREIN.
@*********************************************************************/@
@ File: mmu_table.s
@
@ Uses Section descriptor within the First-level dscriptor format
@
@ For Bulverde
@
@ 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
@ 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
@
@ --- Virtual Offset ---- 0 0 0 0 0 0 0 X -AP 0 -Domain 0 C B 1 0 <---- 1MB page descriptor
@
@
@
@ X C B
@ 0 0 0 IO Cycle, stall until complete
@ 0 0 1 Write merging, but uncached
@ 0 1 0 Buffering, cache Write-Through mode, read allocate
@ 0 1 1 Regular Caching, Writi-Through mode, read allocate
@
@ 1 0 0 Unpredictable
@ 1 0 1 Buffer Writes, but don't coalesce
@ 1 1 0 Mini D-Cache, (cache policy is determined by MD field of Auxillary Control Reg)
@ 1 1 1 Same as X=0 with Read & Write Allocate
@
@
@ write-through table (SDRAM / SRAM Write-through, Flash / ROM banks still write-back)
@ write-back table
@.ALIGN 0x4000
.align 14
.global MMUTableWT
MMUTableWT:
.word 0x0000000A @ ROM (x=0,c=1,b=1 => Write-Through)
.word 0x0010000A
.word 0x0020000A
.word 0x0030000A
.word 0x0040000A
.word 0x0050000A
.word 0x0060000A
.word 0x0070000A
.word 0x0080000A
.word 0x0090000A
.word 0x00A0000A
.word 0x00B0000A
.word 0x00C0000A
.word 0x00D0000A
.word 0x00E0000A
.word 0x00F0000A
.word 0x0100000A
.word 0x0110000A
.word 0x0120000A
.word 0x0130000A
.word 0x0140000A
.word 0x0150000A
.word 0x0160000A
.word 0x0170000A
.word 0x0180000A
.word 0x0190000A
.word 0x01A0000A
.word 0x01B0000A
.word 0x01C0000A
.word 0x01D0000A
.word 0x01E0000A
.word 0x01F0000A @ 32 MByte
@.ALIGN 0x100 @(0x4100=0x4000+0x040*4)
.align 8
.word 0x0400000A @ Flash (x=0,c=1,b=1 => Write-Through)
.word 0x0410000A
.word 0x0420000A
.word 0x0430000A
.word 0x0440000A
.word 0x0450000A
.word 0x0460000A
.word 0x0470000A
.word 0x0480000A
.word 0x0490000A
.word 0x04A0000A
.word 0x04B0000A
.word 0x04C0000A
.word 0x04D0000A
.word 0x04E0000A
.word 0x04F0000A
.word 0x0500000A
.word 0x0510000A
.word 0x0520000A
.word 0x0530000A
.word 0x0540000A
.word 0x0550000A
.word 0x0560000A
.word 0x0570000A
.word 0x0580000A
.word 0x0590000A
.word 0x05A0000A
.word 0x05B0000A
.word 0x05C0000A
.word 0x05D0000A
.word 0x05E0000A
.word 0x05F0000A @ 32 MByte
@.ALIGN 0x100 @(0x4200=0x4000+0x080*4)
.align 8
.word 0x08000002 @ Mainstone Board Regs (x=0,c=0,b=0 => I/O space)
@.ALIGN 0x80 @(0x4280=0x4000+0x0A0*4)
.align 7
.word 0x0A00000A @ nCS2 - 2M SRAM (x=0,c=1,b=1 => Write-Through)
.word 0x0A10000A @
@.ALIGN 0x80 @(0x4300=0x4000+0x0C0*4)
.align 7
.word 0x0 @ (nCS3 (x=0,c=0,b=0 => I/O space)
@.ALIGN 0x100 @(0x4400=0x4000+0x100*4)
.align 8
.word 0x10000002 @ nCS4 - 100BASE2 Ethernet (x=0,c=0,b=0 => I/O space)
.word 0x10100002
.word 0x10200002
.word 0x10300002
@.ALIGN 0x100 @(0x4500=0x4000+0x140*4)
.align 8
.word 0x14000002 @ nCS5 - Expansion Connector (x=0,c=0,b=0 => I/O space)
.word 0x14100002
.word 0x14200002
.word 0x14300002
@.ALIGN 0x400 @(0x4800=0x4000+0x200*4)
.align 10
.word 0x20000002 @ PCMCIA/CF Slot 0 (x=0,c=0,b=0 => I/O space)
.word 0x20100002
.word 0x20200002
.word 0x20300002 @ REALLY SHOULD BE 256 MB!!!!!!
@.ALIGN 0x400 @(0x4C00=0x4000+0x300*4)
.align 10
.word 0x30000002 @ PCMCIA/CF Slot 1 (x=0,c=0,b=0 => I/O space)
.word 0x30100002
.word 0x30200002
.word 0x30300002 @ REALLY SHOULD BE 256 MB!!!!!!
@.ALIGN 0x400 @(0x5000=0x4000+0x400*4)
.align 10
.word 0x40000002 @ Internal Registers (periphs) (x=0,c=0,b=0 => I/O space)
.word 0x40100002
.word 0x40200002
.word 0x40300002
.word 0x40400002
.word 0x40500002
.word 0x40600002
.word 0x40700002
.word 0x40800002
.word 0x40900002
.word 0x40A00002
.word 0x40B00002
.word 0x40C00002
.word 0x40D00002
.word 0x40E00002
.word 0x40F00002
.word 0x41000002
.word 0x41100002
.word 0x41200002
.word 0x41300002
.word 0x41400002
.word 0x41500002
.word 0x41600002
.word 0x41700002
.word 0x41800002
.word 0x41900002
.word 0x41A00002
.word 0x41B00002
.word 0x41C00002
.word 0x41D00002
.word 0x41E00002
.word 0x41F00002 @ 32 MByte
.word 0x42000002
.word 0x42100002
.word 0x42200002
.word 0x42300002
.word 0x42400002
.word 0x42500002
.word 0x42600002
.word 0x42700002
.word 0x42800002
.word 0x42900002
.word 0x42A00002
.word 0x42B00002
.word 0x42C00002
.word 0x42D00002
.word 0x42E00002
.word 0x42F00002
.word 0x43000002
.word 0x43100002
.word 0x43200002
.word 0x43300002
.word 0x43400002
.word 0x43500002
.word 0x43600002
.word 0x43700002
.word 0x43800002
.word 0x43900002
.word 0x43A00002
.word 0x43B00002
.word 0x43C00002
.word 0x43D00002
.word 0x43E00002
.word 0x43F00002 @ 32 MByte
.word 0x44000002 @ Internal Registers (LCD) (x=0,c=0,b=0 => I/O space)
.word 0x44100002
.word 0x44200002
.word 0x44300002
.word 0x44400002
.word 0x44500002
.word 0x44600002
.word 0x44700002
.word 0x44800002
.word 0x44900002
.word 0x44A00002
.word 0x44B00002
.word 0x44C00002
.word 0x44D00002
.word 0x44E00002
.word 0x44F00002
.word 0x45000002
.word 0x45100002
.word 0x45200002
.word 0x45300002
.word 0x45400002
.word 0x45500002
.word 0x45600002
.word 0x45700002
.word 0x45800002
.word 0x45900002
.word 0x45A00002
.word 0x45B00002
.word 0x45C00002
.word 0x45D00002
.word 0x45E00002
.word 0x45F00002 @ 32 MByte
.word 0x46000002
.word 0x46100002
.word 0x46200002
.word 0x46300002
.word 0x46400002
.word 0x46500002
.word 0x46600002
.word 0x46700002
.word 0x46800002
.word 0x46900002
.word 0x46A00002
.word 0x46B00002
.word 0x46C00002
.word 0x46D00002
.word 0x46E00002
.word 0x46F00002
.word 0x47000002
.word 0x47100002
.word 0x47200002
.word 0x47300002
.word 0x47400002
.word 0x47500002
.word 0x47600002
.word 0x47700002
.word 0x47800002
.word 0x47900002
.word 0x47A00002
.word 0x47B00002
.word 0x47C00002
.word 0x47D00002
.word 0x47E00002
.word 0x47F00002 @ 32 MByte
.word 0x48000002 @ Internal Registers (mem ctrl) (x=0,c=0,b=0 => I/O space)
.word 0x48100002
.word 0x48200002
.word 0x48300002
.word 0x48400002
.word 0x48500002
.word 0x48600002
.word 0x48700002
.word 0x48800002
.word 0x48900002
.word 0x48A00002
.word 0x48B00002
.word 0x48C00002
.word 0x48D00002
.word 0x48E00002
.word 0x48F00002
.word 0x49000002
.word 0x49100002
.word 0x49200002
.word 0x49300002
.word 0x49400002
.word 0x49500002
.word 0x49600002
.word 0x49700002
.word 0x49800002
.word 0x49900002
.word 0x49A00002
.word 0x49B00002
.word 0x49C00002
.word 0x49D00002
.word 0x49E00002
.word 0x49F00002 @ 32 MByte
.word 0x4A000002
.word 0x4A100002
.word 0x4A200002
.word 0x4A300002
.word 0x4A400002
.word 0x4A500002
.word 0x4A600002
.word 0x4A700002
.word 0x4A800002
.word 0x4A900002
.word 0x4AA00002
.word 0x4AB00002
.word 0x4AC00002
.word 0x4AD00002
.word 0x4AE00002
.word 0x4AF00002
.word 0x4B000002
.word 0x4B100002
.word 0x4B200002
.word 0x4B300002
.word 0x4B400002
.word 0x4B500002
.word 0x4B600002
.word 0x4B700002
.word 0x4B800002
.word 0x4B900002
.word 0x4BA00002
.word 0x4BB00002
.word 0x4BC00002
.word 0x4BD00002
.word 0x4BE00002
.word 0x4BF00002
.word 0x4C000002 @ 33 MByte
@// end at ( 0x5300 = 0x4000 + 0x4C0 *4 )
@.ALIGN 0x200 @// this should get us to 0x5400
.align 9
.word 0x0 @insert a word so the next align goes to 0x5600
@.ALIGN 0x200 @ (0x5600=0x4000+0x580*4)
.align 9
@// this should get us to 0x5600
.word 0x58000002 @ internal SRAM control registers
@.ALIGN 0x100 @ (0x5700=0x4000+0x5C0*4)
.align 8
@// this should get us to 0x5700
.word 0x5C00000A @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
@.ALIGN 0x1000 @// this should get us to 0x6000
.align 12
.word 0x0 @insert a word so the next align goes to 0x6800
@.ALIGN 0x800 @(0x6800=0x4000+0xA00*4)
.align 11
.word 0xA000000A @ SDRAM bank 0 (x=0,c=1,b=0 => Write-Through)
.word 0xA010000A
.word 0xA020000A
.word 0xA030000A
.word 0xA040000A
.word 0xA050000A
.word 0xA060000A
.word 0xA070000A
.word 0xA080000A
.word 0xA090000A
.word 0xA0A0000A
.word 0xA0B0000A
.word 0xA0C0000A
.word 0xA0D0000A
.word 0xA0E0000A
.word 0xA0F0000A
.word 0xA100000A
.word 0xA110000A
.word 0xA120000A
.word 0xA130000A
.word 0xA140000A
.word 0xA150000A
.word 0xA160000A
.word 0xA170000A
.word 0xA180000A
.word 0xA190000A
.word 0xA1A0000A
.word 0xA1B0000A
.word 0xA1C0000A
.word 0xA1D0000A
.word 0xA1E0000A
.word 0xA1F0000A @ 32 MByte
.word 0xA200000A
.word 0xA210000A
.word 0xA220000A
.word 0xA230000A
.word 0xA240000A
.word 0xA250000A
.word 0xA260000A
.word 0xA270000A
.word 0xA280000A
.word 0xA290000A
.word 0xA2A0000A
.word 0xA2B0000A
.word 0xA2C0000A
.word 0xA2D0000A
.word 0xA2E0000A
.word 0xA2F0000A
.word 0xA300000A
.word 0xA310000A
.word 0xA320000A
.word 0xA330000A
.word 0xA340000A
.word 0xA350000A
.word 0xA360000A
.word 0xA370000A
.word 0xA380000A
.word 0xA390000A
.word 0xA3A0000A
.word 0xA3B0000A
.word 0xA3C0000A
.word 0xA3D0000A
.word 0xA3E0000A
.word 0xA3F0000A @ 32 MByte
@ write-back table
@.ALIGN 0x4000
.align 14
.global MMUTableWB
MMUTableWB:
.word 0x0000000E @ ROM (x=0,c=1,b=1 => Write-Back)
.word 0x0010000E
.word 0x0020000E
.word 0x0030000E
.word 0x0040000E
.word 0x0050000E
.word 0x0060000E
.word 0x0070000E
.word 0x0080000E
.word 0x0090000E
.word 0x00A0000E
.word 0x00B0000E
.word 0x00C0000E
.word 0x00D0000E
.word 0x00E0000E
.word 0x00F0000E
.word 0x0100000E
.word 0x0110000E
.word 0x0120000E
.word 0x0130000E
.word 0x0140000E
.word 0x0150000E
.word 0x0160000E
.word 0x0170000E
.word 0x0180000E
.word 0x0190000E
.word 0x01A0000E
.word 0x01B0000E
.word 0x01C0000E
.word 0x01D0000E
.word 0x01E0000E
.word 0x01F0000E @ 32 MByte
@.ALIGN 0x100 @(0x4100=0x4000+0x040*4)
.align 8
.word 0x0400000E @ Flash (x=0,c=1,b=1 => Write-Back)
.word 0x0410000E
.word 0x0420000E
.word 0x0430000E
.word 0x0440000E
.word 0x0450000E
.word 0x0460000E
.word 0x0470000E
.word 0x0480000E
.word 0x0490000E
.word 0x04A0000E
.word 0x04B0000E
.word 0x04C0000E
.word 0x04D0000E
.word 0x04E0000E
.word 0x04F0000E
.word 0x0500000E
.word 0x0510000E
.word 0x0520000E
.word 0x0530000E
.word 0x0540000E
.word 0x0550000E
.word 0x0560000E
.word 0x0570000E
.word 0x0580000E
.word 0x0590000E
.word 0x05A0000E
.word 0x05B0000E
.word 0x05C0000E
.word 0x05D0000E
.word 0x05E0000E
.word 0x05F0000E @ 32 MByte
@.ALIGN 0x100 @(0x4200=0x4000+0x080*4)
.align 8
.word 0x08000002 @ Mainstone Board Regs (x=0,c=0,b=0 => I/O space)
@.ALIGN 0x80 @(0x4280=0x4000+0x0A0*4)
.align 7
.word 0x0A00000E @ nCS2 - 2M SRAM (x=0,c=1,b=1 => Write-Back)
.word 0x0A10000E @
@.ALIGN 0x80 @(0x4300=0x4000+0x0C0*4)
.align 7
.word 0x0 @ (nCS3 (x=0,c=0,b=0 => I/O space)
@.ALIGN 0x100 @(0x4400=0x4000+0x100*4)
.align 8
.word 0x10000002 @ nCS4 - 100BASE2 Ethernet (x=0,c=0,b=0 => I/O space)
.word 0x10100002
.word 0x10200002
.word 0x10300002
@.ALIGN 0x100 @(0x4500=0x4000+0x140*4)
.align 8
.word 0x14000002 @ nCS5 - Expansion Connector (x=0,c=0,b=0 => I/O space)
.word 0x14100002
.word 0x14200002
.word 0x14300002
@.ALIGN 0x400 @(0x4800=0x4000+0x200*4)
.align 10
.word 0x20000002 @ PCMCIA/CF Slot 0 (x=0,c=0,b=0 => I/O space)
.word 0x20100002
.word 0x20200002
.word 0x20300002 @ REALLY SHOULD BE 256 MB!!!!!!
@.ALIGN 0x400 @(0x4C00=0x4000+0x300*4)
.align 10
.word 0x30000002 @ PCMCIA/CF Slot 1 (x=0,c=0,b=0 => I/O space)
.word 0x30100002
.word 0x30200002
.word 0x30300002 @ REALLY SHOULD BE 256 MB!!!!!!
@.ALIGN 0x400 @(0x5000=0x4000+0x400*4)
.align 10
.word 0x40000002 @ Internal Registers (periphs) (x=0,c=0,b=0 => I/O space)
.word 0x40100002
.word 0x40200002
.word 0x40300002
.word 0x40400002
.word 0x40500002
.word 0x40600002
.word 0x40700002
.word 0x40800002
.word 0x40900002
.word 0x40A00002
.word 0x40B00002
.word 0x40C00002
.word 0x40D00002
.word 0x40E00002
.word 0x40F00002
.word 0x41000002
.word 0x41100002
.word 0x41200002
.word 0x41300002
.word 0x41400002
.word 0x41500002
.word 0x41600002
.word 0x41700002
.word 0x41800002
.word 0x41900002
.word 0x41A00002
.word 0x41B00002
.word 0x41C00002
.word 0x41D00002
.word 0x41E00002
.word 0x41F00002 @ 32 MByte
.word 0x42000002
.word 0x42100002
.word 0x42200002
.word 0x42300002
.word 0x42400002
.word 0x42500002
.word 0x42600002
.word 0x42700002
.word 0x42800002
.word 0x42900002
.word 0x42A00002
.word 0x42B00002
.word 0x42C00002
.word 0x42D00002
.word 0x42E00002
.word 0x42F00002
.word 0x43000002
.word 0x43100002
.word 0x43200002
.word 0x43300002
.word 0x43400002
.word 0x43500002
.word 0x43600002
.word 0x43700002
.word 0x43800002
.word 0x43900002
.word 0x43A00002
.word 0x43B00002
.word 0x43C00002
.word 0x43D00002
.word 0x43E00002
.word 0x43F00002 @ 32 MByte
.word 0x44000002 @ Internal Registers (LCD) (x=0,c=0,b=0 => I/O space)
.word 0x44100002
.word 0x44200002
.word 0x44300002
.word 0x44400002
.word 0x44500002
.word 0x44600002
.word 0x44700002
.word 0x44800002
.word 0x44900002
.word 0x44A00002
.word 0x44B00002
.word 0x44C00002
.word 0x44D00002
.word 0x44E00002
.word 0x44F00002
.word 0x45000002
.word 0x45100002
.word 0x45200002
.word 0x45300002
.word 0x45400002
.word 0x45500002
.word 0x45600002
.word 0x45700002
.word 0x45800002
.word 0x45900002
.word 0x45A00002
.word 0x45B00002
.word 0x45C00002
.word 0x45D00002
.word 0x45E00002
.word 0x45F00002 @ 32 MByte
.word 0x46000002
.word 0x46100002
.word 0x46200002
.word 0x46300002
.word 0x46400002
.word 0x46500002
.word 0x46600002
.word 0x46700002
.word 0x46800002
.word 0x46900002
.word 0x46A00002
.word 0x46B00002
.word 0x46C00002
.word 0x46D00002
.word 0x46E00002
.word 0x46F00002
.word 0x47000002
.word 0x47100002
.word 0x47200002
.word 0x47300002
.word 0x47400002
.word 0x47500002
.word 0x47600002
.word 0x47700002
.word 0x47800002
.word 0x47900002
.word 0x47A00002
.word 0x47B00002
.word 0x47C00002
.word 0x47D00002
.word 0x47E00002
.word 0x47F00002 @ 32 MByte
.word 0x48000002 @ Internal Registers (mem ctrl) (x=0,c=0,b=0 => I/O space)
.word 0x48100002
.word 0x48200002
.word 0x48300002
.word 0x48400002
.word 0x48500002
.word 0x48600002
.word 0x48700002
.word 0x48800002
.word 0x48900002
.word 0x48A00002
.word 0x48B00002
.word 0x48C00002
.word 0x48D00002
.word 0x48E00002
.word 0x48F00002
.word 0x49000002
.word 0x49100002
.word 0x49200002
.word 0x49300002
.word 0x49400002
.word 0x49500002
.word 0x49600002
.word 0x49700002
.word 0x49800002
.word 0x49900002
.word 0x49A00002
.word 0x49B00002
.word 0x49C00002
.word 0x49D00002
.word 0x49E00002
.word 0x49F00002 @ 32 MByte
.word 0x4A000002
.word 0x4A100002
.word 0x4A200002
.word 0x4A300002
.word 0x4A400002
.word 0x4A500002
.word 0x4A600002
.word 0x4A700002
.word 0x4A800002
.word 0x4A900002
.word 0x4AA00002
.word 0x4AB00002
.word 0x4AC00002
.word 0x4AD00002
.word 0x4AE00002
.word 0x4AF00002
.word 0x4B000002
.word 0x4B100002
.word 0x4B200002
.word 0x4B300002
.word 0x4B400002
.word 0x4B500002
.word 0x4B600002
.word 0x4B700002
.word 0x4B800002
.word 0x4B900002
.word 0x4BA00002
.word 0x4BB00002
.word 0x4BC00002
.word 0x4BD00002
.word 0x4BE00002
.word 0x4BF00002
.word 0x4C000002 @ 33 MByte
@// end at ( 0x5300 = 0x4000 + 0x4C0 *4 )
@.ALIGN 0x200 @// this should get us to 0x5400
.align 9
.word 0x0 @insert a word so the next align goes to 0x5600
@.ALIGN 0x200 @ (0x5600=0x4000+0x580*4)
.align 9
@// this should get us to 0x5600
.word 0x58000002 @ internal SRAM control registers
@.ALIGN 0x100 @ (0x5700=0x4000+0x5C0*4)
.align 8
@// this should get us to 0x5700
.word 0x5C00000E @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
@.ALIGN 0x1000 @// this should get us to 0x6000
.align 12
.word 0x0 @insert a word so the next align goes to 0x6800
@.ALIGN 0x800 @(0x6800=0x4000+0xA00*4)
.align 11
.word 0xA000000A @ SDRAM bank 0 1M Write-Through for LCD Frame Buffer
.word 0xA010000E @ SDRAM bank 0 (x=0,c=1,b=0 => Write-Back)
.word 0xA020000E
.word 0xA030000E
.word 0xA040000E
.word 0xA050000E
.word 0xA060000E
.word 0xA070000E
.word 0xA080000E
.word 0xA090000E
.word 0xA0A0000E
.word 0xA0B0000E
.word 0xA0C0000E
.word 0xA0D0000E
.word 0xA0E0000E
.word 0xA0F0000E
.word 0xA100000E
.word 0xA110000E
.word 0xA120000E
.word 0xA130000E
.word 0xA140000E
.word 0xA150000E
.word 0xA160000E
.word 0xA170000E
.word 0xA180000E
.word 0xA190000E
.word 0xA1A0000E
.word 0xA1B0000E
.word 0xA1C0000E
.word 0xA1D0000E
.word 0xA1E0000E
.word 0xA1F0000E @ 32 MByte
.word 0xA200000E
.word 0xA210000E
.word 0xA220000E
.word 0xA230000E
.word 0xA240000E
.word 0xA250000E
.word 0xA260000E
.word 0xA270000E
.word 0xA280000E
.word 0xA290000E
.word 0xA2A0000E
.word 0xA2B0000E
.word 0xA2C0000E
.word 0xA2D0000E
.word 0xA2E0000E
.word 0xA2F0000E
.word 0xA300000E
.word 0xA310000E
.word 0xA320000E
.word 0xA330000E
.word 0xA340000E
.word 0xA350000E
.word 0xA360000E
.word 0xA370000E
.word 0xA380000E
.word 0xA390000E
.word 0xA3A0000E
.word 0xA3B0000E
.word 0xA3C0000E
.word 0xA3D0000E
.word 0xA3E0000E
.word 0xA3F0000E @ 32 MByte
.END
--- NEW FILE: util.s ---
.macro CPWAIT Rd
MRC P15, 0, \Rd, C2, C0, 0 @ arbitrary read of CP15 into register Rd
MOV \Rd, \Rd @ wait for it (foward dependency)
SUB PC, PC, #4 @ branch to next instruction
.endm
.extern MMUTableWT
.extern MMUTableWB
.equ MEMORY_CONFIG_BASE,(0x48000000)
.equ FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode
@.equ FLASH_SYNC_value, (0x25C2<<1) @ Value to set flash into burst 8 sync mode
.equ FLASH_WRITE,(0x0060) @ Code for writing to flash
.equ FLASH_READSTATUS,(0x0070) @ Code for reading status
.equ FLASH_WCONF,(0x0003) @ Code to confirm write to flash
.equ FLASH_READ,(0x00FF) @ Code to place flash in read mode
.equ SXCNFG_sync_value,(0x7011) @ SXCNFG value for burst16 sync flash operation
@ .equ SXCNFG_sync_value,(0x6011) @ SXCNFG value for burst8 sync flash operation
.equ SXCNFG_offset,(0x1c)
initSyncFlash:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
.global initSyncFlash
ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base
ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register
ldr r3, =FLASH_WRITE @ Write to flash instruction
ldr r4, =FLASH_WCONF @ Write to flash confirm instruction
ldr r5, =FLASH_READ @ Load "read array" mode command
ldr r6, =0x0 @ Boot ROM Flash Base address
ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now
b goSyncFlash
@align on cache line so that we fetch the next 8 instructions...
.align 5
goSyncFlash:
@ Now program everything into the Flash and SXCNFG registers
str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register
strh r3, [r2] @ Yes, the data is on the address bus!
strh r4, [r2] @ Confirm the write to the RCR
strh r5, [r6] @ Place flash back in read mode
ldrh r5, [r6] @ Create a data dependency stall to guarantee write
nop @ go to the end of the cache line
nop
nop
@ Return to caller
mov PC, LR
readFlashStatusRegister:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
.global readFlashStatusRegister
ldr r1, =FLASH_READSTATUS @ read status instruction
ldr r2, =FLASH_READ @ Load "read array" mode command
ldr r3, =0x0 @ Boot ROM Flash Base address
b goReadStatus
@align on cache line so that we fetch the next 8 instructions...
.align 5
goReadStatus:
@ Now program everything into the Flash and SXCNFG registers
strh r1, [r3] @ Yes, the data is on the address bus!
ldrh r0, [r3] @ Confirm the write to the RCR
strh r2, [r3] @ Place flash back in read mode
ldrh r2, [r3] @ Create a data dependency stall to guarantee write
nop @ go to the end of the cache line
nop
nop
nop
@ Return to caller
mov PC, LR
readFlashCFI:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
.global readFlashCFI
ldr r1, =0x98 @ read status instruction
ldr r2, =FLASH_READ @ Load "read array" mode command
ldr r3, =0x0 @ Boot ROM Flash Base address
ldr r4, =0x20 @ Boot ROM Flash Base address
b goReadCFI
@align on cache line so that we fetch the next 8 instructions...
.align 5
goReadCFI:
@ Now program everything into the Flash and SXCNFG registers
strh r1, [r3] @ Yes, the data is on the address bus!
ldrh r0, [r4] @ read into r0
strh r2, [r3] @ Place flash back in read mode
ldrh r2, [r3] @ Create a data dependency stall to guarantee write
nop @ go to the end of the cache line
nop
nop
nop
@ Return to caller
mov PC, LR
@assembly routine to init our MMU....just for kicks align on an icache line ; o)
.align 5
initMMU:
.global initMMU
MRC P15,0,R0,C3,C0,0 @read the domain register into R0
ORR R0, R0, #0xFF @make sure that we completely enable domain 0
MCR P15,0,R0,C3,C0,0 @write the domain register
CPWAIT R0 @be anal and make sure it completes
_WritePageTable:
@time to setup the page table base register
LDR R0, =MMUTableWT @move the table we want into R0
MCR P15, 0, R0, C2, C0 @save it
CPWAIT R0 @wait it
_EnablePageTable:
@time to enable the MMU!
MRC P15,0,R0,C1,C0,0 @get CP15 register 1
ORR R0, R0, #0x1 @set the MMU enable bit
MCR P15,0,R0,C1,C0,0 @save it
CPWAIT R0 @wait it
@icache section
@globally unlock the icache
MCR P15, 0, R0, C9, C1, 1
CPWAIT R0
@globally unlock the itlb
MCR P15, 0, R0, C10, C4, 1
CPWAIT R0
@invalidate just the icache and BTB....write to P15 C7, C5, 0
MCR P15, 0, R0, C7, C5, 0
CPWAIT R0
@invalidate the iTLB...write to P15 C8, C5, 0
MCR P15, 0, R0, c8, c5, 0 @save it
CPWAIT R0 @wait it
@Enable instruction cache
MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
ORR R0, R0, #0x1000 @set the icache bit
MCR P15, 0, R0, C1, C0, 0 @wait it
CPWAIT R0
@enable the BTB
MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
ORR R0, R0, #0x800 @set the btb enable bit
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
@dcache section
@globally unlock the dtlb
MCR P15, 0, R0, c10, c8, 1
CPWAIT R0
@globally unlock the dcache
MCR P15, 0, R0, C9, c2, 1
CPWAIT R0
@first invalidate dcache and mini-dcache
MCR P15, 0, R0, C7, C6, 0
CPWAIT R0
@invalidate the dTLB...write to P15 C8, C6, 0
MCR P15, 0, R0, C8, C6, 0 @save it
CPWAIT R0 @wait it
@ now, enable data cache
MCR P15, 0, R0, C7, C10, 4 @drain write buffer
MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
ORR R0, R0, #0x4 @set the dcache enable bit
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
MOV PC, LR
Index: HPLInit.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/HPLInit.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** HPLInit.nc 27 May 2005 17:52:28 -0000 1.3
--- HPLInit.nc 4 Aug 2005 22:34:25 -0000 1.4
***************
*** 80,85 ****
implementation
{
! command result_t init() {
CKEN = (CKEN22_MEMC | CKEN20_IMEM | CKEN15_PMI2C | CKEN9_OST);
--- 80,90 ----
implementation
{
+ #define FAKEADDR(_x) ((uint32_t *)(_x))
! extern void initSyncFlash() __attribute__ ((C,spontaneous));
! extern void initMMU() __attribute__ ((C,spontaneous));
!
! command result_t init() {
! uint32_t temp;
CKEN = (CKEN22_MEMC | CKEN20_IMEM | CKEN15_PMI2C | CKEN9_OST);
***************
*** 89,96 ****
TOSH_SET_PIN_DIRECTIONS();
- #if 0
- // Place PXA27X into 13M w/ PPLL enabled
- CCCR = (CCCR_CPDIS | CCCR_PLL_EARLY_EN);
asm volatile (
"mcr p14,0,%0,c6,c0,0\n\t"
--- 94,118 ----
TOSH_SET_PIN_DIRECTIONS();
+
+ #if 1
+ // Place PXA27X into 13M w/ PPLL enabled...other bits are ignored...but might be useful later
+ CCCR = (CCCR_CPDIS | CCCR_L(8) | CCCR_2N(2) | CCCR_A);
+ /*********
+ Don't early enable PLL here. Page 3-96 of manual says
+ "Write to this bit only when the processor is in 13M mode and the core PLL has
+ been disabled by setting CPDIS. In normal run mode, writing to this bit causes
+ unpredictable results"
+ *******/
+ //PLACE PXA27X into 104MHz mode....valid bus settings
+
+ /*
+ CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ;
+ asm volatile (
+ "mcr p14,0,%0,c6,c0,0\n\t"
+ :
+ : "r" (0xb)
+ );
+ */
asm volatile (
"mcr p14,0,%0,c6,c0,0\n\t"
***************
*** 99,121 ****
);
#endif
! #if 0
! PVCR = 0;
! PCMD(0) = (PCMD_MBC | PCMD_LC | ((1023 >> 8) & 0xFF));
! PCMD(1) = (PCMD_LC | ((1023) & 0xFF));
! PCFR = PCFR_PI2C_EN;
! asm volatile (
! "mcr p14,0,%0,c6,c0,0\n\t"
! :
! : "r" (0x8)
! );
!
!
! #endif
- return SUCCESS;
}
-
-
}
--- 121,162 ----
);
#endif
! //initialize the MMU...call assembly routine
! initMMU();
+ #if 1
+ //initialize the memory controller
+ //PXA27x MemConttroller 1st tier initialization.See 6.4.10 for details
+ SA1110 = SA1110_SXSTACK(1);
+ MSC0 = MSC0 | (1<<3) | (1<<15) | 2 ;
+ MSC1 = MSC1 | (1<<3);
+ MSC2 = MSC2 | (1<<3);
+
+ //PXA27x MemController 2nd tier initialization.See 6.4.10 for details
+ MECR =0; //no PC Card is present and 1 card slot
+ /*
+ MCMEM0;
+ MCMEM1;
+ MCATT0;
+ MCATT1;;
+ MCIO0;
+ MCIO1;
+ */
+
+ //PXA27x MemController 3rd tier initialization.See 6.4.10 for details
+ //FLYCNFG
+
+ //PXA27x MemController 4th tier initialization.See 6.4.10 for details
+ MDCNFG = 0x0B002BCC; //should be 0x0B002BCD, but we want it disabled.
+ //MDREFR;
+
+ //PXA27x MemController 5th tier initialization.See 6.4.10 for details
+ //SXCNFG = SXCNFG_SXEN0 | SXCNFG_SXCL0(4) | SXCNFG_SXTP0(3);
+ initSyncFlash();
+
+ #endif
+
+ return SUCCESS;
}
}
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AccelDriverM.nc, 1.3, 1.4 Mic.h, 1.1, 1.2 MicDriverC.nc, 1.2,
1.3 MicDriverM.nc, 1.2, 1.3 PhotoDriverM.nc, 1.2, 1.3
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