[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2
HPLCC2420C.nc, 1.4, 1.5 HPLCC2420M.nc, 1.4, 1.5
Robbie Adler
radler at users.sourceforge.net
Thu Aug 18 15:34:03 PDT 2005
Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv19550
Modified Files:
HPLCC2420C.nc HPLCC2420M.nc
Log Message:
updated low level radio interface component to support the new DMA programming model. The radio now works correctly with the MMU, caches, and 13M mode
Index: HPLCC2420C.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLCC2420C.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HPLCC2420C.nc 14 May 2005 18:53:32 -0000 1.4
--- HPLCC2420C.nc 18 Aug 2005 22:34:00 -0000 1.5
***************
*** 56,60 ****
implementation
{
! components HPLCC2420M, PXA27XGPIOIntC, PXA27XInterruptM;
--- 56,60 ----
implementation
{
! components HPLCC2420M, PXA27XGPIOIntC, PXA27XInterruptM, PXA27XDMAC;
***************
*** 75,79 ****
HPLCC2420M.SFD_GPIOInt -> PXA27XGPIOIntC.PXA27XGPIOInt[CC_SFD_PIN];
! HPLCC2420M.DMAInterrupt -> PXA27XInterruptM.PXA27XIrq[PPID_DMAC];
!
}
--- 75,80 ----
HPLCC2420M.SFD_GPIOInt -> PXA27XGPIOIntC.PXA27XGPIOInt[CC_SFD_PIN];
! HPLCC2420M.RxDMAChannel -> PXA27XDMAC.PXA27XDMAChannel[unique("DMAChannel")];
! HPLCC2420M.TxDMAChannel -> PXA27XDMAC.PXA27XDMAChannel[unique("DMAChannel")];
! HPLCC2420M.DMAControl -> PXA27XDMAC.StdControl;
}
Index: HPLCC2420M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLCC2420M.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HPLCC2420M.nc 9 Mar 2005 22:42:59 -0000 1.4
--- HPLCC2420M.nc 18 Aug 2005 22:34:00 -0000 1.5
***************
*** 31,35 ****
/*
*
! * Authors: Phil Buonadonna
* Date last modified: $Revision$
*
--- 31,35 ----
/*
*
! * Authors: Phil Buonadonna, Robbie Adler
* Date last modified: $Revision$
*
***************
*** 38,41 ****
--- 38,42 ----
/**
* @author Phil Buonadonna
+ * @author Robbie Adler
*/
***************
*** 53,61 ****
uses {
interface StdControl as GPIOControl;
interface PXA27XGPIOInt as FIFOP_GPIOInt;
interface PXA27XGPIOInt as FIFO_GPIOInt;
interface PXA27XGPIOInt as CCA_GPIOInt;
interface PXA27XGPIOInt as SFD_GPIOInt;
! interface PXA27XInterrupt as DMAInterrupt;
}
}
--- 54,64 ----
uses {
interface StdControl as GPIOControl;
+ interface StdControl as DMAControl;
interface PXA27XGPIOInt as FIFOP_GPIOInt;
interface PXA27XGPIOInt as FIFO_GPIOInt;
interface PXA27XGPIOInt as CCA_GPIOInt;
interface PXA27XGPIOInt as SFD_GPIOInt;
! interface PXA27XDMAChannel as RxDMAChannel;
! interface PXA27XDMAChannel as TxDMAChannel;
}
}
***************
*** 64,83 ****
enum {
- HPLCC2420_STATE_IDLE,
- HPLCC2420_STATE_CMD,
- HPLCC2420_STATE_WRITE,
- HPLCC2420_STATE_READ,
- HPLCC2420_STATE_RAMWR,
- HPLCC2420_STATE_RAMRD,
- HPLCC2420_STATE_FIFORD,
- HPLCC2420_STATE_FIFOWR
- };
-
- enum {
PXA27X_SSP_FIFOMAXLEN = 13
};
! uint8_t gIFState;
!
norace uint8_t* rxbuf;
norace uint8_t* txbuf;
--- 67,75 ----
enum {
PXA27X_SSP_FIFOMAXLEN = 13
};
! uint8_t gbDMAChannelInitDone;
! bool gbIgnoreTxDMA;
norace uint8_t* rxbuf;
norace uint8_t* txbuf;
***************
*** 94,98 ****
command result_t StdControl.init() {
- atomic gIFState = HPLCC2420_STATE_IDLE;
// Set the appropriate GPIO bits
--- 86,89 ----
***************
*** 106,116 ****
_GPIO_setaltfn(SSP3_RXD,SSP3_RXD_ALTFN);
//_GPIO_setaltfn(SSP3_SFRM,SSP3_SFRM_ALTFN);
-
- DRCMR(66) = ((1 << 7) | (0 & 0x1f)); // SSP3 Rx = DMA CH0
- DRCMR(67) = ((1 << 7) | (1 & 0x1f)); // SSP3 Tx = DMA CH1
- DALGN = ((1 << 1) | (1 << 0)); // Align Channel 0 and 1 for byte operations
- call DMAInterrupt.allocate();
call GPIOControl.init();
return SUCCESS;
--- 97,124 ----
_GPIO_setaltfn(SSP3_RXD,SSP3_RXD_ALTFN);
//_GPIO_setaltfn(SSP3_SFRM,SSP3_SFRM_ALTFN);
+ atomic gbDMAChannelInitDone = 2;
+
+ call RxDMAChannel.requestChannel(DMAID_SSP3_RX,DMA_Priority1, TRUE);
+ call TxDMAChannel.requestChannel(DMAID_SSP3_TX,DMA_Priority1, TRUE);
+
+ call DMAControl.init();
call GPIOControl.init();
+
+ call TxDMAChannel.setTargetAddr(0x41900010);
+ call TxDMAChannel.enableSourceAddrIncrement(TRUE);
+ call TxDMAChannel.enableTargetAddrIncrement(FALSE);
+ call TxDMAChannel.enableSourceFlowControl(FALSE);
+ call TxDMAChannel.enableTargetFlowControl(TRUE);
+ call TxDMAChannel.setMaxBurstSize(DMA_8ByteBurst);
+ call TxDMAChannel.setTransferWidth(DMA_1ByteWidth);
+
+ call RxDMAChannel.setSourceAddr(0x41900010);
+ call RxDMAChannel.enableSourceAddrIncrement(FALSE);
+ call RxDMAChannel.enableTargetAddrIncrement(TRUE);
+ call RxDMAChannel.enableSourceFlowControl(TRUE);
+ call RxDMAChannel.enableTargetFlowControl(FALSE);
+ call RxDMAChannel.setMaxBurstSize(DMA_8ByteBurst);
+ call RxDMAChannel.setTransferWidth(DMA_1ByteWidth);
return SUCCESS;
***************
*** 123,134 ****
// Serial Clock Rate = 6.5 MHz, Frame Format = SPI, Data Size = 8-bit
- SSCR0_3 = (SSCR0_SCR(1) | SSCR0_FRF(0) | SSCR0_DSS(0x7));
// RX&TX
! SSCR1_3 = (SSCR1_TRAIL | SSCR1_TSRE | SSCR1_RSRE | SSCR1_RFT(8) | SSCR1_TFT(1));
! SSTO_3 = 0;
!
! SSCR0_3 |= SSCR0_SSE; // Enable SSP1 port
! call DMAInterrupt.enable();
call GPIOControl.start();
return SUCCESS;
--- 131,141 ----
// Serial Clock Rate = 6.5 MHz, Frame Format = SPI, Data Size = 8-bit
// RX&TX
! SSCR1_3 = (SSCR1_TRAIL | SSCR1_RFT(8) | SSCR1_TFT(8));
! SSTO_3 = (96*8);
! SSCR0_3 = (SSCR0_SCR(1) | SSCR0_FRF(0) | SSCR0_DSS(0x7) | SSCR0_SSE);
!
! call DMAControl.start();
call GPIOControl.start();
return SUCCESS;
***************
*** 137,141 ****
command result_t StdControl.stop() {
! call DMAInterrupt.disable();
call GPIOControl.stop();
--- 144,148 ----
command result_t StdControl.stop() {
! call DMAControl.start();
call GPIOControl.stop();
***************
*** 193,196 ****
--- 200,204 ----
status = SSDR_3;
+ //drain the fifo since we got a couple of extra samples in there due to writes>reads
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
***************
*** 209,212 ****
--- 217,221 ----
TOSH_CLR_CC_CSN_PIN();
+ //drain the fifo so that we're in the right state
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
***************
*** 254,257 ****
--- 263,267 ----
SSDR_3 = (((rxramaddr >> 1) & 0xC0) | 0x20);
+ //this effectively allows us to read in the data
for (i = 0; i < rxramlen; i++) {
SSDR_3 = 0;
***************
*** 261,265 ****
TOSH_SET_CC_CSN_PIN();
!
tmp = SSDR_3;
tmp = SSDR_3;
--- 271,275 ----
TOSH_SET_CC_CSN_PIN();
!
tmp = SSDR_3;
tmp = SSDR_3;
***************
*** 325,329 ****
*/
async command result_t HPLCC2420FIFO.readRXFIFO(uint8_t length, uint8_t *data) {
! uint8_t tmp;
uint8_t pktlen;
result_t result = SUCCESS;
--- 335,339 ----
*/
async command result_t HPLCC2420FIFO.readRXFIFO(uint8_t length, uint8_t *data) {
! uint8_t tmp, OkToUse;
uint8_t pktlen;
result_t result = SUCCESS;
***************
*** 331,348 ****
atomic {
rxbuf = data;
! gIFState = HPLCC2420_STATE_FIFORD;
}
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
TOSH_CLR_CC_CSN_PIN();
!
! DCSR(0) = (DCSR_NODESCFETCH);
! DSADR(0) = ((uint32_t) &SSDR_3);
! DTADR(0) = (uint32_t) &rxbuf[1];
!
! DCSR(1) = (DCSR_NODESCFETCH);
! DSADR(1) = (uint32_t) &txdummy;
! DTADR(1) = ((uint32_t) &SSDR_3);
!
SSDR_3 = (CC2420_RXFIFO | 0x40);
SSDR_3 = 0;
--- 341,351 ----
atomic {
rxbuf = data;
! OkToUse = gbDMAChannelInitDone;
}
+ //flush the receive fifo
while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
TOSH_CLR_CC_CSN_PIN();
!
SSDR_3 = (CC2420_RXFIFO | 0x40);
SSDR_3 = 0;
***************
*** 355,378 ****
pktlen++;
! if (pktlen > 0) {
! //rxbuf = data;
!
rxlen = (pktlen < length) ? pktlen : length;
! DCMD(0) = (DCMD_INCTRGADDR | DCMD_FLOWSRC | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_LENGTH(rxlen-1));
! DCMD(1) = (DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_LENGTH(rxlen-1));
! DCSR(0) = (DCSR_RUN | DCSR_NODESCFETCH | DCSR_STOPIRQEN);
! DCSR(1) = (DCSR_RUN | DCSR_NODESCFETCH);
! SSTO_3 = (96*8);
}
else {
TOSH_SET_CC_CSN_PIN();
- atomic gIFState = HPLCC2420_STATE_IDLE;
result = FAIL;
}
return result;
-
}
--- 358,389 ----
pktlen++;
! if (pktlen > 0 && (OkToUse == 0)) {
!
rxlen = (pktlen < length) ? pktlen : length;
!
! call RxDMAChannel.setTargetAddr((uint32_t)(&rxbuf[1]));
! call RxDMAChannel.setTransferLength(rxlen-1);
! SSCR1_3 |= SSCR1_RSRE;
! call RxDMAChannel.run();
!
! atomic{
! gbIgnoreTxDMA = TRUE;
! }
! //just want to send something
! call TxDMAChannel.setSourceAddr((uint32_t)txbuf);
! call TxDMAChannel.enableSourceAddrIncrement(FALSE);
! call TxDMAChannel.setTransferLength(rxlen-1);
! //request a permanent channel
+ SSCR1_3 |= SSCR1_TSRE;
+ call TxDMAChannel.run();
}
else {
TOSH_SET_CC_CSN_PIN();
result = FAIL;
}
return result;
}
***************
*** 390,415 ****
*/
async command result_t HPLCC2420FIFO.writeTXFIFO(uint8_t length, uint8_t *data) {
!
atomic {
txbuf = data;
txlen = length;
! gIFState = HPLCC2420_STATE_FIFOWR;
}
-
- TOSH_CLR_CC_CSN_PIN();
-
- DCSR(1) = (DCSR_NODESCFETCH);
- DSADR(1) = (uint32_t) txbuf;
- DTADR(1) = ((uint32_t) &SSDR_3);
- DCMD(1) = (DCMD_INCSRCADDR | DCMD_FLOWTRG | DCMD_BURST8 | DCMD_WIDTH1 | DCMD_LENGTH(txlen));
-
- SSDR_3 = (CC2420_TXFIFO);
-
- DCSR(1) = (DCSR_RUN | DCSR_NODESCFETCH | DCSR_STOPIRQEN);
-
- return SUCCESS;
}
-
async command result_t InterruptFIFOP.startWait(bool low_to_high){
// set FIFOP to a rising edge interrupt
--- 401,435 ----
*/
async command result_t HPLCC2420FIFO.writeTXFIFO(uint8_t length, uint8_t *data) {
!
! uint8_t OkToUse;
atomic {
txbuf = data;
txlen = length;
! OkToUse = gbDMAChannelInitDone;
! }
! if(OkToUse == 0){
!
! call TxDMAChannel.setSourceAddr((uint32_t)data);
! call TxDMAChannel.enableSourceAddrIncrement(TRUE);
! call TxDMAChannel.setTransferLength(length);
!
! //request a permanent channel
! atomic{
! gbIgnoreTxDMA = FALSE;
! }
! TOSH_CLR_CC_CSN_PIN();
!
! SSDR_3 = (CC2420_TXFIFO);
! while (SSSR_3 & SSSR_BSY);
!
! SSCR1_3 |= SSCR1_TSRE;
! call TxDMAChannel.run();
! return SUCCESS;
! }
! else{
! return FAIL;
}
}
async command result_t InterruptFIFOP.startWait(bool low_to_high){
// set FIFOP to a rising edge interrupt
***************
*** 529,533 ****
call InterruptCCA.disable();
}
-
return;
}
--- 549,552 ----
***************
*** 544,586 ****
}
! async event void DMAInterrupt.fired() {
! uint8_t i,tmp;
!
! switch (gIFState) {
!
! case HPLCC2420_STATE_IDLE:
! break;
!
! case HPLCC2420_STATE_FIFORD:
! TOSH_SET_CC_CSN_PIN();
!
! SSTO_3 = 0;
! SSSR_3 |= (SSSR_TINT);
!
! gIFState = HPLCC2420_STATE_IDLE;
! post signalRXFIFO();
! break;
!
! case HPLCC2420_STATE_FIFOWR:
!
// Drain the RXFIFO
! for (i = 0; i < 17; i++) {
tmp = SSDR_3;
}
TOSH_SET_CC_CSN_PIN();
!
! gIFState = HPLCC2420_STATE_IDLE;
post signalTXFIFO();
- break;
-
- default:
- break;
-
}
! // Clear the interrupting conditions.
! DCSR(0) = (DCSR_NODESCFETCH | DCSR_EORINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
! DCSR(1) = (DCSR_NODESCFETCH | DCSR_EORINTR | DCSR_STARTINTR | DCSR_BUSERRINTR);
! }
!
default async event result_t InterruptFIFOP.fired() {
return FAIL;
--- 563,604 ----
}
! event result_t RxDMAChannel.requestChannelDone(){
! atomic {gbDMAChannelInitDone -= 1;}
! return SUCCESS;
! }
!
! async event void RxDMAChannel.Interrupt(){
! //turn off things and post a task to signal that we're done
! TOSH_SET_CC_CSN_PIN();
!
! SSCR1_3 &= ~SSCR1_RSRE;
! post signalRXFIFO();
! return;
! }
!
! event result_t TxDMAChannel.requestChannelDone(){
! atomic {gbDMAChannelInitDone -= 1;}
! return SUCCESS;
! }
!
! async event void TxDMAChannel.Interrupt(){
! uint8_t tmp, localIgnoreTxDMA;
! atomic{
! localIgnoreTxDMA = gbIgnoreTxDMA;
! }
! if(localIgnoreTxDMA == FALSE){
! SSCR1_3 &= ~SSCR1_TSRE;
// Drain the RXFIFO
! while(SSSR_3 & SSSR_RNE){
tmp = SSDR_3;
}
TOSH_SET_CC_CSN_PIN();
!
post signalTXFIFO();
}
! return;
! }
!
!
default async event result_t InterruptFIFOP.fired() {
return FAIL;
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