[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
HPLInit.nc, 1.4, 1.5 mmu_table.s, 1.1, 1.2 util.s, 1.1, 1.2
Robbie Adler
radler at users.sourceforge.net
Thu Aug 18 16:05:41 PDT 2005
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1.1 PXA27XHPLDMAM.nc, NONE, 1.1 PXA27XDMAC.nc, 1.1,
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Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv26300
Modified Files:
HPLInit.nc mmu_table.s util.s
Log Message:
restructured and cleanup MMU init code a little bit. Updated pagetable to make internal SRAM non-cacheable non-bufferable due to DMA
Index: HPLInit.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/HPLInit.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HPLInit.nc 4 Aug 2005 22:34:25 -0000 1.4
--- HPLInit.nc 18 Aug 2005 23:05:38 -0000 1.5
***************
*** 73,76 ****
--- 73,77 ----
// create a separate component
+ includes GlobalUtil;
module HPLInit {
***************
*** 80,118 ****
implementation
{
! #define FAKEADDR(_x) ((uint32_t *)(_x))
extern void initSyncFlash() __attribute__ ((C,spontaneous));
extern void initMMU() __attribute__ ((C,spontaneous));
! command result_t init() {
! uint32_t temp;
!
CKEN = (CKEN22_MEMC | CKEN20_IMEM | CKEN15_PMI2C | CKEN9_OST);
OSCC = (OSCC_OON);
!
while ((OSCC & OSCC_OOK) == 0);
-
- TOSH_SET_PIN_DIRECTIONS();
#if 1
- // Place PXA27X into 13M w/ PPLL enabled...other bits are ignored...but might be useful later
- CCCR = (CCCR_CPDIS | CCCR_L(8) | CCCR_2N(2) | CCCR_A);
- /*********
- Don't early enable PLL here. Page 3-96 of manual says
- "Write to this bit only when the processor is in 13M mode and the core PLL has
- been disabled by setting CPDIS. In normal run mode, writing to this bit causes
- unpredictable results"
- *******/
//PLACE PXA27X into 104MHz mode....valid bus settings
! /*
! CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ;
! asm volatile (
! "mcr p14,0,%0,c6,c0,0\n\t"
! :
! : "r" (0xb)
! );
! */
!
asm volatile (
"mcr p14,0,%0,c6,c0,0\n\t"
--- 81,159 ----
implementation
{
! result_t pushqueue(queue_t *queue, uint32_t val) __attribute__((C,spontaneous)){
! //check to see if there is room in the queue
! uint16_t availableslots = (queue->head <= queue->tail) ? queue->size - queue->tail + queue->head: queue->head - queue->tail;
! //available entries in the queue is really size-1 since we need to guard against aliasing
! if(availableslots > 1 ){
! queue->entries[queue->tail] = val;
! queue->tail++;
! if(queue->tail >= queue->size){
! queue->tail = 0;
! }
! return SUCCESS;
! }
! else{
! return FAIL;
! }
! }
!
! result_t popqueue(queue_t *queue, uint32_t *val)__attribute__((C,spontaneous)){
! if(queue->head != queue->tail){
! *val = queue->entries[queue->head];
! queue->head++;
! if(queue->head >= queue->size){
! queue->head = 0;
! }
! return SUCCESS;
! }
! else{
! *val = 0;
! //queue is empty
! return FAIL;
! }
! }
!
! void initqueue(queue_t *queue, uint32_t size)__attribute__((C,spontaneous)){
! queue->head = 0;
! queue->tail = 0;
! queue->size = size;
! }
extern void initSyncFlash() __attribute__ ((C,spontaneous));
extern void initMMU() __attribute__ ((C,spontaneous));
+ extern void enableICache() __attribute__ ((C,spontaneous));
+ extern void enableDCache() __attribute__ ((C,spontaneous));
! command result_t init() {
! uint32_t tempQueueVal;
CKEN = (CKEN22_MEMC | CKEN20_IMEM | CKEN15_PMI2C | CKEN9_OST);
OSCC = (OSCC_OON);
!
while ((OSCC & OSCC_OOK) == 0);
+ TOSH_SET_PIN_DIRECTIONS();
+ initqueue(¶mtaskQueue,defaultQueueSize);
+ pushqueue(¶mtaskQueue,0);
+ popqueue(¶mtaskQueue,&tempQueueVal);
#if 1
//PLACE PXA27X into 104MHz mode....valid bus settings
!
! CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ;
! asm volatile (
! "mcr p14,0,%0,c6,c0,0\n\t"
! :
! : "r" (0xb)
! );
! #else
! // Place PXA27X into 13M w/ PPLL enabled...other bits are ignored...but might be useful later
! /*********
! Don't early enable PLL here. Page 3-96 of manual says
! "Write to this bit only when the processor is in 13M mode and the core PLL has
! been disabled by setting CPDIS. In normal run mode, writing to this bit causes
! unpredictable results"
! *******/
!
! CCCR = (CCCR_CPDIS | CCCR_L(8) | CCCR_2N(2) | CCCR_A);
asm volatile (
"mcr p14,0,%0,c6,c0,0\n\t"
***************
*** 121,130 ****
);
#endif
! //initialize the MMU...call assembly routine
! initMMU();
!
!
! #if 1
! //initialize the memory controller
//PXA27x MemConttroller 1st tier initialization.See 6.4.10 for details
SA1110 = SA1110_SXSTACK(1);
--- 162,168 ----
);
#endif
!
! #if 1
! //initialize the memory controller
//PXA27x MemConttroller 1st tier initialization.See 6.4.10 for details
SA1110 = SA1110_SXSTACK(1);
***************
*** 153,158 ****
//PXA27x MemController 5th tier initialization.See 6.4.10 for details
//SXCNFG = SXCNFG_SXEN0 | SXCNFG_SXCL0(4) | SXCNFG_SXTP0(3);
initSyncFlash();
!
#endif
--- 191,200 ----
//PXA27x MemController 5th tier initialization.See 6.4.10 for details
//SXCNFG = SXCNFG_SXEN0 | SXCNFG_SXCL0(4) | SXCNFG_SXTP0(3);
+
+ //initialize the MMU
+ initMMU();
+ enableICache();
initSyncFlash();
! enableDCache();
#endif
Index: mmu_table.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/mmu_table.s,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** mmu_table.s 4 Aug 2005 22:34:26 -0000 1.1
--- mmu_table.s 18 Aug 2005 23:05:38 -0000 1.2
***************
*** 380,384 ****
@// this should get us to 0x5600
! .word 0x58000002 @ internal SRAM control registers
@.ALIGN 0x100 @ (0x5700=0x4000+0x5C0*4)
--- 380,384 ----
@// this should get us to 0x5600
! .word 0x58000002 @ internal SRAM control registers
@.ALIGN 0x100 @ (0x5700=0x4000+0x5C0*4)
***************
*** 386,390 ****
@// this should get us to 0x5700
! .word 0x5C00000A @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
@.ALIGN 0x1000 @// this should get us to 0x6000
--- 386,392 ----
@// this should get us to 0x5700
! @RA...disable SRAM cacheability until we deal with dynamic DMA/cache interaction problem
! @.word 0x5C00000A @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
! .word 0x5C000002 @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
@.ALIGN 0x1000 @// this should get us to 0x6000
***************
*** 805,810 ****
.align 8
@// this should get us to 0x5700
!
! .word 0x5C00000E @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
@.ALIGN 0x1000 @// this should get us to 0x6000
--- 807,813 ----
.align 8
@// this should get us to 0x5700
! @RA...disable SRAM cacheability until we deal with dynamic DMA/cache interaction problem
! @.word 0x5C00000E @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
! .word 0x5C000002 @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
@.ALIGN 0x1000 @// this should get us to 0x6000
Index: util.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/util.s,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** util.s 4 Aug 2005 22:34:26 -0000 1.1
--- util.s 18 Aug 2005 23:05:38 -0000 1.2
***************
*** 5,9 ****
SUB PC, PC, #4 @ branch to next instruction
.endm
!
.extern MMUTableWT
.extern MMUTableWB
--- 5,17 ----
SUB PC, PC, #4 @ branch to next instruction
.endm
! @@@@@@@@@@@@@@@@@@@@@@@@@
! @ to create an assembly function that confirms to AAPCS (or so I think ;o)
! @ .func function name
! @ STMFD R13!, {R4 - R12, LR}..alternatively STMFD R13!, {registers used, LR}
! @ {function body}
! @ LDMFD R13!, {R4 - R12, PC}...must match above with LR replaced by PC
! @ .endfunc
! @@@@@@@@@@@@@@@@@@@@@@@@@@
!
.extern MMUTableWT
.extern MMUTableWB
***************
*** 20,33 ****
.equ SXCNFG_offset,(0x1c)
initSyncFlash:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
! .global initSyncFlash
! ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base
! ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register
! ldr r3, =FLASH_WRITE @ Write to flash instruction
! ldr r4, =FLASH_WCONF @ Write to flash confirm instruction
! ldr r5, =FLASH_READ @ Load "read array" mode command
! ldr r6, =0x0 @ Boot ROM Flash Base address
! ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now
b goSyncFlash
--- 28,48 ----
.equ SXCNFG_offset,(0x1c)
+ .global initMMU
+ .global initSyncFlash
+ .global enableICache
+ .global enableDCache
+
initSyncFlash:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
! @also, the DCache being on in WB mode will possibly cause this to randomly FAIL!
! .func initSyncFlash
! STMFD R13!, {R4 - R7, LR}
! ldr r1, =MEMORY_CONFIG_BASE @ Memory config register base
! ldr r2, =FLASH_SYNC_value @ Value to set into flash RCR register
! ldr r3, =FLASH_WRITE @ Write to flash instruction
! ldr r4, =FLASH_WCONF @ Write to flash confirm instruction
! ldr r5, =FLASH_READ @ Load "read array" mode command
! ldr r6, =0x0 @ Boot ROM Flash Base address
! ldr r7, =SXCNFG_sync_value @ SXCNFG Magic number for now
b goSyncFlash
***************
*** 36,40 ****
goSyncFlash:
@ Now program everything into the Flash and SXCNFG registers
! str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register
strh r3, [r2] @ Yes, the data is on the address bus!
strh r4, [r2] @ Confirm the write to the RCR
--- 51,55 ----
goSyncFlash:
@ Now program everything into the Flash and SXCNFG registers
! str r7, [r1, #SXCNFG_offset] @ Update PXA27x SXCNFG register
strh r3, [r2] @ Yes, the data is on the address bus!
strh r4, [r2] @ Confirm the write to the RCR
***************
*** 44,55 ****
nop
nop
!
! @ Return to caller
! mov PC, LR
!
readFlashStatusRegister:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
! .global readFlashStatusRegister
ldr r1, =FLASH_READSTATUS @ read status instruction
ldr r2, =FLASH_READ @ Load "read array" mode command
--- 59,68 ----
nop
nop
! LDMFD R13!, {R4 - R7, PC}
! .endfunc
readFlashStatusRegister:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
! .func readFlashStatusRegister
ldr r1, =FLASH_READSTATUS @ read status instruction
ldr r2, =FLASH_READ @ Load "read array" mode command
***************
*** 64,68 ****
ldrh r0, [r3] @ Confirm the write to the RCR
strh r2, [r3] @ Place flash back in read mode
! ldrh r2, [r3] @ Create a data dependency stall to guarantee write
nop @ go to the end of the cache line
nop
--- 77,82 ----
ldrh r0, [r3] @ Confirm the write to the RCR
strh r2, [r3] @ Place flash back in read mode
! ldrh r2, [r3] @ Create a data dependency stall
! @ to guarantee write
nop @ go to the end of the cache line
nop
***************
*** 71,78 ****
@ Return to caller
mov PC, LR
!
readFlashCFI:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
! .global readFlashCFI
ldr r1, =0x98 @ read status instruction
ldr r2, =FLASH_READ @ Load "read array" mode command
--- 85,94 ----
@ Return to caller
mov PC, LR
! .endfunc
!
readFlashCFI:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
! .func readFlashCFI
! STMFD R13!, {R4, PC}
ldr r1, =0x98 @ read status instruction
ldr r2, =FLASH_READ @ Load "read array" mode command
***************
*** 81,92 ****
b goReadCFI
! @align on cache line so that we fetch the next 8 instructions...
.align 5
goReadCFI:
@ Now program everything into the Flash and SXCNFG registers
! strh r1, [r3] @ Yes, the data is on the address bus!
ldrh r0, [r4] @ read into r0
strh r2, [r3] @ Place flash back in read mode
! ldrh r2, [r3] @ Create a data dependency stall to guarantee write
nop @ go to the end of the cache line
nop
--- 97,109 ----
b goReadCFI
! @align on cache line so that we fetch the next 8 instructions...
.align 5
goReadCFI:
@ Now program everything into the Flash and SXCNFG registers
! strh r1, [r3] @ Yes, the data is on the bus!
ldrh r0, [r4] @ read into r0
strh r2, [r3] @ Place flash back in read mode
! ldrh r2, [r3] @ Create a data dependency stall
! @ to guarantee write
nop @ go to the end of the cache line
nop
***************
*** 94,104 ****
nop
@ Return to caller
! mov PC, LR
! @assembly routine to init our MMU....just for kicks align on an icache line ; o)
! .align 5
initMMU:
! .global initMMU
MRC P15,0,R0,C3,C0,0 @read the domain register into R0
ORR R0, R0, #0xFF @make sure that we completely enable domain 0
--- 111,121 ----
nop
@ Return to caller
! LDMFD R13!, {R4, PC}
! .endfunc
! @assembly routine to init our MMU
initMMU:
! .func initMMU
MRC P15,0,R0,C3,C0,0 @read the domain register into R0
ORR R0, R0, #0xFF @make sure that we completely enable domain 0
***************
*** 106,116 ****
CPWAIT R0 @be anal and make sure it completes
- _WritePageTable:
@time to setup the page table base register
! LDR R0, =MMUTableWT @move the table we want into R0
MCR P15, 0, R0, C2, C0 @save it
CPWAIT R0 @wait it
- _EnablePageTable:
@time to enable the MMU!
MRC P15,0,R0,C1,C0,0 @get CP15 register 1
--- 123,131 ----
CPWAIT R0 @be anal and make sure it completes
@time to setup the page table base register
! LDR R0, =MMUTableWB @move the table we want into R0
MCR P15, 0, R0, C2, C0 @save it
CPWAIT R0 @wait it
@time to enable the MMU!
MRC P15,0,R0,C1,C0,0 @get CP15 register 1
***************
*** 118,123 ****
MCR P15,0,R0,C1,C0,0 @save it
CPWAIT R0 @wait it
! @icache section
@globally unlock the icache
MCR P15, 0, R0, C9, C1, 1
--- 133,142 ----
MCR P15,0,R0,C1,C0,0 @save it
CPWAIT R0 @wait it
+ mov PC, LR @return
+ .endfunc
! enableICache:
! .func enableICache
! @icache section
@globally unlock the icache
MCR P15, 0, R0, C9, C1, 1
***************
*** 147,152 ****
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
! @dcache section
@globally unlock the dtlb
MCR P15, 0, R0, c10, c8, 1
--- 166,175 ----
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
+ MOV PC, LR @return
+ .endfunc
!
! enableDCache:
! .func enableDCache
@globally unlock the dtlb
MCR P15, 0, R0, c10, c8, 1
***************
*** 172,176 ****
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
!
! MOV PC, LR
!
--- 195,198 ----
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
- Previous message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2
hardware.h, 1.6, 1.7
- Next message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x DMA.h,
NONE, 1.1 PXA27XHPLDMA.nc, NONE, 1.1 PXA27XHPLDMAC.nc, NONE,
1.1 PXA27XHPLDMAM.nc, NONE, 1.1 PXA27XDMAC.nc, 1.1,
1.2 PXA27XDMAChannel.nc, 1.1, 1.2 PXA27XDMAM.nc, 1.1, 1.2
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