[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x pxa27x_registers.h, 1.7, 1.8

[Robbie Adler]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv32079

Modified Files:
	pxa27x_registers.h 
Log Message:
updates to a couple of registers defines


Index: pxa27x_registers.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/pxa27x_registers.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** pxa27x_registers.h	18 Aug 2005 20:22:44 -0000	1.7
--- pxa27x_registers.h	18 Aug 2005 23:24:39 -0000	1.8
***************
*** 1,1509 ****
! // $Id$ 
! 
! /*									tab:4
!  *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
!  *  downloading, copying, installing or using the software you agree to
!  *  this license.  If you do not agree to this license, do not download,
!  *  install, copy or use the software.
!  *
!  *  Intel Open Source License 
!  *
[...2994 lines suppressed...]
! #define MSRXFIFO	_PXAREG(0x41800018) /* MSHC Receive FIFO register 17-14 */
! #define MSTXFIFO	_PXAREG(0x4180001C) /* MSHC Transmit FIFO register 17-15 */
! 
! 
! /******************************************************************************/
! /* Synchronous Serial Port 3 */
! /******************************************************************************/
! #define SSCR0_3	_PXAREG(0x41900000) /* SSP 3 Control register 0 8-25 */
! #define SSCR1_3	_PXAREG(0x41900004) /* SSP 3 Control register 1 8-29 */
! #define SSSR_3	_PXAREG(0x41900008) /* SSP 3 Status register 8-43 */
! #define SSITR_3	_PXAREG(0x4190000C) /* SSP 3 Interrupt Test register 8-42 */
! #define SSDR_3	_PXAREG(0x41900010) /* SSP 3 Data Write register/Data Read register 8-48 */
! #define SSTO_3	_PXAREG(0x41900028) /* SSP 3 Time-Out register 8-41 */
! #define SSPSP_3	_PXAREG(0x4190002C) /* SSP 3 Programmable Serial Protocol 8-39 */
! #define SSTSA_3	_PXAREG(0x41900030) /* SSP TX Timeslot Active register 8-48 */
! #define SSRSA_3	_PXAREG(0x41900034) /* SSP RX Timeslot Active register 8-49 */
! #define SSTSS_3	_PXAREG(0x41900038) /* SSP Timeslot Status register 8-50 */
! #define SSACD_3	_PXAREG(0x4190003C) /* SSP Audio Clock Divider register 8-51 */
! 
! #endif /* _PXA27X_REGISTER_H */