[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2 DVFS.nc,
NONE, 1.1 DVFSC.nc, NONE, 1.1 DVFSM.nc, NONE,
1.1 DebugUARTBufferC.nc, NONE, 1.1 DebugUARTBufferM.nc, NONE,
1.1 UART.h, NONE, 1.1 BluSHC.nc, 1.3, 1.4 HPLCC2420M.nc, 1.7,
1.8 HPLFFUARTM.nc, 1.2, 1.3 PMICM.nc, 1.2, 1.3 SSP1M.nc, 1.3,
1.4 SettingsC.nc, 1.1, 1.2 SettingsM.nc, 1.1, 1.2 TrickleM.nc,
1.6, 1.7 UARTBufferC.nc, 1.2, 1.3 UARTBufferM.nc, 1.2, 1.3
Lama Nachman
lnachman at users.sourceforge.net
Thu Dec 8 15:13:17 PST 2005
Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv25214
Modified Files:
BluSHC.nc HPLCC2420M.nc HPLFFUARTM.nc PMICM.nc SSP1M.nc
SettingsC.nc SettingsM.nc TrickleM.nc UARTBufferC.nc
UARTBufferM.nc
Added Files:
DVFS.nc DVFSC.nc DVFSM.nc DebugUARTBufferC.nc
DebugUARTBufferM.nc UART.h
Log Message:
Updated the platform files from the internal tree on 12/08/05
--- NEW FILE: DVFS.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
/*
*
* Authors: Lama Nachman
*/
interface DVFS {
/*
* Switch the core frequency of the processor. It also changes the
* voltage to the lowest allowed voltage for the chosen frequency.
*
* @param coreFreq This can be any of the supported core frequencies
*
* @param sysBusFreq This can be any of the supported bus frequencies
*
* @return SUCCESS if an allowed combination is chosen.
*/
command result_t SwitchCoreFreq(uint32_t coreFreq, uint32_t sysBusFreq);
}
--- NEW FILE: DVFSC.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
*
* Author: Lama Nachman
*/
configuration DVFSC{
provides{
interface DVFS;
}
}
implementation{
components DVFSM, BluSHC, PMICC;
DVFS = DVFSM;
DVFSM.PMIC -> PMICC;
BluSHC.BluSH_AppI[unique("BluSH")] -> DVFSM.SwitchFreq;
}
--- NEW FILE: DVFSM.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2005 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/* @author Lama Nachman
*/
includes trace;
module DVFSM {
provides interface DVFS;
provides interface BluSH_AppI as SwitchFreq;
uses interface PMIC;
}
implementation
{
command result_t DVFS.SwitchCoreFreq(uint32_t coreFreq, uint32_t sysBusFreq) {
/*
* TODO : add all supported frequencies, for now support 13 & 104 only
* add core voltage switching to min value based on freq
*/
switch (coreFreq) {
case 13:
if (sysBusFreq != 13) {
return FAIL;
}
atomic {
CCCR = CCCR_CPDIS | CCCR_A;
asm volatile (
"mcr p14,0,%0,c6,c0,0\n\t"
:
: "r" (0x2)
);
// check that core PLL was disabled
while ((CCSR & CCSR_CPDIS_S) == 0);
}
return SUCCESS;
case 104:
if (sysBusFreq != 104) {
return FAIL;
}
atomic {
CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ;
asm volatile (
"mcr p14,0,%0,c6,c0,0\n\t"
:
: "r" (0xb)
);
// wait until core pll locks
while ((CCSR & CCSR_CPLCK) == 0);
}
return SUCCESS;
default:
return FAIL;
}
}
command BluSH_result_t SwitchFreq.getName(char *buff, uint8_t len) {
const char name[] = "SwitchFreq";
strcpy(buff, name);
return BLUSH_SUCCESS_DONE;
}
command BluSH_result_t SwitchFreq.callApp(char *cmdBuff, uint8_t cmdLen,
char *resBuff, uint8_t resLen) {
uint32_t target_freq;
if(strlen(cmdBuff) < 12) {
sprintf(resBuff,"SwitchFreq <Target Freq in MHz>\r\n");
} else {
sscanf(cmdBuff,"SwitchFreq %d", &target_freq);
if (call DVFS.SwitchCoreFreq(target_freq, target_freq) == SUCCESS) {
sprintf(resBuff,"Switched to %d successfully\r\n", target_freq);
} else {
sprintf(resBuff,"Failed to switch to %d\r\n", target_freq);
}
}
return BLUSH_SUCCESS_DONE;
}
}
--- NEW FILE: DebugUARTBufferC.nc ---
configuration DebugUARTBufferC {
provides {
interface StdControl as Control;
interface SendVarLenPacket;
interface ReceiveData;
}
}
implementation {
components DebugUARTBufferM, DebugUART;
Control = DebugUARTBufferM;
SendVarLenPacket = DebugUARTBufferM;
ReceiveData = DebugUARTBufferM;
DebugUARTBufferM.ByteComm -> DebugUART;
DebugUARTBufferM.ByteControl -> DebugUART;
}
--- NEW FILE: DebugUARTBufferM.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2002 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*
*/
/*
* This module maintains a buffer of characters to put on the UART.
* It copies incoming characters into the buffer and streams them out the
* UART as each previous character finishes.
*/
module DebugUARTBufferM {
provides {
interface StdControl as Control;
interface SendVarLenPacket;
interface ReceiveData;
}
uses {
interface ByteComm;
interface StdControl as ByteControl;
}
}
implementation
{
uint32_t Head; // Next entry in the buffer to fill
uint32_t Tail; // Oldest entry in the buffer
// Head == Tail -> buffer is empty
#define NEXT_BUFFER(ent, max) (((ent) >= ((max) - 1)) ? 0 : ((ent) + 1))
#define BUFFER_SIZE 400 // maximum characters buffered in the queue
char Buffer[BUFFER_SIZE]; // circular buffer of characters
bool BytePending; // whether there is a byte sent w/o a
// corresponding sendDone
/*
* Start of StdControl interface
*/
command result_t Control.init() {
atomic {
Head = 0;
Tail = 0;
BytePending = FALSE;
}
return call ByteControl.init();
}
command result_t Control.start() {
return call ByteControl.start();
}
command result_t Control.stop() {
return call ByteControl.stop();
}
/*
* End of StdControl interface
*/
result_t SendNextByte() {
bool busy;
uint32_t queueEmpty;
char nextChar;
atomic {
busy = (BytePending == TRUE);
queueEmpty = (Head ==Tail);
}
if (busy) {
return FAIL;
}
if (queueEmpty) return SUCCESS; // buffer is empty
atomic {
BytePending = TRUE;
nextChar = Buffer[Tail];
}
call ByteComm.txByte(nextChar);
// if (call ByteComm.txByte(Buffer[Tail]) == FAIL) {
// // UART not enabled
// Tail = Head;
// BytePending = FALSE;
// }
return SUCCESS;
}
/*
* Start of SendVarLenPacket interface
*/
command result_t SendVarLenPacket.send(uint8_t* data, uint8_t length) {
int i, size;
bool not_busy;
// see if there's enough room for this packet
atomic{
size = (Head < Tail) ? Head + BUFFER_SIZE - Tail : Head - Tail;
}
if (size + length >= BUFFER_SIZE) return FAIL; // not enough room
// copy incoming bytes to the buffer
atomic{
for (i = 0; i < length; i++) {
Buffer[Head] = data[i];
Head = NEXT_BUFFER(Head, BUFFER_SIZE);
}
not_busy = (BytePending == FALSE);
}
if (not_busy) SendNextByte();
return SUCCESS;
}
default event result_t SendVarLenPacket.sendDone(uint8_t* data, result_t suc) {
return suc;
}
/*
* End of SendVarLenPacket interface
*/
/*
* Start of ByteComm interface
*/
async event result_t ByteComm.txByteReady(bool success) {
uint32_t queueEmpty;
atomic {
BytePending = FALSE;
queueEmpty = (Head == Tail);
}
if (queueEmpty) return SUCCESS;
atomic {
Tail = NEXT_BUFFER(Tail, BUFFER_SIZE);
}
SendNextByte();
return SUCCESS;
}
// this appears to be redundant in the interface with txByteReady
async event result_t ByteComm.txDone() { return SUCCESS; }
async event result_t ByteComm.rxByteReady(uint8_t data, bool error, uint16_t str) {
//arguably need to add receive fifo here, however what should its behavior be?
signal ReceiveData.receive(&data, 1);
return SUCCESS;
}
/*
* End of ByteComm interface
*/
/*
* Start of ReceiveData interface
*/
default event result_t ReceiveData.receive(uint8_t* Data, uint32_t Length) {
return SUCCESS;
}
/*
* End of ReceiveData interface
*/
}
--- NEW FILE: UART.h ---
/* tab:4
* "Copyright (c) 2000-2003 The Regents of the University of California.
* All rights reserved.
*
* Permission to use, copy, modify, and distribute this software and its
* documentation for any purpose, without fee, and without written agreement is
* hereby granted, provided that the above copyright notice, the following
* two paragraphs and the author appear in all copies of this software.
*
* IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
* DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
* OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
* CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES,
* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE. THE SOFTWARE PROVIDED HEREUNDER IS
* ON AN "AS IS" BASIS, AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO
* PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS."
*
* Copyright (c) 2002-2003 Intel Corporation
* All rights reserved.
*
* This file is distributed under the terms in the attached INTEL-LICENSE
* file. If you do not find these files, copies can be found by writing to
* Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA,
* 94704. Attention: Intel License Inquiry.
*/
/*
*
* Authors: Lama Nachman
*
*/
#ifndef UART_H
#define UART_H
enum {
UART_BAUD_300 = 1,
UART_BAUD_1200 = 2,
UART_BAUD_2400 = 3,
UART_BAUD_4800 = 4,
UART_BAUD_9600 = 5,
UART_BAUD_19200 = 6,
UART_BAUD_38400 = 7,
UART_BAUD_57600 = 8,
UART_BAUD_115200 = 9,
UART_BAUD_230400 = 10,
UART_BAUD_460800 = 11,
UART_BAUD_921600 = 12
};
#endif
Index: BluSHC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/BluSHC.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** BluSHC.nc 2 Sep 2005 23:37:02 -0000 1.3
--- BluSHC.nc 8 Dec 2005 23:13:04 -0000 1.4
***************
*** 12,16 ****
implementation {
components
! UARTBufferC as UARTBuffer,
//DebugUARTBufferC as UARTBuffer,
#if USE_USB
--- 12,16 ----
implementation {
components
! DebugUARTBufferC as UARTBuffer,
//DebugUARTBufferC as UARTBuffer,
#if USE_USB
Index: HPLCC2420M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLCC2420M.nc,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** HPLCC2420M.nc 19 Sep 2005 23:58:34 -0000 1.7
--- HPLCC2420M.nc 8 Dec 2005 23:13:05 -0000 1.8
***************
*** 68,87 ****
#define USE_DMA 0
uint8_t gbDMAChannelInitDone;
bool gbIgnoreTxDMA;
! uint8_t RxDMAInProgress;
! norace uint8_t* rxbuf;
! norace uint8_t* txbuf;
! norace uint8_t* txrambuf;
! norace uint8_t* rxrambuf;
! norace uint8_t txlen;
! norace uint8_t rxlen;
! norace uint8_t txramlen;
! norace uint8_t rxramlen;
! norace uint8_t rxdummy,txdummy;
! norace uint16_t txramaddr;
! norace uint16_t rxramaddr;
! norace uint32_t errno;
command result_t StdControl.init() {
--- 68,94 ----
#define USE_DMA 0
+ #define DEBUG 0
uint8_t gbDMAChannelInitDone;
bool gbIgnoreTxDMA;
! bool gRadioOpInProgress;
!
! uint8_t* rxbuf;
! uint8_t* txbuf;
! uint8_t* txrambuf;
! uint8_t* rxrambuf;
! uint8_t txlen;
! uint8_t rxlen;
! uint8_t txramlen;
! uint8_t rxramlen;
! uint8_t rxdummy,txdummy;
! uint16_t txramaddr;
! uint16_t rxramaddr;
! uint32_t errno;
!
! #define HPLCC2420_DBG_LEVEL (DBG_USR1)
! #define DEASSERT_SPI_CS {TOSH_uwait(1); TOSH_SET_CC_CSN_PIN();}
! #define ASSERT_SPI_CS {TOSH_CLR_CC_CSN_PIN(); TOSH_uwait(1);}
! #define DRAIN_RXFIFO(_tmp) {while (SSSR_3 & SSSR_RNE) _tmp = SSDR_3;}
command result_t StdControl.init() {
***************
*** 92,96 ****
// _PXA_setaltfn(SSP3_SFRM,SSP3_SFRM_ALTFN,GPIOIN);
! atomic gbDMAChannelInitDone = 2;
call RxDMAChannel.requestChannel(DMAID_SSP3_RX,DMA_Priority1, TRUE);
call TxDMAChannel.requestChannel(DMAID_SSP3_TX,DMA_Priority1, TRUE);
--- 99,106 ----
// _PXA_setaltfn(SSP3_SFRM,SSP3_SFRM_ALTFN,GPIOIN);
! atomic{
! gbDMAChannelInitDone = 2;
! gRadioOpInProgress = FALSE;
! }
call RxDMAChannel.requestChannel(DMAID_SSP3_RX,DMA_Priority1, TRUE);
call TxDMAChannel.requestChannel(DMAID_SSP3_TX,DMA_Priority1, TRUE);
***************
*** 151,176 ****
* @return status byte from the chipcon
*/
async command uint8_t HPLCC2420.cmd(uint8_t addr) {
uint8_t status = 0;
uint8_t tmp;
! if(RxDMAInProgress == TRUE){
! RxDMAInProgress++;
}
!
! TOSH_CLR_CC_CSN_PIN();
// Empty the PXA recieve fifo...
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
! SSDR_3 = addr;
while (SSSR_3 & SSSR_BSY);
!
! TOSH_SET_CC_CSN_PIN();
!
status = SSDR_3;
return status;
}
!
/**
* Transmit 16-bit data
--- 161,222 ----
* @return status byte from the chipcon
*/
+ result_t getSSPPort(){
+ result_t res;
+ atomic{
+ if(gRadioOpInProgress){
+ res = FAIL;
+ }
+ else{
+ res = SUCCESS;
+ gRadioOpInProgress = TRUE;
+ }
+ }
+ return res;
+ }
+
+ result_t releaseSSPPort(){
+ result_t res;
+ atomic{
+ if(gRadioOpInProgress){
+ res = SUCCESS;
+ gRadioOpInProgress = FALSE;
+ }
+ else{
+ res = FAIL;
+ }
+ }
+ return res;
+ }
+
+
async command uint8_t HPLCC2420.cmd(uint8_t addr) {
uint8_t status = 0;
uint8_t tmp;
!
! if(getSSPPort()==FAIL){
! //something else is using the radio, print a message and return;
! //trace(DBG_USR1,"ERROR: HPLC2420.cmd has attempted to access the radio during an existing radio operation");
! return 0;
}
!
// Empty the PXA recieve fifo...
! DRAIN_RXFIFO(tmp);
+ ASSERT_SPI_CS;
+ SSDR_3 = addr;
while (SSSR_3 & SSSR_BSY);
! DEASSERT_SPI_CS;
status = SSDR_3;
+ if(releaseSSPPort() == FAIL){
+ trace(DBG_USR1,"ERROR: HPLC2420.cmd failed while attempting to release the SSP port");
+ return 0;
+ }
+ #if DEBUG
+ trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 cmd %#x..status =%#x\r\n",addr,status);
+ #endif
return status;
}
!
/**
* Transmit 16-bit data
***************
*** 181,193 ****
uint8_t status = 0;
uint8_t tmp;
!
! if(RxDMAInProgress == TRUE){
! RxDMAInProgress++;
}
! TOSH_CLR_CC_CSN_PIN();
!
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
SSDR_3 = addr;
SSDR_3 = ((data >> 8) & 0xFF);
--- 227,246 ----
uint8_t status = 0;
uint8_t tmp;
!
! if(getSSPPort()==FAIL){
! //something else is using the radio, print a message and return;
! trace(DBG_USR1,"ERROR: HPLC2420.write has attempted to access the radio during an existing radio operation");
! return 0;
}
! #if DEBUG
! trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 write %#x to %#x\r\n",data,addr);
! #endif
+ //drain the fifo
+ DRAIN_RXFIFO(tmp);
+
+ ASSERT_SPI_CS;
+
SSDR_3 = addr;
SSDR_3 = ((data >> 8) & 0xFF);
***************
*** 196,206 ****
while (SSSR_3 & SSSR_BSY);
! TOSH_SET_CC_CSN_PIN();
!
status = SSDR_3;
-
//drain the fifo since we got a couple of extra samples in there due to writes>reads
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
return status;
}
--- 249,261 ----
while (SSSR_3 & SSSR_BSY);
! DEASSERT_SPI_CS;
status = SSDR_3;
//drain the fifo since we got a couple of extra samples in there due to writes>reads
! DRAIN_RXFIFO(tmp);
!
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420.write failed while attempting to release the SSP port");
! return 0;
! }
return status;
}
***************
*** 214,227 ****
uint16_t data = 0;
uint8_t tmp;
!
! if(RxDMAInProgress == TRUE ){
! RxDMAInProgress++;
}
! TOSH_CLR_CC_CSN_PIN();
//drain the fifo so that we're in the right state
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
SSDR_3 = (addr | 0x40);
SSDR_3 = 0;
--- 269,288 ----
uint16_t data = 0;
uint8_t tmp;
!
! if(getSSPPort()==FAIL){
! //something else is using the radio, print a message and return;
! trace(DBG_USR1,"ERROR: HPLC2420.read has attempted to access the radio during an existing radio operation");
! return 0;
}
! #if DEBUG
! trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 read from %#x\r\n",addr);
! #endif
//drain the fifo so that we're in the right state
! DRAIN_RXFIFO(tmp);
!
! ASSERT_SPI_CS;
!
SSDR_3 = (addr | 0x40);
SSDR_3 = 0;
***************
*** 229,339 ****
while (SSSR_3 & SSSR_BSY);
!
! TOSH_SET_CC_CSN_PIN();
!
tmp = SSDR_3;
data = SSDR_3;
data = ((data << 8 ) & 0xFF00);
data |= SSDR_3;
!
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
return data;
}
-
task void signalRAMRd() {
! signal HPLCC2420RAM.readDone(rxramaddr, rxramlen, rxrambuf);
}
async command result_t HPLCC2420RAM.read(uint16_t addr, uint8_t length, uint8_t* buffer) {
uint8_t i = 0, tmp;
// XXX - To simplify things, this only supports 11 byte reads. Longer would be
// signficantly more complicated.
! if(RxDMAInProgress == TRUE){
! RxDMAInProgress++;
}
! if (length < 12) {
!
! TOSH_CLR_CC_CSN_PIN();
! atomic {
! rxramaddr = addr;
! rxramlen = length;
! rxrambuf = buffer;
! }
!
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
! SSDR_3 = ((rxramaddr & 0x7F) | 0x80);
! SSDR_3 = (((rxramaddr >> 1) & 0xC0) | 0x20);
!
! //this effectively allows us to read in the data
! for (i = 0; i < rxramlen; i++) {
SSDR_3 = 0;
}
!
! while (SSSR_3 & SSSR_BSY);
!
! TOSH_SET_CC_CSN_PIN();
!
! tmp = SSDR_3;
! tmp = SSDR_3;
!
! for (i = 0; i < rxramlen; i++) {
! rxrambuf[i] = SSDR_3;
}
! return post signalRAMRd();
}
! return FAIL;
}
task void signalRAMWr() {
! signal HPLCC2420RAM.writeDone(txramaddr, txramlen, txrambuf);
}
async command result_t HPLCC2420RAM.write(uint16_t addr, uint8_t length, uint8_t* buffer) {
uint8_t i = 0, tmp;
! if(RxDMAInProgress == TRUE){
! RxDMAInProgress++;
}
!
! if (length < 12) {
! TOSH_CLR_CC_CSN_PIN();
! atomic {
txramaddr = addr;
txramlen = length;
txrambuf = buffer;
}
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
! SSDR_3 = ((txramaddr & 0x7F) | 0x80);
! SSDR_3 = ((txramaddr >> 1) & 0xC0);
!
! for (i = 0; i < txramlen; i++) {
! SSDR_3 = txrambuf[i];
! }
!
! while (SSSR_3 & SSSR_BSY);
!
! TOSH_SET_CC_CSN_PIN();
!
! while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
!
! return post signalRAMWr();
}
! return FAIL;
}
task void signalRXFIFO() {
! signal HPLCC2420FIFO.RXFIFODone(rxlen, rxbuf);
}
--- 290,461 ----
while (SSSR_3 & SSSR_BSY);
! DEASSERT_SPI_CS;
!
tmp = SSDR_3;
data = SSDR_3;
data = ((data << 8 ) & 0xFF00);
data |= SSDR_3;
!
! DRAIN_RXFIFO(tmp);
!
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420.read failed while attempting to release the SSP port");
! return 0;
! }
!
return data;
}
task void signalRAMRd() {
! uint16_t ramaddr;
! uint8_t ramlen;
! uint8_t* rambuf;
!
! atomic{
! ramaddr = rxramaddr;
! ramlen = rxramlen;
! rambuf = rxrambuf;
! }
!
! signal HPLCC2420RAM.readDone(ramaddr, ramlen, rambuf);
}
async command result_t HPLCC2420RAM.read(uint16_t addr, uint8_t length, uint8_t* buffer) {
uint8_t i = 0, tmp;
+ uint32_t temp32;
// XXX - To simplify things, this only supports 11 byte reads. Longer would be
// signficantly more complicated.
+
+ #if DEBUG
+ trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 read %d bytes from %#x\r\n",length,addr);
+ #endif
+ if(getSSPPort()==FAIL){
+ //something else is using the radio, print a message and return;
+ trace(DBG_USR1,"ERROR: HPLC2420RAM.read has attempted to access the radio during an existing radio operation");
+ return 0;
+ }
+
+ //flush the SSP rx fifo and save state
+ DRAIN_RXFIFO(tmp);
! atomic {
! rxramaddr = addr;
! rxramlen = length;
! rxrambuf = buffer;
}
+ ASSERT_SPI_CS;
! SSDR_3 = ((addr & 0x7F) | 0x80);
! SSDR_3 = (((addr >> 1) & 0xC0) | 0x20);
! //wait for the bytes to get out, but let the fifo over flow
! while (SSSR_3 & SSSR_BSY);
!
! while(length >16){
! //still have more than 16 byte to go, do a "burst"
! for(i=0; i<16; i++){
SSDR_3 = 0;
}
! while(SSSR_3 & SSSR_BSY);
! for(i=0; i<16; i++){
! temp32=SSDR_3;
! *buffer++ = temp32;
}
+ length -= 16;
+ }
+ for(i=0;i<length;i++){
+ SSDR_3 = 0;
+ }
+ while(SSSR_3 & SSSR_BSY);
! for(i=0; i<length; i++){
! temp32=SSDR_3;
! *buffer++ = temp32;
}
! DEASSERT_SPI_CS;
! DRAIN_RXFIFO(tmp);
!
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420RAM.read failed while attempting to release the SSP port");
! return 0;
! }
! return post signalRAMRd();
}
+
task void signalRAMWr() {
! uint16_t ramaddr;
! uint8_t ramlen;
! uint8_t* rambuf;
! atomic{
! ramaddr = txramaddr;
! ramlen = txramlen;
! rambuf = txrambuf;
! }
!
! signal HPLCC2420RAM.writeDone(ramaddr, ramlen, rambuf);
}
async command result_t HPLCC2420RAM.write(uint16_t addr, uint8_t length, uint8_t* buffer) {
uint8_t i = 0, tmp;
+
! #if DEBUG
! trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 write %d bytes to %#x\r\n",length,addr);
! #endif
! if(getSSPPort()==FAIL){
! //something else is using the radio, print a message and return;
! trace(DBG_USR1,"ERROR: HPLC2420RAM.write has attempted to access the radio during an existing radio operation");
! return 0;
}
! DRAIN_RXFIFO(tmp);
! atomic {
txramaddr = addr;
txramlen = length;
txrambuf = buffer;
+ }
+
+ ASSERT_SPI_CS;
+
+ SSDR_3 = ((addr & 0x7F) | 0x80);
+ SSDR_3 = ((addr >> 1) & 0xC0);
+ while (SSSR_3 & SSSR_BSY);
+
+ while(length >16){
+ //still have more than 16 byte to go, do a "burst"
+ for(i=0; i<16; i++){
+ SSDR_3 = *buffer++;
}
+ while(SSSR_3 & SSSR_BSY);
+ length -= 16;
+ }
+ for(i=0;i<length;i++){
+ SSDR_3 = *buffer++;
+ }
+ while(SSSR_3 & SSSR_BSY);
+
+ //now clear out the FIFO
+ DEASSERT_SPI_CS;
+
+ DRAIN_RXFIFO(tmp);
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420RAM.write failed while attempting to release the SSP port");
! return 0;
}
!
! return post signalRAMWr();
}
task void signalRXFIFO() {
! uint8_t len, *buf;
! atomic{
! len = rxlen;
! buf = rxbuf;
! }
! signal HPLCC2420FIFO.RXFIFODone(len, buf);
}
***************
*** 350,395 ****
*/
async command result_t HPLCC2420FIFO.readRXFIFO(uint8_t length, uint8_t *data) {
! uint8_t tmp, OkToUse;
uint8_t pktlen;
!
! if(RxDMAInProgress == TRUE){
! RxDMAInProgress++;
}
! atomic {
rxbuf = data;
OkToUse = gbDMAChannelInitDone;
}
- //flush the receive fifo
- while (SSSR_3 & SSSR_RNE) tmp = SSDR_3;
//for cache coherency reasons, we need to read in the length field from the radio's ram
//read 1 byte from address 0x80
! TOSH_CLR_CC_CSN_PIN();
!
//put the address we're interested in out after formating it properly
SSDR_3 = 0x80;
SSDR_3 = (((0x80 >>1) & 0xc0) | 0x20);
-
SSDR_3 = 0; //get the byte we care about
while(SSSR_3 & SSSR_BSY);
! TOSH_SET_CC_CSN_PIN();
!
! tmp = SSDR_3;
tmp = SSDR_3;
pktlen = SSDR_3;
!
! TOSH_CLR_CC_CSN_PIN();
!
//send the access RXFIFO command
SSDR_3 = (CC2420_RXFIFO | 0x40);
while (SSSR_3 & SSSR_BSY);
! tmp = SSDR_3;
!
!
//increment the length to include the length byte itself
pktlen++;
if (pktlen > 0 && (OkToUse == 0)) {
--- 472,534 ----
*/
async command result_t HPLCC2420FIFO.readRXFIFO(uint8_t length, uint8_t *data) {
! uint32_t temp32;
! uint8_t status,tmp, OkToUse;
uint8_t pktlen;
! result_t ret;
!
! if(getSSPPort()==FAIL){
! //something else is using the radio, print a message and return;
! trace(DBG_USR1,"ERROR: HPLC2420FIFO.readRXFIFO has attempted to access the radio during an existing radio operation");
! return 0;
}
+
+ #if DEBUG
+ trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 readRXFIFO...length=%d\r\n",length);
+ #endif
+ //flush the receive fifo
+ DRAIN_RXFIFO(tmp);
! //store stuff away correctlu
! atomic{
rxbuf = data;
OkToUse = gbDMAChannelInitDone;
}
+ #if 0
//for cache coherency reasons, we need to read in the length field from the radio's ram
//read 1 byte from address 0x80
! ASSERT_SPI_CS;
!
//put the address we're interested in out after formating it properly
SSDR_3 = 0x80;
SSDR_3 = (((0x80 >>1) & 0xc0) | 0x20);
SSDR_3 = 0; //get the byte we care about
while(SSSR_3 & SSSR_BSY);
! DEASSERT_SPI_CS;
!
! status = SSDR_3;
tmp = SSDR_3;
pktlen = SSDR_3;
!
! #endif
!
! ASSERT_SPI_CS;
!
//send the access RXFIFO command
SSDR_3 = (CC2420_RXFIFO | 0x40);
+ SSDR_3 = 0;
while (SSSR_3 & SSSR_BSY);
! status = SSDR_3;
! pktlen = SSDR_3;
! data[0] = pktlen;
! data++;
! #if 1
//increment the length to include the length byte itself
pktlen++;
+ #else
+ //don't increment the length since we no longer need to read it out
+ #endif
if (pktlen > 0 && (OkToUse == 0)) {
***************
*** 398,405 ****
rxlen = (pktlen < length) ? pktlen : length;
}
!
#if USE_DMA
! call RxDMAChannel.setTargetAddr((uint32_t)(rxbuf));
! call RxDMAChannel.setTransferLength(rxlen);
//enable the dma interrupt and go
--- 537,547 ----
rxlen = (pktlen < length) ? pktlen : length;
}
!
#if USE_DMA
! //DO NOT USE DMA !!!
!
! cleanDCache(data-1,1);
! call RxDMAChannel.setTargetAddr((uint32_t)(rxbuf+1));
! call RxDMAChannel.setTransferLength(rxlen-1);
//enable the dma interrupt and go
***************
*** 407,411 ****
if(call RxDMAChannel.run(TRUE) == FAIL){
errno = -1;
! return FAIL;
}
RxDMAInProgress = TRUE;
--- 549,553 ----
if(call RxDMAChannel.run(TRUE) == FAIL){
errno = -1;
! ret=FAIL;
}
RxDMAInProgress = TRUE;
***************
*** 420,424 ****
//enable the dma interrupt and go
SSCR1_3 |= SSCR1_TSRE;
! return call TxDMAChannel.run(TRUE);
#else
//read it out manually...don't use DMA we have a 16 entry fifo, so let's take advantage!
--- 562,566 ----
//enable the dma interrupt and go
SSCR1_3 |= SSCR1_TSRE;
! ret = call TxDMAChannel.run(TRUE);
#else
//read it out manually...don't use DMA we have a 16 entry fifo, so let's take advantage!
***************
*** 426,430 ****
//introduce a new scope to avoid compiler warnings
int i;
! length = rxlen; //overload the parameter that was passed to use with the proper value
while(length >16){
//still have more than 16 byte to go, do a "burst"
--- 568,574 ----
//introduce a new scope to avoid compiler warnings
int i;
! atomic{
! length = rxlen; //overload the parameter that was passed to use with the proper value
! }
while(length >16){
//still have more than 16 byte to go, do a "burst"
***************
*** 434,438 ****
while(SSSR_3 & SSSR_BSY);
for(i=0; i<16; i++){
! *data++ = SSDR_3;
}
length -= 16;
--- 578,583 ----
while(SSSR_3 & SSSR_BSY);
for(i=0; i<16; i++){
! temp32=SSDR_3;
! *data++ = temp32;
}
length -= 16;
***************
*** 443,464 ****
while(SSSR_3 & SSSR_BSY);
for(i=0; i<length; i++){
! *data++ = SSDR_3;
}
post signalRXFIFO();
! TOSH_SET_CC_CSN_PIN();
! return SUCCESS;
}
#endif
}
else {
! TOSH_SET_CC_CSN_PIN();
! return FAIL;
}
}
task void signalTXFIFO() {
! signal HPLCC2420FIFO.TXFIFODone(txlen, txbuf);
}
!
/**
* Writes a series of bytes to the transmit FIFO.
--- 588,621 ----
while(SSSR_3 & SSSR_BSY);
for(i=0; i<length; i++){
! temp32=SSDR_3;
! *data++ = temp32;
}
post signalRXFIFO();
! DEASSERT_SPI_CS;
! ret = SUCCESS;
}
#endif
}
else {
! DEASSERT_SPI_CS;
! ret=FAIL;
! }
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420FIFO.readRXFIFO failed while attempting to release the SSP port");
! return 0;
}
+
+ return ret;
}
task void signalTXFIFO() {
! uint8_t len, *buf;
! atomic{
! len = txlen;
! buf = txbuf;
! }
! signal HPLCC2420FIFO.TXFIFODone(len, buf);
}
!
/**
* Writes a series of bytes to the transmit FIFO.
***************
*** 472,479 ****
uint8_t OkToUse;
! if(RxDMAInProgress == TRUE){
! RxDMAInProgress++;
}
atomic {
txbuf = data;
--- 629,641 ----
uint8_t OkToUse;
! if(getSSPPort()==FAIL){
! //something else is using the radio, print a message and return;
! trace(DBG_USR1,"ERROR: HPLC2420RAM.read has attempted to access the radio during an existing radio operation");
! return FAIL;
}
+ #if DEBUG
+ trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 writeTXFIFO length=%d\r\n",length);
+ #endif
atomic {
txbuf = data;
***************
*** 493,497 ****
gbIgnoreTxDMA = FALSE;
}
! TOSH_CLR_CC_CSN_PIN();
SSDR_3 = (CC2420_TXFIFO);
--- 655,659 ----
gbIgnoreTxDMA = FALSE;
}
! ASSERT_SPI_CS;
SSDR_3 = (CC2420_TXFIFO);
***************
*** 510,515 ****
int i;
uint8_t tmp;
!
! TOSH_CLR_CC_CSN_PIN();
SSDR_3 = (CC2420_TXFIFO);
while(SSSR_3 & SSSR_BSY);
--- 672,679 ----
int i;
uint8_t tmp;
!
! DRAIN_RXFIFO(tmp);
!
! ASSERT_SPI_CS;
SSDR_3 = (CC2420_TXFIFO);
while(SSSR_3 & SSSR_BSY);
***************
*** 533,541 ****
}
post signalTXFIFO();
! TOSH_SET_CC_CSN_PIN();
return SUCCESS;
}
#endif
! }
async command result_t InterruptFIFOP.startWait(bool low_to_high){
--- 697,712 ----
}
post signalTXFIFO();
! DEASSERT_SPI_CS;
! DRAIN_RXFIFO(tmp);
!
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420FIFO.writeTXFIFO failed while attempting to release the SSP port");
! return 0;
! }
!
return SUCCESS;
}
#endif
! }
async command result_t InterruptFIFOP.startWait(bool low_to_high){
***************
*** 677,686 ****
async event void RxDMAChannel.Interrupt(){
//turn off things and post a task to signal that we're done
! RxDMAInProgress = FALSE;
! TOSH_SET_CC_CSN_PIN();
!
SSCR1_3 &= ~SSCR1_RSRE;
! invalidateDCache(rxbuf, rxlen);
!
post signalRXFIFO();
return;
--- 848,860 ----
async event void RxDMAChannel.Interrupt(){
//turn off things and post a task to signal that we're done
! DEASSERT_SPI_CS;
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420FIFO.readRXFIFO DMA version failed while attempting to release the SSP port");
! }
!
SSCR1_3 &= ~SSCR1_RSRE;
! atomic{
! invalidateDCache(rxbuf, rxlen);
! }
post signalRXFIFO();
return;
***************
*** 703,708 ****
tmp = SSDR_3;
}
! TOSH_SET_CC_CSN_PIN();
!
post signalTXFIFO();
}
--- 877,885 ----
tmp = SSDR_3;
}
! DEASSERT_SPI_CS;
! if(releaseSSPPort() == FAIL){
! trace(DBG_USR1,"ERROR: HPLC2420FIFO.writeTXFIFO DMA version failed while attempting to release the SSP port");
! }
!
post signalTXFIFO();
}
Index: HPLFFUARTM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLFFUARTM.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** HPLFFUARTM.nc 6 Sep 2005 18:13:58 -0000 1.2
--- HPLFFUARTM.nc 8 Dec 2005 23:13:06 -0000 1.3
***************
*** 47,50 ****
--- 47,52 ----
*/
+ includes UART;
+
module HPLFFUARTM {
provides {
***************
*** 58,62 ****
implementation
{
! uint8_t baudrate = 115200;
async event void Interrupt.fired(){
--- 60,64 ----
implementation
{
! uint8_t baudrate = UART_BAUD_115200;
async event void Interrupt.fired(){
***************
*** 80,83 ****
--- 82,86 ----
//Receive Error
error = FFLSR;
+ trace(DBG_USR1, "UART Error %d\r\n", error);
break;
}
***************
*** 85,88 ****
--- 88,149 ----
}
+ void setBaudRate(uint8_t rate) {
+
+ switch (rate) {
+ case UART_BAUD_300:
+ FFDLL = 0x0;
+ FFDLH = 0xC;
+ break;
+ case UART_BAUD_1200:
+ FFDLL = 0x0;
+ FFDLH = 0x3;
+ break;
+ case UART_BAUD_2400:
+ FFDLL = 0x80;
+ FFDLH = 0x1;
+ break;
+ case UART_BAUD_4800:
+ FFDLL = 0xC0;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_9600:
+ FFDLL = 0x60;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_19200:
+ FFDLL = 0x30;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_38400:
+ FFDLL = 0x18;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_57600:
+ FFDLL = 0x10;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_115200:
+ FFDLL = 0x8;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_230400:
+ FFDLL = 0x4;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_460800:
+ FFDLL = 0x2;
+ FFDLH = 0;
+ break;
+ case UART_BAUD_921600:
+ FFDLL = 0x1;
+ FFDLH = 0;
+ break;
+ default:
+ FFDLL = 0x8; // set default to 115200
+ FFDLH = 0;
+ break;
+ }
+ }
+
async command result_t UART.init() {
***************
*** 101,106 ****
--- 162,172 ----
FFLCR |=LCR_DLAB; //turn on DLAB so we can change the divisor
+ #if 0
FFDLL = 8; //configure to 115200;
FFDLH = 0;
+ #else
+ // USE baudrate variable
+ setBaudRate(baudrate);
+ #endif
FFLCR &= ~(LCR_DLAB); //turn off DLAB
***************
*** 134,137 ****
--- 200,205 ----
command result_t UART.setRate(uint8_t newbaudrate){
+ // TODO : Assume this is called before init for now
+ baudrate = newbaudrate;
return SUCCESS;
}
Index: PMICM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/PMICM.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** PMICM.nc 18 Oct 2005 21:11:20 -0000 1.2
--- PMICM.nc 8 Dec 2005 23:13:06 -0000 1.3
***************
*** 44,52 ****
#define START_RADIO_LDO 1
#define START_SENSOR_BOARD_LDO 1
/*
! * VCC_MEM is connected to BUCK2 by default, make sure you have a board
! * that has the right resistor settings before disabling BUCK2
*/
! #define DISABLE_BUCK2 0
includes trace;
--- 44,58 ----
#define START_RADIO_LDO 1
#define START_SENSOR_BOARD_LDO 1
+
/*
! * VCC_MEM is connected to LDO by default,
! * If the imote2 board has R49 on and R40 off then ENABLE_BUCK2 can be set t0 0
! * This is assumed to be the default setting.
! * If the imote2 board has R49 off and R40 on, you need to set ENABLE_BUCK2
! * to 1 when making the app.
*/
! #ifndef ENABLE_BUCK2
! #define ENABLE_BUCK2 1
! #endif
includes trace;
***************
*** 153,157 ****
void startLDOs() {
- uint8_t temp;
uint8_t oldVal, newVal;
--- 159,162 ----
***************
*** 174,178 ****
#endif
! #if DISABLE_BUCK2 // Disable BUCK2 if VCC_MEM is not configured to use BUCK2
readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);
newVal = oldVal & ~BRC1_BUCK_EN;
--- 179,183 ----
#endif
! #if (!ENABLE_BUCK2) // Disable BUCK2 if VCC_MEM is not configured to use BUCK2
readPMIC(PMIC_B_REG_CONTROL_1, &oldVal, 1);
newVal = oldVal & ~BRC1_BUCK_EN;
***************
*** 215,220 ****
// Set default core voltage to 0.85 V
! call PMIC.setCoreVoltage(B2R1_TRIM_P85_V);
!
startLDOs();
return SUCCESS;
--- 220,226 ----
// Set default core voltage to 0.85 V
! //call PMIC.setCoreVoltage(B2R1_TRIM_P85_V);
! call PMIC.setCoreVoltage(B2R1_TRIM_P95_V);
!
startLDOs();
return SUCCESS;
***************
*** 245,248 ****
--- 251,258 ----
}
+ task void resetTask(){
+ call Reset.reset();
+ }
+
async event void PMICInterrupt.fired(){
uint8_t events[3];
***************
*** 258,262 ****
}
if(localGotReset==TRUE){
! call Reset.reset();
}
else{
--- 268,273 ----
}
if(localGotReset==TRUE){
! //eliminate error since Reset.reset is not declared as async
! post resetTask();
}
else{
***************
*** 280,284 ****
command result_t PMIC.shutDownLDOs() {
- uint8_t temp;
uint8_t oldVal, newVal;
/*
--- 291,294 ----
Index: SSP1M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SSP1M.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** SSP1M.nc 18 Oct 2005 21:11:20 -0000 1.3
--- SSP1M.nc 8 Dec 2005 23:13:06 -0000 1.4
***************
*** 236,240 ****
//RWOT
! temp |= (gReceiveWithoutTransmit == TRUE)? SSCR1_RWOT : 0;
//TRAIL
--- 236,240 ----
//RWOT
! temp |= (gReceiveWithoutTransmit == TRUE)? SSCR1_RWOT : 0;
//TRAIL
***************
*** 260,272 ****
//MWDS
! temp |= (gMicrowireSize == SSP_8bitCommands)? 0 : SSCR1_MWDS;
! //SPH
! //SPO
! //LBM
! //TIE
! //RIE
! return temp;
}
--- 260,272 ----
//MWDS
! temp |= (gMicrowireSize == SSP_8bitCommands)? 0 : SSCR1_MWDS;
! //SPH
! //SPO
! //LBM
! //TIE
! //RIE
! return temp;
}
***************
*** 289,303 ****
}
! command result_t BulkTxRx.BulkReceive(uint8_t *RxBuffer, uint16_t NumBytes){
//need to fake the dma transaction until we get DMA working...
! gRxBuffer = (uint16_t *)RxBuffer;
! gRxNumBytes = NumBytes;
! gRxBufferPos = 0;
! gNumRxFifoOverruns=0;
! call SSPInterrupt.disable();
! if(!gRxInProgress){
! if(!gTxInProgress){
//if we're neither transmitting nor receiving, setup the port how we want it be setup
CKEN |= (CKEN23_SSP1);
--- 289,311 ----
}
! command result_t BulkTxRx.BulkReceive(uint8_t *RxBuffer, uint16_t NumBytes){
//need to fake the dma transaction until we get DMA working...
+ bool RxInProgress, TxInProgress;
! gRxBuffer = (uint16_t *)RxBuffer;
! gRxNumBytes = NumBytes;
! gRxBufferPos = 0;
! gNumRxFifoOverruns=0;
! call SSPInterrupt.disable();
!
! atomic{
! RxInProgress = gRxInProgress;
! TxInProgress = gTxInProgress;
! }
!
!
! if(!RxInProgress){
! if(!TxInProgress){
//if we're neither transmitting nor receiving, setup the port how we want it be setup
CKEN |= (CKEN23_SSP1);
***************
*** 320,324 ****
//go
! gRxInProgress = TRUE;
return SUCCESS;
}
--- 328,334 ----
//go
! atomic{
! gRxInProgress = TRUE;
! }
return SUCCESS;
}
***************
*** 327,332 ****
//transaction is in progress...return FAIL...(equivalent to the port being already opened)
}
! return FAIL;
! }
command result_t BulkTxRx.BulkTransmit(uint8_t *TxBuffer, uint16_t NumBytes){
--- 337,342 ----
//transaction is in progress...return FAIL...(equivalent to the port being already opened)
}
! return FAIL;
! }
command result_t BulkTxRx.BulkTransmit(uint8_t *TxBuffer, uint16_t NumBytes){
***************
*** 335,377 ****
command result_t SingleTxRx.startReceive(){
! uint32_t SSCR0, SSCR1;
! bool RxInProgress, TxInProgress;
! atomic{
! RxInProgress = gRxInProgress;
! TxInProgress = gTxInProgress;
! }
! if(!RxInProgress){
! if(!TxInProgress){
! //if we're neither transmitting nor receiving, setup the port how we want it be setup
! TOSH_SET_YELLOW_LED_PIN();
! gNumRxFifoOverruns=0;
! SSCR0 = createSSCR0() | SSCR0_SSE;
! //create SSCR1 and enable the RX fifo interrupt only!!
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1 | SSCR1_RIE);
! atomic gRxInProgress = TRUE;
! call SSPInterrupt.enable();
! //go
! CKEN |= (CKEN23_SSP1);
! call HPLSSP.setSSCR0(SSCR0);
! if(gMasterSFRM == TRUE){
! while((call HPLSSP.getSSSR()) & SSSR_CSS); //wait for the clock synchonization
! }
! return SUCCESS;
! }
! else{//tx is in progress but RX is not..just turn on the RX interrupt
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1 | SSCR1_RIE);
! atomic gRxInProgress = TRUE;
! return SUCCESS;
! }
! }
! else{
! //transaction is in progress...return FAIL...(equivalent to the port being already opened)
! return FAIL;
! }
}
--- 345,387 ----
command result_t SingleTxRx.startReceive(){
! uint32_t SSCR0, SSCR1;
! bool RxInProgress, TxInProgress;
! atomic{
! RxInProgress = gRxInProgress;
! TxInProgress = gTxInProgress;
! }
! if(!RxInProgress){
! if(!TxInProgress){
! //if we're neither transmitting nor receiving, setup the port how we want it be setup
! TOSH_SET_YELLOW_LED_PIN();
! gNumRxFifoOverruns=0;
! SSCR0 = createSSCR0() | SSCR0_SSE;
! //create SSCR1 and enable the RX fifo interrupt only!!
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1 | SSCR1_RIE);
! atomic gRxInProgress = TRUE;
! call SSPInterrupt.enable();
! //go
! CKEN |= (CKEN23_SSP1);
! call HPLSSP.setSSCR0(SSCR0);
! if(gMasterSFRM == TRUE){
! while((call HPLSSP.getSSSR()) & SSSR_CSS); //wait for the clock synchonization
! }
! return SUCCESS;
! }
! else{//tx is in progress but RX is not..just turn on the RX interrupt
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1 | SSCR1_RIE);
! atomic gRxInProgress = TRUE;
! return SUCCESS;
! }
! }
! else{
! //transaction is in progress...return FAIL...(equivalent to the port being already opened)
! return FAIL;
! }
}
***************
*** 379,383 ****
command result_t SingleTxRx.stopReceive(){
uint32_t SSCR1, SSCR0;
! gRxInProgress = FALSE;
if(!gTxInProgress){
//if we're neither transmitting nor receiving, kill everything
--- 389,393 ----
command result_t SingleTxRx.stopReceive(){
uint32_t SSCR1, SSCR0;
! atomic gRxInProgress = FALSE;
if(!gTxInProgress){
//if we're neither transmitting nor receiving, kill everything
***************
*** 403,407 ****
}
return SUCCESS;
! }
command result_t SingleTxRx.transmit(uint32_t data){
--- 413,417 ----
}
return SUCCESS;
! }
command result_t SingleTxRx.transmit(uint32_t data){
***************
*** 459,463 ****
//atomic
//uint16_t data;
! {
while(SSSR_1 & SSSR_RNE){
//while fifo not empty
--- 469,473 ----
//atomic
//uint16_t data;
! {
while(SSSR_1 & SSSR_RNE){
//while fifo not empty
***************
*** 496,504 ****
async event void RxDMAChannel.Interrupt(){
uint32_t SSCR0;
- uint8_t *newBuffer;
//invlidate the DCache so that we can bring our data in
invalidateDCache((uint8_t *)gRxBuffer, gRxNumBytes);
! gRxBuffer = (uint8_t *)signal BulkTxRx.BulkReceiveDone((uint8_t *)gRxBuffer,
gRxNumBytes);
if(gRxBuffer){
--- 506,513 ----
async event void RxDMAChannel.Interrupt(){
uint32_t SSCR0;
//invlidate the DCache so that we can bring our data in
invalidateDCache((uint8_t *)gRxBuffer, gRxNumBytes);
! gRxBuffer = (uint16_t *)signal BulkTxRx.BulkReceiveDone((uint8_t *)gRxBuffer,
gRxNumBytes);
if(gRxBuffer){
***************
*** 514,518 ****
}
! gRxInProgress = FALSE;
SSCR0 = call HPLSSP.getSSCR0();
SSCR0 &= ~SSCR0_SSE;
--- 523,527 ----
}
! atomic gRxInProgress = FALSE;
SSCR0 = call HPLSSP.getSSCR0();
SSCR0 &= ~SSCR0_SSE;
Index: SettingsC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SettingsC.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** SettingsC.nc 18 Oct 2005 20:59:16 -0000 1.1
--- SettingsC.nc 8 Dec 2005 23:13:06 -0000 1.2
***************
*** 47,55 ****
}
implementation{
! components SettingsM, BluSHC, UIDC;
StdControl = SettingsM;
SettingsM.UID->UIDC;
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.NodeID;
!
}
--- 47,64 ----
}
implementation{
! components SettingsM, BluSHC, UIDC, CC2420ControlM, SleepC;
StdControl = SettingsM;
SettingsM.UID->UIDC;
+ #ifdef RADIO_DEBUG
+ SettingsM.CC2420Control->CC2420ControlM;
+ #endif
+ SettingsM.Sleep->SleepC;
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.NodeID;
! BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.TestTaskQueue;
! #ifdef RADIO_DEBUG
! BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.SetRadioChannel;
! BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.GetRadioChannel;
! #endif
! BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.GoToSleep;
}
Index: SettingsM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SettingsM.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** SettingsM.nc 18 Oct 2005 20:59:16 -0000 1.1
--- SettingsM.nc 8 Dec 2005 23:13:06 -0000 1.2
***************
*** 52,58 ****
--- 52,68 ----
interface StdControl;
interface BluSH_AppI as NodeID;
+ interface BluSH_AppI as TestTaskQueue;
+ #ifdef RADIO_DEBUG
+ interface BluSH_AppI as SetRadioChannel;
+ interface BluSH_AppI as GetRadioChannel;
+ #endif
+ interface BluSH_AppI as GoToSleep;
}
uses {
interface UID;
+ #ifdef RADIO_DEBUG
+ interface CC2420Control;
+ #endif
+ interface Sleep;
}
}
***************
*** 77,80 ****
--- 87,94 ----
}
+ task void testQueue() {
+ trace(DBG_USR1,"Task Executed\r\n");
+ }
+
command BluSH_result_t NodeID.getName(char *buff, uint8_t len) {
const char name[] = "NodeID";
***************
*** 88,90 ****
--- 102,188 ----
return BLUSH_SUCCESS_DONE;
}
+
+ command BluSH_result_t TestTaskQueue.getName(char *buff, uint8_t len) {
+ const char name[] = "TestTaskQueue";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t TestTaskQueue.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ post testQueue();
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ #if 0
+ command BluSH_result_t SetDebugMode.getName(char *buff, uint8_t len) {
+ const char name[] = "SetDebugMode";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t SetDebugMode.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ return BLUSH_SUCCESS_DONE;
+ }
+ #endif
+
+ #ifdef RADIO_DEBUG
+ command BluSH_result_t SetRadioChannel.getName(char *buff, uint8_t len) {
+ const char name[] = "SetRadioChannel";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t SetRadioChannel.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ uint32_t radio_channel;
+
+ if(strlen(cmdBuff) <17) {
+ sprintf(resBuff,"SetRadioChannel <channel number>\r\n");
+ } else {
+ sscanf(cmdBuff,"SetRadioChannel %d", &radio_channel);
+ call CC2420Control.TunePreset((uint16_t) radio_channel);
+ }
+
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t GetRadioChannel.getName(char *buff, uint8_t len) {
+ const char name[] = "GetRadioChannel";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t GetRadioChannel.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ uint32_t radio_channel;
+
+ radio_channel = (uint32_t) call CC2420Control.GetPreset();
+ trace(DBG_USR1,"Channel is %d\r\n", radio_channel);
+
+ return BLUSH_SUCCESS_DONE;
+ }
+ #endif
+
+ command BluSH_result_t GoToSleep.getName(char *buff, uint8_t len) {
+ const char name[] = "GoToSleep";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t GoToSleep.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ uint32_t sleep_time;
+
+ if(strlen(cmdBuff) < 11) {
+ sprintf(resBuff,"GoToSleep <Sleep time in seconds>\r\n");
+ } else {
+ sscanf(cmdBuff,"GoToSleep %d", &sleep_time);
+ call Sleep.goToDeepSleep(sleep_time);
+ }
+
+ return BLUSH_SUCCESS_DONE;
+ }
+
}
Index: TrickleM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/TrickleM.nc,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** TrickleM.nc 19 Sep 2005 20:54:01 -0000 1.6
--- TrickleM.nc 8 Dec 2005 23:13:06 -0000 1.7
***************
*** 126,130 ****
}
! typedef uint8_t (*binaryMoverFunc)(uint32_t addr, uint32_t size);
binaryMoverFunc binaryMover;
--- 126,130 ----
}
! typedef uint8_t (*binaryMoverFunc)(uint32_t addr, uint32_t size) __attribute__((long_call));
binaryMoverFunc binaryMover;
Index: UARTBufferC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/UARTBufferC.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** UARTBufferC.nc 18 Oct 2005 21:11:20 -0000 1.2
--- UARTBufferC.nc 8 Dec 2005 23:13:06 -0000 1.3
***************
*** 7,11 ****
}
implementation {
! components UARTBufferM, DebugUART;
Control = UARTBufferM;
--- 7,11 ----
}
implementation {
! components UARTBufferM, UART;
Control = UARTBufferM;
***************
*** 13,17 ****
ReceiveData = UARTBufferM;
! UARTBufferM.ByteComm -> DebugUART;
! UARTBufferM.ByteControl -> DebugUART;
}
--- 13,17 ----
ReceiveData = UARTBufferM;
! UARTBufferM.ByteComm -> UART;
! UARTBufferM.ByteControl -> UART;
}
Index: UARTBufferM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/UARTBufferM.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** UARTBufferM.nc 26 Jul 2005 01:37:37 -0000 1.2
--- UARTBufferM.nc 8 Dec 2005 23:13:06 -0000 1.3
***************
*** 64,68 ****
#define NEXT_BUFFER(ent, max) (((ent) >= ((max) - 1)) ? 0 : ((ent) + 1))
! #define BUFFER_SIZE 400 // maximum characters buffered in the queue
char Buffer[BUFFER_SIZE]; // circular buffer of characters
--- 64,68 ----
#define NEXT_BUFFER(ent, max) (((ent) >= ((max) - 1)) ? 0 : ((ent) + 1))
! #define BUFFER_SIZE 1000 // maximum characters buffered in the queue
char Buffer[BUFFER_SIZE]; // circular buffer of characters
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