[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x pxa27x_registers.h, 1.1, 1.2

[Philip Buonadonna]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv5865

Modified Files:
	pxa27x_registers.h 
Log Message:
- Added UART registers bit definitions


Index: pxa27x_registers.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/pxa27x_registers.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** pxa27x_registers.h	13 Nov 2004 01:12:40 -0000	1.1
--- pxa27x_registers.h	19 Jan 2005 02:06:14 -0000	1.2
***************
*** 528,531 ****
--- 528,600 ----
  #define BTACR	_PXAREG(0x4020002C) /* Auto-Baud Count register 10-24 */
  
+ #define IER_DMAE	(1 << 7)	/* DMA Requests Enable */
+ #define IER_UUE		(1 << 6)	/* UART Unit Enable */
+ #define IER_NRZE	(1 << 5)	/* NRZ coding Enable */
+ #define IER_RTIOE	(1 << 4)	/* Receiver Time Out Interrupt Enable */
+ #define IER_MIE		(1 << 3)	/* Modem Interrupt Enable */
+ #define IER_RLSE	(1 << 2)	/* Receiver Line Status Interrupt Enable */
+ #define IER_TIE		(1 << 1)	/* Transmit Data request Interrupt Enable */
+ #define IER_RAVIE	(1 << 0)	/* Receiver Data Available Interrupt Enable */
+ 
+ #define IIR_FIFOES1	(1 << 7)	/* FIFO Mode Enable Status */
+ #define IIR_FIFOES0	(1 << 6)	/* FIFO Mode Enable Status */
+ #define IIR_TOD		(1 << 3)	/* Time Out Detected */
+ #define IIR_IID2	(1 << 2)	/* Interrupt Source Encoded */
+ #define IIR_IID1	(1 << 1)	/* Interrupt Source Encoded */
+ #define IIR_IP		(1 << 0)	/* Interrupt Pending (active low) */
+ 
+ #define FCR_ITL(_x)	((_x) << 6)	/* Interrupt Trigger Level */
+ #define FCR_BUS		(1 << 5)	/* 32-Bit Peripheral Bus */
+ #define FCR_TRAIL	(1 << 4)	/* Trailing Bytes */
+ #define FCR_TIL		(1 << 3)	/* Transmitter Interrupt Level */
+ #define FCR_RESETTF	(1 << 2)	/* Reset Transmitter FIFO */
+ #define FCR_RESETRF	(1 << 1)	/* Reset Receiver FIFO */
+ #define FCR_TRFIFOE	(1 << 0)	/* Transmit and Receive FIFO Enable */
+ 
+ #define ABR_ABT		(1 << 3)	/* Auto-Baud Rate Calculation */
+ #define ABR_ABUP	(1 << 2)	/* Auto-Baud Programmer */
+ #define ABR_ABLIE	(1 << 1)	/* Auto-Baud Interrupt */
+ #define ABR_ABE		(1 << 0)	/* Auto-Baud Enable */
+ 
+ #define LCR_DLAB	(1 << 7)	/* Divisor Latch Access */
+ #define LCR_SB		(1 << 6)	/* Set Break */
+ #define LCR_STKYP	(1 << 5)	/* Sticky Parity */
+ #define LCR_EPS		(1 << 4)	/* Even Parity Select */
+ #define LCR_PEN		(1 << 3)	/* Parity Enable */
+ #define LCR_STB		(1 << 2)	/* Stop Bit */
+ #define LCR_WLS1	(1 << 1)	/* Word Length Select */
+ #define LCR_WLS0	(1 << 0)	/* Word Length Select */
+ 
+ #define LSR_FIFOE	(1 << 7)	/* FIFO Error Status */
+ #define LSR_TEMT	(1 << 6)	/* Transmitter Empty */
+ #define LSR_TDRQ	(1 << 5)	/* Transmit Data Request */
+ #define LSR_BI		(1 << 4)	/* Break Interrupt */
+ #define LSR_FE		(1 << 3)	/* Framing Error */
+ #define LSR_PE		(1 << 2)	/* Parity Error */
+ #define LSR_OE		(1 << 1)	/* Overrun Error */
+ #define LSR_DR		(1 << 0)	/* Data Ready */
+ 
+ #define MCR_AFE		(1 << 5)	/* Auto-Flow Control Enable */
+ #define MCR_LOOP	(1 << 4)	/* Loopback Mode */
+ #define MCR_OUT2	(1 << 3)	/* OUT2 Signal control */
+ #define MCR_OUT1	(1 << 2)	/* Test Bit */
+ #define MCR_RTS		(1 << 1)	/* Request to Send */
+ #define MCR_DTR		(1 << 0)	/* Data Terminal Ready */
+ 
+ #define MSR_DCD		(1 << 7)	/* Data Carrier Detect */
+ #define MSR_RI		(1 << 6)	/* Ring Indicator */
+ #define MSR_DSR		(1 << 5)	/* Data Set Ready */
+ #define MSR_CTS		(1 << 4)	/* Clear To Send */
+ #define MSR_DDCD	(1 << 3)	/* Delta Data Carrier Detect */
+ #define MSR_TERI	(1 << 2)	/* Trailing Edge Ring Indicator */
+ #define MSR_DDSR	(1 << 1)	/* Delta Data Set Ready */
+ #define MSR_DCTS	(1 << 0)	/* Delta Clear To Send */
+ 
+ #define ISR_RXPL	(1 << 4)	/* Receive Data Polarity */
+ #define ISR_TXPL	(1 << 3)	/* Transmit Data Polarity */
+ #define ISR_XMODE	(1 << 2)	/* Transmit Pulse Width Select */
+ #define ISR_RCVEIR	(1 << 1)	/* Receiver SIR Enable */
+ #define ISR_XMITIR	(1 << 0)	/* Transmitter SIR Enable */
+ 
  
  /******************************************************************************/