[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2 HPLFFUARTC.nc, NONE, 1.1 HPLFFUARTM.nc, NONE, 1.1

Mon Jul 25 18:34:27 PDT 2005

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv26211

Added Files:
	HPLFFUARTC.nc HPLFFUARTM.nc 
Log Message:
low level FFUART driver.  Functionality is the same as what is provided by the STUART module

--- NEW FILE: HPLFFUARTC.nc ---
// $Id: HPLFFUARTC.nc,v 1.1 2005/07/26 01:34:24 radler Exp $

/*									tab:4
 * "Copyright (c) 2000-2003 The Regents of the University  of California.  
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 * Permission to use, copy, modify, and distribute this software and its
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 * two paragraphs and the author appear in all copies of this software.
 * 
 * IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR
 * DIRECT, INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES ARISING OUT
 * OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF THE UNIVERSITY OF
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 * Copyright (c) 2002-2003 Intel Corporation
 * All rights reserved.
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 * This file is distributed under the terms in the attached INTEL-LICENSE     
 * file. If you do not find these files, copies can be found by writing to
 * Intel Research Berkeley, 2150 Shattuck Avenue, Suite 1300, Berkeley, CA, 
 * 94704.  Attention:  Intel License Inquiry.
 */
/*
 *
 * Authors:		Jason Hill, David Gay, Philip Levis
 * Date last modified:  $Id: HPLFFUARTC.nc,v 1.1 2005/07/26 01:34:24 radler Exp $
 *
 */

// The hardware presentation layer. See hpl.h for the C side.
// Note: there's a separate C side (hpl.h) to get access to the avr macros

// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component

/**
 *  @author Robbie Adler
 */
configuration HPLFFUARTC {
  provides interface HPLUART as UART;
}
implementation
{
  components HPLFFUARTM as UARTM, 
      PXA27XInterruptM;

  UART = UARTM; 
  UARTM.Interrupt -> PXA27XInterruptM.PXA27XIrq[PPID_FFUART];
}

--- NEW FILE: HPLFFUARTM.nc ---
/*									tab:4
 *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
 *  downloading, copying, installing or using the software you agree to
 *  this license.  If you do not agree to this license, do not download,
 *  install, copy or use the software.
 *
 *  Intel Open Source License
 *
 *  Copyright (c) 2002 Intel Corporation
 *  All rights reserved.
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
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 *	Redistributions of source code must retain the above copyright
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 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
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 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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 */

// The hardware presentation layer. See hpl.h for the C side.
// Note: there's a separate C side (hpl.h) to get access to the avr macros

// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component
/*
 *@author Robbie Adler
 */

module HPLFFUARTM {
    provides {
        interface HPLUART as UART;
    }
    uses {
        interface PXA27XInterrupt as Interrupt;
    }
}

implementation
{
    uint8_t baudrate = 115200;

    async event void Interrupt.fired(){
      uint8_t error,intSource = FFIIR;
      intSource = (intSource >> 1) & 0x3;
      switch(intSource){
      case 0:
          //MODEM STATUS
          break;
      case 1:
          //TRANSMIT FIFO Wants data
          signal UART.putDone();
          break;
      case 2:
          //Received Data Available
          while(FFLSR & LSR_DR){
              signal UART.get(FFRBR);
          }
          break;
      case 3:
          //Receive Error
          error = FFLSR;
          break;
      }
      return;
    }

    async command result_t UART.init() {

        /*** 
           need to configure the FF UART pins for the correct functionality

           GPIO<46> = STDRXD = ALT2(in)
           GPIO<47> = STDTXD = ALT1(out)
        *********/
        //atomic{

            //configure the GPIO Alt functions and directions
      _PXA_setaltfn(96,3, GPIO_IN);
      _PXA_setaltfn(99,3, GPIO_OUT); //FFTXD

        FFLCR |=LCR_DLAB; //turn on DLAB so we can change the divisor
        FFDLL = 8;  //configure to 115200;
        FFDLH = 0;
        FFLCR &= ~(LCR_DLAB);  //turn off DLAB

        FFLCR |= 0x3; //configure to 8 bits

        FFMCR &= ~MCR_LOOP;
        FFMCR |= MCR_OUT2;
        FFIER |= IER_RAVIE;
        FFIER |= IER_TIE;
        FFIER |= IER_UUE; //enable the UART

        //STMCR |= MCR_AFE; //Auto flow control enabled;
        //STMCR |= MCR_RTS;

        FFFCR |= FCR_TRFIFOE; //enable the fifos

        call Interrupt.allocate();
        call Interrupt.enable();
        //configure all the interrupt stuff
        //make sure that the interrupt causes an IRQ not an FIQ
        // __REG(0x40D00008) &= ~(1<<21);
        //configure the priority as IPR1
        //__REG(0x40D00020) = (1<<31 | 21);
        //unmask the interrupt
        //__REG(0x40D00004) |= (1<<21);

        CKEN |= CKEN6_FFUART; //enable the UART's clk
	    // }
        return SUCCESS;
    }

    command result_t UART.setRate(uint8_t newbaudrate){
        return SUCCESS;
    }

    async command result_t UART.stop() {
        CKEN &= ~CKEN6_FFUART;
        return SUCCESS;
    }

    async command result_t UART.put(uint8_t data) {
        FFTHR = data;
        return SUCCESS;
    }

    default async event result_t UART.get(uint8_t data) { return SUCCESS; }

    default async event result_t UART.putDone() { return SUCCESS; }

}