[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x pxa27x_registers.h, 1.4, 1.5

[Robbie Adler]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv27355

Modified Files:
	pxa27x_registers.h 
Log Message:
added additional register bit defintions for missing SSP port registers and an additional helper macro or 2

Index: pxa27x_registers.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/pxa27x_registers.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** pxa27x_registers.h	11 Mar 2005 18:44:42 -0000	1.4
--- pxa27x_registers.h	26 Jul 2005 01:40:11 -0000	1.5
***************
*** 1084,1087 ****
--- 1084,1098 ----
     _GAFR((_gp)) = ((_GAFR((_gp)) & ~(_GPIO_fn((_gp),3))) | (_GPIO_fn((_gp),(_fn))))
  
+ #define GPIO_OUT 1
+ #define GPIO_IN 0
+ 
+ #define _PXA_setaltfn(_gp,_fn,_dir) \
+ { _GPDR(_gp) = (_dir==GPIO_OUT)? (_GPDR(_gp) |  _GPIO_bit(_gp)) : (_GPDR(_gp) & ~_GPIO_bit(_gp)); _GPIO_setaltfn(_gp,_fn);}
+ 
+ #define _PXA_setgpio(_gp) \
+ {_GPSR(_gp) = _GPIO_bit(_gp);}
+ 
+ #define _PXA_clrgpio(_gp) \
+ {_GPCR(_gp) = _GPIO_bit(_gp);}
  
  /******************************************************************************/
***************
*** 1202,1209 ****
  
  // SSP Bit positions. THESE ARE ALSO VALID FOR SSP2 AND SSP3
! #define SSCRO_MOD	(1 << 31)	  /* Mode Network Mode Enable */
  #define SSCR0_ACS	(1 << 30)	  /* Audio Clock Select */
  #define SSCR0_FRDC(_x)  (((_x) & 0x7) << 24)      /* Frame Rate Divider Control value */
! #define SSCRO_TIM	(1 << 23)	  /* Transmit FIFO underrun interrupt mask */
  #define SSCR0_RIM	(1 << 22)	  /* Receive FIFO overrun interrupt mask */
  #define SSCR0_NCS	(1 << 21)	  /* Network Clock select */
--- 1213,1220 ----
  
  // SSP Bit positions. THESE ARE ALSO VALID FOR SSP2 AND SSP3
! #define SSCR0_MOD	(1 << 31)	  /* Mode Network Mode Enable */
  #define SSCR0_ACS	(1 << 30)	  /* Audio Clock Select */
  #define SSCR0_FRDC(_x)  (((_x) & 0x7) << 24)      /* Frame Rate Divider Control value */
! #define SSCR0_TIM	(1 << 23)	  /* Transmit FIFO underrun interrupt mask */
  #define SSCR0_RIM	(1 << 22)	  /* Receive FIFO overrun interrupt mask */
  #define SSCR0_NCS	(1 << 21)	  /* Network Clock select */
***************
*** 1256,1259 ****
--- 1267,1284 ----
  #define SSSR_TNF	(1 << 2)	 /* TX FIFO Not Full */
  
+ #define SSPSP_FSRT      (1 << 25)        /* Frame Sync Relative Timing */
+ #define SSPSP_DMYSTOP(_x) (((_x) & 0x3) << 23)	 /* Dummy Stop */
+ #define SSPSP_SFRMWDTH(_x)    (((_x) & 0x3F) << 16) /* Serial Frame width*/
+ #define SSPSP_SFRMDLY(_x)    (((_x) & 0x7F) << 9) /* Serial Frame delay*/
+ #define SSPSP_DMYSTRT(_x)    (((_x) & 0x3) << 7) /* Dummy Start*/
+ #define SSPSP_STRTDLY(_x)    (((_x) & 0x7) << 4) /* Start Delay*/
+ #define SSPSP_ETDS      (1 << 3)        /* End-of-Transfer Data State*/
+ #define SSPSP_SFRMP     (1 << 2)        /* Serial Frame Polarity */
+ #define SSPSP_SCMODE(_x)    (((_x) & 0x3)) /* Serial Bit-Rate Clock mode*/
+ 
+ #define SSACD_ACPS(_x)    (((_x) & 0x7) << 4) /* Audio Clock PLL Select */
+ #define SSACD_SCDB        (1 << 3) /* Audio Clock PLL Select */
+ #define SSACD_ACDS(_x)    (((_x) & 0x7)) /* Audio Clock Divider Select */
+ 
  
  /******************************************************************************/