[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x PXA27XDMAC.nc, NONE, 1.1 PXA27XDMAChannel.nc, NONE, 1.1 PXA27XDMAExtReq.nc, NONE, 1.1 PXA27XDMAM.nc, NONE, 1.1

Philip Buonadonna philipb at users.sourceforge.net
Mon Mar 28 09:13:38 PST 2005


Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv14590

Added Files:
	PXA27XDMAC.nc PXA27XDMAChannel.nc PXA27XDMAExtReq.nc 
	PXA27XDMAM.nc 
Log Message:
- Initial add of DMA components


--- NEW FILE: PXA27XDMAC.nc ---
// $Id: PXA27XDMAC.nc,v 1.1 2005/03/28 17:13:36 philipb Exp $ 

/*									tab:4
 *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
 *  downloading, copying, installing or using the software you agree to
 *  this license.  If you do not agree to this license, do not download,
 *  install, copy or use the software.
 *
 *  Intel Open Source License 
 *
 *  Copyright (c) 2002 Intel Corporation 
 *  All rights reserved. 
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
 * 
 *	Redistributions of source code must retain the above copyright
 *  notice, this list of conditions and the following disclaimer.
 *	Redistributions in binary form must reproduce the above copyright
 *  notice, this list of conditions and the following disclaimer in the
 *  documentation and/or other materials provided with the distribution.
 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
 *  
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 *  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE INTEL OR ITS
 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * 
 */
/*
 *
 * Authors:		Phil Buonadonna
 */

configuration PXA27XDMAC
{
  provides {
    interface StdControl;
    interface PXA27XDMAChannel[uint8_t channel];
    interface PXA27XDMAExtReq[uint8_t pin];
    async command uint32_t getDPCSR();
    async command void setDPCSR(uint32_t val);
  }
}

implementation
{
  components PXA27XDMAM, PXA27XInterruptM;

  StdControl = PXA27XDMAM;
  PXA27XDMAChannel = PXA27XDMAM;
  PXA27XDMAExtReq = PXA27XDMAM;
  getDPCSR = PXA27XDMAM;
  setDPCSR = PXA27XDMAM;

  PXA27XDMAM.DMAIrq -> PXA27XInterruptM.PXA27XIrq[PPID_DMAC];

}


--- NEW FILE: PXA27XDMAChannel.nc ---
// $Id: PXA27XDMAChannel.nc,v 1.1 2005/03/28 17:13:36 philipb Exp $ 

/*									tab:4
 *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
 *  downloading, copying, installing or using the software you agree to
 *  this license.  If you do not agree to this license, do not download,
 *  install, copy or use the software.
 *
 *  Intel Open Source License 
 *
 *  Copyright (c) 2002 Intel Corporation 
 *  All rights reserved. 
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
 * 
 *	Redistributions of source code must retain the above copyright
 *  notice, this list of conditions and the following disclaimer.
 *	Redistributions in binary form must reproduce the above copyright
 *  notice, this list of conditions and the following disclaimer in the
 *  documentation and/or other materials provided with the distribution.
 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
 *  
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 *  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE INTEL OR ITS
 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * 
 */
/*
 *
 * Authors:		Phil Buonadonna
 */


interface PXA27XDMAChannel 
{
  
  async command result_t setMap(uint8_t device);
  async command uint8_t getMap();

  async command void setByteAlignment(uint8_t val);

  async command void setDCSR(uint32_t val);
  async command uint32_t getDCSR();
  async command void setDCMD(uint32_t val);
  async command uint32_t getDCMD();
  async command void setDDADR(uint32_t val);
  async command uint32_t getDDADR();
  async command void setDSADR(uint32_t val);
  async command uint32_t getDSADR();
  async command void setDTADR(uint32_t val);
  async command uint32_t getDTADR();
  
  async event void Interrupt();

}

--- NEW FILE: PXA27XDMAExtReq.nc ---
// $Id: PXA27XDMAExtReq.nc,v 1.1 2005/03/28 17:13:36 philipb Exp $ 

/*									tab:4
 *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
 *  downloading, copying, installing or using the software you agree to
 *  this license.  If you do not agree to this license, do not download,
 *  install, copy or use the software.
 *
 *  Intel Open Source License 
 *
 *  Copyright (c) 2002 Intel Corporation 
 *  All rights reserved. 
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
 * 
 *	Redistributions of source code must retain the above copyright
 *  notice, this list of conditions and the following disclaimer.
 *	Redistributions in binary form must reproduce the above copyright
 *  notice, this list of conditions and the following disclaimer in the
 *  documentation and/or other materials provided with the distribution.
 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
 *  
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 *  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE INTEL OR ITS
 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * 
 */
/*
 *
 * Authors:		Phil Buonadonna
 */

interface PXA27XDMAExtReq
{
  async command uint8_t getDREQPend();
  async command void clearDREQPend();
}

--- NEW FILE: PXA27XDMAM.nc ---
// $Id: PXA27XDMAM.nc,v 1.1 2005/03/28 17:13:36 philipb Exp $ 

/*									tab:4
 *  IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.  By
 *  downloading, copying, installing or using the software you agree to
 *  this license.  If you do not agree to this license, do not download,
 *  install, copy or use the software.
 *
 *  Intel Open Source License 
 *
 *  Copyright (c) 2002 Intel Corporation 
 *  All rights reserved. 
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions are
 *  met:
 * 
 *	Redistributions of source code must retain the above copyright
 *  notice, this list of conditions and the following disclaimer.
 *	Redistributions in binary form must reproduce the above copyright
 *  notice, this list of conditions and the following disclaimer in the
 *  documentation and/or other materials provided with the distribution.
 *      Neither the name of the Intel Corporation nor the names of its
 *  contributors may be used to endorse or promote products derived from
 *  this software without specific prior written permission.
 *  
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 *  PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE INTEL OR ITS
 *  CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 *  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 *  PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 *  PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 *  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 *  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 *  SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * 
 * 
 */
/*
 *
 * Authors:		Phil Buonadonna
 */


module PXA27XDMAM
{
  provides {
    interface StdControl;
    interface PXA27XDMAChannel[uint8_t channel];
    interface PXA27XDMAExtReq[uint8_t pin];
    async command uint32_t getDPCSR();
    async command void setDPCSR(uint32_t val);
  }

  uses {
    interface PXA27XInterrupt as DMAIrq;
  }
}

implementation
{
  uint8_t mDeviceMap[32];
  bool mfInitialized = FALSE;

  command result_t StdControl.init() 
  {
    bool isInited;
    int i;
    atomic {
      isInited = mfInitialized;
      mfInitialized = TRUE;
    }

    if (!isInited) {
      atomic {
	for (i = 0;i < 32;i++) {
	  mDeviceMap[i] = -1;
	}
      }
      call DMAIrq.allocate();
    }

    return SUCCESS;
  }

  command result_t StdControl.start()
  {
    result_t result = FAIL;
    if (mfInitialized == TRUE) {
      call DMAIrq.enable();
      result = SUCCESS;
    }
    return result;
  }

  command result_t StdControl.stop()
  {
    return SUCCESS;
  }

  async command result_t PXA27XDMAChannel.setMap[uint8_t channel](uint8_t device) 
  {
    result_t result = FAIL;
    
    if ((channel < 32) && ((device < 70) || (device == 74))) {
      uint32_t oldDevice;
      atomic oldDevice = mDeviceMap[channel];
      if (oldDevice != -1) {
	DRCMR(oldDevice) &= ~(DRCMR_MAPVLD);
      }
      DRCMR(device) = (DRCMR_MAPVLD | DRCMR_CHLNUM(channel));
      atomic mDeviceMap[channel] = device;
      result=SUCCESS;
    }
    return result;
  }

  async command uint8_t PXA27XDMAChannel.getMap[uint8_t channel]() 
  {
    if (channel < 32) {
      int dev;
      atomic dev = mDeviceMap[channel];
      return dev;
    }
  }

  async command void PXA27XDMAChannel.setByteAlignment[uint8_t channel](bool flag) 
  {
    if (channel < 32) {
      if (flag) {
	DALGN |= (1 << channel);
      }
      else {
	DALGN &= ~(1 << channel);
      }
    }
    return;
  }

  async command void PXA27XDMAChannel.setDCSR[uint8_t channel](uint32_t val) 
  {
    if (channel < 32) {
      DCSR(channel) = val;
    }
    return;
  }

  async command uint32_t PXA27XDMAChannel.getDCSR[uint8_t channel]() 
  {
    uint32_t val;
    if (channel < 32) {
      val = DCSR(channel);
    }
    return val;
  }

  async command void PXA27XDMAChannel.setDCMD[uint8_t channel](uint32_t val) 
  {
    if (channel < 32) {
      DCMD(channel) = val;
    }
    return;
  }

  async command uint32_t PXA27XDMAChannel.getDCMD[uint8_t channel]() 
  {
    uint32_t val;
    if (channel < 32) {
      val = DCMD(channel);
    }
    return val;
  }

  async command void PXA27XDMAChannel.setDDADR[uint8_t channel](uint32_t val) 
  {
    if (channel < 32) {
      DDADR(channel) = val;
    }
    return;
  }

  async command uint32_t PXA27XDMAChannel.getDDADR[uint8_t channel]() 
  {
    uint32_t val;
    if (channel < 32) {
      val = DDADR(channel);
    }
    return val;
  }

  async command void PXA27XDMAChannel.setDSADR[uint8_t channel](uint32_t val) 
  {
    if (channel < 32) {
      DSADR(channel) = val;
    }
    return;
  }

  async command uint32_t PXA27XDMAChannel.getDSADR[uint8_t channel]() 
  {
    uint32_t val;
    if (channel < 32) {
      val = DSADR(channel);
    }
    return val;
  }

  async command void PXA27XDMAChannel.setDTADR[uint8_t channel](uint32_t val) 
  {
    if (channel < 32) {
      DTADR(channel) = val;
    }
    return;
  }

  async command uint32_t PXA27XDMAChannel.getDTADR[uint8_t channel]() 
  {
    uint32_t val;
    if (channel < 32) {
      val = DTADR(channel);
    }
    return val;
  }

  async command uint8_t PXA27XDMAExtReq.getDREQPend[uint8_t pin]() 
  {
    uint8_t val;
    if (pin < 3) {
      atomic val = (DRQSR(pin) & 0x1F);
    }
    return val;
  }

  async command void PXA27XDMAExtReq.clearDREQPend[uint8_t pin]()
  {
    if (pin < 3) {
      atomic DRQSR(pin) = DRQSR_CLR;
    }
    return;
  }

  async command uint32_t getDPCSR()
  {
    return DPCSR;
  }

  async command void setDPCSR(uint32_t val)
  {
    DPCSR = val;
    return;
  }

  async event void DMAIrq.fired()
  {
    uint32_t IntReg;

    atomic IntReg = DINT;
    while (IntReg) {
      uint32_t channel;
      channel = 31 - _pxa27x_clzui(IntReg);
      if (channel < 32) {
	signal PXA27XDMAChannel.Interrupt[channel]();
	IntReg &= ~(1 << channel);
      }
    }
    return;
  }

  default async event void PXA27XDMAChannel.Interrupt[uint8_t channel]() 
  {
    // Default behavior: clear all potential interrupts on the channel
    if (channel < 32) {
      uint32_t tmp;
      tmp = DCSR(channel);
      tmp |= (DCSR_RASINTR | DCSR_ENDINTR | DCSR_STARTINTR);
      tmp &= ~(DCSR_RUN | DCSR_STOPIRQEN);
      DCMD(channel) = tmp;
    }
    return;
  }



}



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