[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x pxa27x_registers.h, 1.12, 1.13

[Lama Nachman]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv2876

Modified Files:
	pxa27x_registers.h 
Log Message:
Added pxa register definitions


Index: pxa27x_registers.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/pxa27x_registers.h,v
retrieving revision 1.12
retrieving revision 1.13
diff -C2 -d -r1.12 -r1.13
*** pxa27x_registers.h	20 Sep 2005 02:28:58 -0000	1.12
--- pxa27x_registers.h	18 Oct 2005 21:24:42 -0000	1.13
***************
*** 929,932 ****
--- 929,934 ----
  #define UDCCRX	_PXAREG(0x4060045C) /* UDC Configuration register-Endpoint X 12-64 */
  
+ /* UDCCR register */
+ #define UDCCR_UDE (1 << 0)	    /* UDC Enable */
  
  /******************************************************************************/
***************
*** 983,986 ****
--- 985,1005 ----
  #define PIAR	_PXAREG(0x40900038) /* RTC Periodic Interrupt Alarm register 21-23 */
  
+ /* RTSR */
+ #define RTSR_PICE	(1 << 15)  /* periodic interrupt count enable */
+ #define RTSR_PIALE	(1 << 14)  /* periodic interrupt alarm enable */
+ #define RTSR_PIAL	(1 << 13)  /* periodic interrupt alarm status */
+ #define RTSR_SWCE	(1 << 12)  /* stopwatch count enable */
+ #define RTSR_SWALE2	(1 << 11)  /* stopwatch alarm 2 enable */
+ #define RTSR_SWAL2	(1 << 10)  /* stopwatch alarm 2 status */
+ #define RTSR_SWALE1	(1 << 9)   /* stopwatch alarm 1 enable */
+ #define RTSR_SWAL1	(1 << 8)   /* stopwatch alarm 1 status */
+ #define RTSR_RDALE2	(1 << 7)   /* wristwatch alarm 2 enable */
+ #define RTSR_RDAL2	(1 << 6)   /* wristwatch alarm 2 status */
+ #define RTSR_RDALE1	(1 << 5)   /* wristwatch alarm 1 enable */
+ #define RTSR_RDAL1	(1 << 4)   /* wristwatch alarm 1 status */
+ #define RTSR_HZE	(1 << 3)   /* HZ interrupt enable */
+ #define RTSR_ALE	(1 << 2)   /* RTC alarm interrupt enable */
+ #define RTSR_HZ		(1 << 1)   /* HZ rising edge detected */
+ #define RTSR_AL		(1 << 0)   /* RTC alarm detected */
  
  /******************************************************************************/
***************
*** 1277,1280 ****
--- 1296,1303 ----
  #define PWER_WE0	(1 << 0)
  
+ #define PRER_RE1	(1 << 1)
+ 
+ #define PFER_RE1	(1 << 1)
+ 
  #define PCFR_RO		(1 << 15)	/* RDH Override */
  #define PCFR_PO		(1 << 14)	/* PH Override */
***************
*** 1301,1304 ****
--- 1324,1337 ----
  #define PCMD_DATA(_x)	(((_x) & 0xFF)) /* Command Data */
  
+ #define PSLR_SYS_DEL(_x) (((_x) & 0xf) << 28) /* High voltage ramp delay */
+ #define PSLR_PWR_DEL(_x) (((_x) & 0xf) << 24) /* Low voltage ramp delay */
+ #define PSLR_PSSD 	(1 << 23)	      /* Shorten wake-up delay */
+ #define PSLR_IVF 	(1 << 22)	      /* Ignore VDD_FAULT */
+ #define PSLR_SL_ROD 	(1 << 20)	      /*  Don't assert nRESET_OUT */
+ #define PSLR_SL_R3 	(1 << 11)	      /* SRAM bank 3 retains state */
+ #define PSLR_SL_R2 	(1 << 10)	      /* SRAM bank 2 retains state */
+ #define PSLR_SL_R1 	(1 << 9)	      /* SRAM bank 1 retains state */
+ #define PSLR_SL_R0 	(1 << 8)	      /* SRAM bank 0 retains state */
+ #define PSLR_SL_PI(_x) (((_x) & 0x3) << 2)    /* PI power domain */
  
  /******************************************************************************/