[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x HPLInitM.nc, NONE, 1.1

Tue Sep 6 10:50:10 PDT 2005

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv19830

Added Files:
	HPLInitM.nc 
Log Message:
HPLinit.nc renamed to HPLInitM.nc to allow for HPLInit.nc to be a configuration

--- NEW FILE: HPLInitM.nc ---
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/*
 *
 * Authors:		Jason Hill, David Gay, Philip Levis
 * Date last modified:  6/25/02
 *
 */

// The hardware presentation layer. See hpl.h for the C side.
// Note: there's a separate C side (hpl.h) to get access to the avr macros

// The model is that HPL is stateless. If the desired interface is as stateless
// it can be implemented here (Clock, FlashBitSPI). Otherwise you should
// create a separate component

includes MMU;
includes queue;

module HPLInitM {
  provides command result_t init();
}

implementation
{

  queue_t paramtaskQueue __attribute__ ((C));

  command result_t init() {
    CKEN = (CKEN22_MEMC | CKEN20_IMEM | CKEN15_PMI2C | CKEN9_OST);
    OSCC = (OSCC_OON);

    while ((OSCC & OSCC_OOK) == 0);

    TOSH_SET_PIN_DIRECTIONS();
    initqueue(&paramtaskQueue,defaultQueueSize);
#if 1
    //PLACE PXA27X into 104MHz mode....valid bus settings

    CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ; 
    asm volatile (
		  "mcr p14,0,%0,c6,c0,0\n\t"
		  :
		  : "r" (0xb)
		  );
#else
     // Place PXA27X into 13M w/ PPLL enabled...other bits are ignored...but might be useful later
    /*********
	      Don't early enable PLL here.  Page 3-96 of manual says
	      "Write to this bit only when the processor is in 13M mode and the core PLL has
	      been disabled by setting CPDIS.  In normal run mode, writing to this bit causes
	      unpredictable results"
    *******/

    CCCR = (CCCR_CPDIS | CCCR_L(8) | CCCR_2N(2) | CCCR_A);
    asm volatile (
		  "mcr p14,0,%0,c6,c0,0\n\t"
		  :
		  : "r" (0x2)
		  );
#endif

#if 1
    //initialize the memory controller
     //PXA27x MemConttroller 1st tier initialization.See 6.4.10 for details
     SA1110 = SA1110_SXSTACK(1);
     MSC0 = MSC0 | (1<<3) | (1<<15) | 2 ;
     MSC1 = MSC1 | (1<<3);
     MSC2 = MSC2 | (1<<3);

     //PXA27x MemController 2nd tier initialization.See 6.4.10 for details
     MECR =0; //no PC Card is present and 1 card slot
     /*
	 MCMEM0;
	 MCMEM1;
	 MCATT0;
	 MCATT1	 MCIO0;
	 MCIO1;
     */

     //PXA27x MemController 3rd tier initialization.See 6.4.10 for details
     //FLYCNFG

     //PXA27x MemController 4th tier initialization.See 6.4.10 for details
     MDCNFG = 0x0B002BCC; //should be 0x0B002BCD, but we want it disabled.
     //MDREFR;

     //PXA27x MemController 5th tier initialization.See 6.4.10 for details
     //SXCNFG = SXCNFG_SXEN0 | SXCNFG_SXCL0(4) | SXCNFG_SXTP0(3);

      //initialize the MMU
      initMMU();
      enableICache();
      initSyncFlash();
      enableDCache();
      invalidateDCache((uint8_t *)&paramtaskQueue.entries, 0);
      invalidateDCache((uint8_t *)&paramtaskQueue.entries, -1);
      invalidateDCache((uint8_t *)&paramtaskQueue.entries, defaultQueueSize*4);
#endif

      return SUCCESS;
  }
}