[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x HPLInit.nc, 1.5, 1.6

[Robbie Adler]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv20668

Modified Files:
	HPLInit.nc 
Log Message:
HPLInit is now a configuration that wires in some base platfrom services

Index: HPLInit.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/HPLInit.nc,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** HPLInit.nc	18 Aug 2005 23:05:38 -0000	1.5
--- HPLInit.nc	6 Sep 2005 17:54:34 -0000	1.6
***************
*** 74,79 ****
  
  includes GlobalUtil;
  
! module HPLInit {
    provides command result_t init();
  }
--- 74,81 ----
  
  includes GlobalUtil;
+ includes MMU;
+ includes queue;
  
! configuration HPLInit {
    provides command result_t init();
  }
***************
*** 81,204 ****
  implementation
  {
!   result_t pushqueue(queue_t *queue, uint32_t val) __attribute__((C,spontaneous)){
!     //check to see if there is room in the queue
!     uint16_t availableslots = (queue->head <= queue->tail) ? queue->size - queue->tail + queue->head: queue->head - queue->tail;
!     //available entries in the queue is really size-1 since we need to guard against aliasing
!     if(availableslots > 1 ){
!       queue->entries[queue->tail] = val;
!       queue->tail++;
!       if(queue->tail >= queue->size){
! 	queue->tail = 0;
!       }
!       return SUCCESS;
!     }
!     else{
!       return FAIL;
!     }
!   }
!   
!   result_t popqueue(queue_t *queue, uint32_t *val)__attribute__((C,spontaneous)){
!     if(queue->head != queue->tail){
!       *val = queue->entries[queue->head];
!       queue->head++;
!       if(queue->head >= queue->size){
! 	queue->head = 0;
!       }
!       return SUCCESS;
!     }
!     else{
!       *val = 0;
!       //queue is empty
!       return FAIL;
!     }
!   }
!   
!   void initqueue(queue_t *queue, uint32_t size)__attribute__((C,spontaneous)){
!     queue->head = 0;
!     queue->tail = 0;
!     queue->size = size;
!   }
! 
!   extern void initSyncFlash() __attribute__ ((C,spontaneous));
!   extern void initMMU() __attribute__ ((C,spontaneous));
!   extern void enableICache() __attribute__ ((C,spontaneous));
!   extern void enableDCache() __attribute__ ((C,spontaneous));
    
!   command result_t init() {
!     uint32_t tempQueueVal;
!     CKEN = (CKEN22_MEMC | CKEN20_IMEM | CKEN15_PMI2C | CKEN9_OST);
!     OSCC = (OSCC_OON);
!     
!     while ((OSCC & OSCC_OOK) == 0);
!     
!     TOSH_SET_PIN_DIRECTIONS();
!     initqueue(&paramtaskQueue,defaultQueueSize);
!     pushqueue(&paramtaskQueue,0);
!     popqueue(&paramtaskQueue,&tempQueueVal);
! #if 1
!     //PLACE PXA27X into 104MHz mode....valid bus settings
! 
!         
!     CCCR = CCCR_L(8) | CCCR_2N(2) | CCCR_A ; 
!     asm volatile (
! 		  "mcr p14,0,%0,c6,c0,0\n\t"
! 		  :
! 		  : "r" (0xb)
! 		  );
! #else
!      // Place PXA27X into 13M w/ PPLL enabled...other bits are ignored...but might be useful later
!     /*********
! 	      Don't early enable PLL here.  Page 3-96 of manual says
! 	      "Write to this bit only when the processor is in 13M mode and the core PLL has
! 	      been disabled by setting CPDIS.  In normal run mode, writing to this bit causes
! 	      unpredictable results"
!     *******/
!     
!     CCCR = (CCCR_CPDIS | CCCR_L(8) | CCCR_2N(2) | CCCR_A);
!     asm volatile (
! 		  "mcr p14,0,%0,c6,c0,0\n\t"
! 		  :
! 		  : "r" (0x2)
! 		  );
! #endif
!     
! #if 1
!     //initialize the memory controller
!      //PXA27x MemConttroller 1st tier initialization.See 6.4.10 for details
!      SA1110 = SA1110_SXSTACK(1);
!      MSC0 = MSC0 | (1<<3) | (1<<15) | 2 ;
!      MSC1 = MSC1 | (1<<3);
!      MSC2 = MSC2 | (1<<3);
!      
!      //PXA27x MemController 2nd tier initialization.See 6.4.10 for details
!      MECR =0; //no PC Card is present and 1 card slot
!      /*
! 	 MCMEM0;
! 	 MCMEM1;
! 	 MCATT0;
! 	 MCATT1;;
! 	 MCIO0;
! 	 MCIO1;
!      */
!      
!      //PXA27x MemController 3rd tier initialization.See 6.4.10 for details
!      //FLYCNFG
!      
!      //PXA27x MemController 4th tier initialization.See 6.4.10 for details
!      MDCNFG = 0x0B002BCC; //should be 0x0B002BCD, but we want it disabled.
!      //MDREFR;
!      
!      //PXA27x MemController 5th tier initialization.See 6.4.10 for details
!      //SXCNFG = SXCNFG_SXEN0 | SXCNFG_SXCL0(4) | SXCNFG_SXTP0(3);
!          
!       //initialize the MMU
!       initMMU();
!       enableICache();
!       initSyncFlash();
!       enableDCache();
! #endif
!       
!       return SUCCESS;
!   }
  }
  
--- 83,94 ----
  implementation
  {
!   components HPLInitM,
!     BluSHC,
!     TrickleC,
!     Main;
    
!   init=HPLInitM;
!   Main.StdControl->BluSHC;
!   Main.StdControl->TrickleC;
  }