[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
mmu_table.s, 1.2, 1.3
Robbie Adler
radler at users.sourceforge.net
Tue Sep 6 10:55:58 PDT 2005
Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv20987
Modified Files:
mmu_table.s
Log Message:
MMUTable is now selected at compile time via #defines to reduce FLASH footprint. Behavior of specific regions of memory is now based on defines as well
Index: mmu_table.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/mmu_table.s,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** mmu_table.s 18 Aug 2005 23:05:38 -0000 1.2
--- mmu_table.s 6 Sep 2005 17:55:56 -0000 1.3
***************
*** 40,55 ****
! @ write-through table (SDRAM / SRAM Write-through, Flash / ROM banks still write-back)
! @ write-back table
!
@.ALIGN 0x4000
.align 14
! .global MMUTableWT
! MMUTableWT:
.word 0x0000000A @ ROM (x=0,c=1,b=1 => Write-Through)
! .word 0x0010000A
.word 0x0020000A
.word 0x0030000A
--- 40,94 ----
! @set WT to 1 to enable the WT through table, set to 0 to use the WB table
! .equ WT,0
+ @set SRAM_CACHEABLE to 1 to enable either WT or WB caching to internal SRAM
+ .equ SRAM_CACHEABLE,1
+ @disable caching for upper 31M of FLASH so that we can write to it without mucking with page table
+ .equ NO_UPPER_FLASH_CACHE, 1
+
+ .if WT
@.ALIGN 0x4000
.align 14
! @.Write Through Table
! .global MMUTable
! MMUTable:
.word 0x0000000A @ ROM (x=0,c=1,b=1 => Write-Through)
! .if NO_UPPER_FLASH_CACHE
! .word 0x00100002
! .word 0x00200002
! .word 0x00300002
! .word 0x00400002
! .word 0x00500002
! .word 0x00600002
! .word 0x00700002
! .word 0x00800002
! .word 0x00900002
! .word 0x00A00002
! .word 0x00B00002
! .word 0x00C00002
! .word 0x00D00002
! .word 0x00E00002
! .word 0x00F00002
! .word 0x01000002
! .word 0x01100002
! .word 0x01200002
! .word 0x01300002
! .word 0x01400002
! .word 0x01500002
! .word 0x01600002
! .word 0x01700002
! .word 0x01800002
! .word 0x01900002
! .word 0x01A00002
! .word 0x01B00002
! .word 0x01C00002
! .word 0x01D00002
! .word 0x01E00002
! .word 0x01F00002 @ 32 MByte
! .else
! .word 0x0010000A
.word 0x0020000A
.word 0x0030000A
***************
*** 82,86 ****
.word 0x01E0000A
.word 0x01F0000A @ 32 MByte
!
@.ALIGN 0x100 @(0x4100=0x4000+0x040*4)
.align 8
--- 121,125 ----
.word 0x01E0000A
.word 0x01F0000A @ 32 MByte
! .endif
@.ALIGN 0x100 @(0x4100=0x4000+0x040*4)
.align 8
***************
*** 386,392 ****
@// this should get us to 0x5700
! @RA...disable SRAM cacheability until we deal with dynamic DMA/cache interaction problem
! @.word 0x5C00000A @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
.word 0x5C000002 @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
@.ALIGN 0x1000 @// this should get us to 0x6000
--- 425,433 ----
@// this should get us to 0x5700
! .if SRAM_CACHEABLE
! .word 0x5C00000A @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
! .else
.word 0x5C000002 @ 256K internal SRAM (x=0, C=1, b=0 => Write-Through)
+ .endif
@.ALIGN 0x1000 @// this should get us to 0x6000
***************
*** 462,476 ****
.word 0xA3E0000A
.word 0xA3F0000A @ 32 MByte
!
!
!
!
@ write-back table
@.ALIGN 0x4000
.align 14
! .global MMUTableWB
! MMUTableWB:
.word 0x0000000E @ ROM (x=0,c=1,b=1 => Write-Back)
.word 0x0010000E
.word 0x0020000E
--- 503,549 ----
.word 0xA3E0000A
.word 0xA3F0000A @ 32 MByte
! MMUTable_end:
! nop
! .else
@ write-back table
@.ALIGN 0x4000
.align 14
! .global MMUTable
! MMUTable:
.word 0x0000000E @ ROM (x=0,c=1,b=1 => Write-Back)
+ .if NO_UPPER_FLASH_CACHE
+ .word 0x00100002
+ .word 0x00200002
+ .word 0x00300002
+ .word 0x00400002
+ .word 0x00500002
+ .word 0x00600002
+ .word 0x00700002
+ .word 0x00800002
+ .word 0x00900002
+ .word 0x00A00002
+ .word 0x00B00002
+ .word 0x00C00002
+ .word 0x00D00002
+ .word 0x00E00002
+ .word 0x00F00002
+ .word 0x01000002
+ .word 0x01100002
+ .word 0x01200002
+ .word 0x01300002
+ .word 0x01400002
+ .word 0x01500002
+ .word 0x01600002
+ .word 0x01700002
+ .word 0x01800002
+ .word 0x01900002
+ .word 0x01A00002
+ .word 0x01B00002
+ .word 0x01C00002
+ .word 0x01D00002
+ .word 0x01E00002
+ .word 0x01F00002 @ 32 MByte
+ .else
.word 0x0010000E
.word 0x0020000E
***************
*** 504,508 ****
.word 0x01E0000E
.word 0x01F0000E @ 32 MByte
!
@.ALIGN 0x100 @(0x4100=0x4000+0x040*4)
.align 8
--- 577,581 ----
.word 0x01E0000E
.word 0x01F0000E @ 32 MByte
! .endif
@.ALIGN 0x100 @(0x4100=0x4000+0x040*4)
.align 8
***************
*** 807,813 ****
.align 8
@// this should get us to 0x5700
! @RA...disable SRAM cacheability until we deal with dynamic DMA/cache interaction problem
! @.word 0x5C00000E @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
.word 0x5C000002 @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
@.ALIGN 0x1000 @// this should get us to 0x6000
--- 880,888 ----
.align 8
@// this should get us to 0x5700
! .if SRAM_CACHEABLE
! .word 0x5C00000E @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
! .else
.word 0x5C000002 @ 256K internal SRAM (x=0, C=1, b=0 => Write-Back)
+ .endif
@.ALIGN 0x1000 @// this should get us to 0x6000
***************
*** 883,888 ****
.word 0xA3E0000E
.word 0xA3F0000E @ 32 MByte
!
!
!
.END
--- 958,963 ----
.word 0xA3E0000E
.word 0xA3F0000E @ 32 MByte
! MMUTable_end:
! nop
! .endif
.END
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