[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x util.s, 1.2, 1.3

[Robbie Adler]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv21244

Modified Files:
	util.s 
Log Message:
added disableDCache, invalidateDCache, and cleanDCache functions

Index: util.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/util.s,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** util.s	18 Aug 2005 23:05:38 -0000	1.2
--- util.s	6 Sep 2005 17:57:03 -0000	1.3
***************
*** 13,20 ****
  @ .endfunc
  @@@@@@@@@@@@@@@@@@@@@@@@@@
! 	
!   .extern MMUTableWT 
!   .extern MMUTableWB 
! 	
  	.equ	MEMORY_CONFIG_BASE,(0x48000000)      
           .equ	FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode
--- 13,20 ----
  @ .endfunc
  @@@@@@@@@@@@@@@@@@@@@@@@@@
! 
! @whether WT or WB is used is determined in mmu_table.s	
!   .extern MMUTable 
! 		
  	.equ	MEMORY_CONFIG_BASE,(0x48000000)      
           .equ	FLASH_SYNC_value, (0x25C3<<1) @ Value to set flash into burst 16 sync mode
***************
*** 31,36 ****
  	.global initSyncFlash
  	.global enableICache	
! 	.global enableDCache		
! 
  initSyncFlash:
  	@this function MUST be called after the ICACHE is initialized to work correctly!!!
--- 31,38 ----
  	.global initSyncFlash
  	.global enableICache	
! 	.global enableDCache
! 	.global disableDCache		
! 	.global invalidateDCache
! 	
  initSyncFlash:
  	@this function MUST be called after the ICACHE is initialized to work correctly!!!
***************
*** 124,128 ****
  
  	@time to setup the page table base register
! 	LDR R0, =MMUTableWB		@move the table we want into R0
  	MCR P15, 0, R0, C2, C0		@save it     
          CPWAIT	R0			@wait it
--- 126,130 ----
  
  	@time to setup the page table base register
! 	LDR R0, =MMUTable		@move the table we want into R0
  	MCR P15, 0, R0, C2, C0		@save it     
          CPWAIT	R0			@wait it
***************
*** 197,198 ****
--- 199,257 ----
  	MOV     PC,  LR
  .endfunc
+ 
+ disableDCache:
+ .func disableDCache
+ @since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency
+ 	@globally unlock the dcache
+ 	MCR P15, 0, R0, C9, c2, 1
+ 	CPWAIT R0
+ 	
+ 	@invalidate dcache and mini-dcache
+ 	MCR P15, 0, R0, C7, C6, 0
+ 	CPWAIT R0
+ 	
+ 	@ now, enable data cache	
+ 	MCR P15, 0, R0, C7, C10, 4	@drain write buffer
+ 	MRC P15, 0, R0, C1, C0, 0	@get CP15 register 1
+ 	BIC R0, R0, #0x4		@clear the dcache enable bit
+ 	MCR P15, 0, R0, C1, C0, 0	@save it
+ 	CPWAIT R0			@wait it
+ 	MOV     PC,  LR
+ .endfunc
+ 
+ @function to invalidate the DCCache for a given Buffer
+ @funtion take 2 parameters
+ @R0 = base virtual address to evict
+ @R1 = number of bytes to evict...cache line is 32 bytes
+ invalidateDCache:	
+ .func invalidateDCache
+ 	CMPS R1,#0			@check that we're greater than 0
+ 	MOVLE PC, LR			@return if not
+ invalidateDCacheLoop:	
+ 	MCR P15, 0, R0, C7, C6, 1	@invalidate this line
+ 	SUBS R1, R1, #32		@subtract out 32 w/CPSR update
+ 	ADD  R0, R0, #32		@add 32 to the address w/o CPSR update
+ 	BGT invalidateDCacheLoop	@rerun if subtract is greater than
+ 	MOV PC, LR			@return
+ .endfunc
+ 
+ @function to clean the DCCache for a given Buffer
+ @if a line is dirty, it will be cleaned...i.e. written back to memory in WB mode
+ @funtion take 2 parameters
+ @R0 = base virtual address to evict
+ @R1 = number of bytes to evict...cache line is 32 bytes
+ cleanDCache:	
+ .func cleanDCache
+ 	CMPS R1,#0			@check that we're greater than 0
+ 	MOVLE PC, LR			@return if not
+ cleanDCacheLoop:	
+ 	MCR P15, 0, R0, C7, C10, 1	@clean this line
+ 	SUBS R1, R1, #32		@subtract out 32 w/CPSR update
+ 	ADD  R0, R0, #32		@add 32 to the address w/o CPSR update
+ 	BGT cleanDCacheLoop		@rerun if subtract is greater than
+ 	MCR P15, 0, R0, C7, C10, 4	@drain write buffer
+ 	CPWAIT R0			@wait it
+ 	MOV PC, LR			@return
+ .endfunc
+ .end
+ 	
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