[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x pxa27xhardware.h, 1.5, 1.6

[Robbie Adler]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv30042

Modified Files:
	pxa27xhardware.h 
Log Message:
update nesc atomic start to only mess with the IRQ bit instead of potentially the IRQ and FIQ bits

Index: pxa27xhardware.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/pxa27xhardware.h,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** pxa27xhardware.h	2 Sep 2005 23:27:24 -0000	1.5
--- pxa27xhardware.h	6 Sep 2005 18:27:20 -0000	1.6
***************
*** 78,81 ****
--- 78,83 ----
  #include "pxa27x_registers.h"
  
+ 
+ 
  #define TOSH_ASSIGN_PIN(name, port, regbit) \
  static inline void TOSH_SET_##name##_PIN() {_GPSR(regbit) |= _GPIO_bit(regbit);} \
***************
*** 148,151 ****
--- 150,154 ----
  typedef uint32_t __nesc_atomic_t;
  
+ //NOTE...at the moment, these functions will ONLY disable the IRQ...FIQ is left alone
  inline __nesc_atomic_t __nesc_atomic_start(void) __attribute__((spontaneous))
  {
***************
*** 160,164 ****
  		: "0" (result) , "1" (temp) , "i" (ARM_CPSR_INT_MASK)
  		);
- 
    return result;
  }
--- 163,166 ----
***************
*** 167,170 ****
--- 169,174 ----
  {
    uint32_t  statusReg = 0;
+   //make sure that we only mess with the INT bit
+   oldState &= ARM_CPSR_INT_MASK;
    asm volatile (
  		"mrs %0,CPSR\n\t"