[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x util.s,
1.3, 1.4
Robbie Adler
radler at users.sourceforge.net
Fri Sep 9 18:12:01 PDT 2005
Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv24978
Modified Files:
util.s
Log Message:
added globalCleanAndInvalidateDCache function,fixed disableDCache to properly clean the DCache before disabling it (otherwise, we potentially lose data), and some misc additional function stuff
Index: util.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/util.s,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** util.s 6 Sep 2005 17:57:03 -0000 1.3
--- util.s 10 Sep 2005 01:11:59 -0000 1.4
***************
*** 5,8 ****
--- 5,13 ----
SUB PC, PC, #4 @ branch to next instruction
.endm
+
+
+ .macro ALLOCATE Rd
+ MCR P15, 0, \Rd, C7, C2, 5 @ perform line allocation based on Rd
+ .endm
@@@@@@@@@@@@@@@@@@@@@@@@@
@ to create an assembly function that confirms to AAPCS (or so I think ;o)
***************
*** 34,38 ****
.global disableDCache
.global invalidateDCache
!
initSyncFlash:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
--- 39,45 ----
.global disableDCache
.global invalidateDCache
! .global cleanDCache
! .global globalCleanAndInvalidateDCache
!
initSyncFlash:
@this function MUST be called after the ICACHE is initialized to work correctly!!!
***************
*** 64,120 ****
.endfunc
- readFlashStatusRegister:
- @this function MUST be called after the ICACHE is initialized to work correctly!!!
- .func readFlashStatusRegister
- ldr r1, =FLASH_READSTATUS @ read status instruction
- ldr r2, =FLASH_READ @ Load "read array" mode command
- ldr r3, =0x0 @ Boot ROM Flash Base address
- b goReadStatus
-
- @align on cache line so that we fetch the next 8 instructions...
- .align 5
- goReadStatus:
- @ Now program everything into the Flash and SXCNFG registers
- strh r1, [r3] @ Yes, the data is on the address bus!
- ldrh r0, [r3] @ Confirm the write to the RCR
- strh r2, [r3] @ Place flash back in read mode
- ldrh r2, [r3] @ Create a data dependency stall
- @ to guarantee write
- nop @ go to the end of the cache line
- nop
- nop
- nop
- @ Return to caller
- mov PC, LR
- .endfunc
-
- readFlashCFI:
- @this function MUST be called after the ICACHE is initialized to work correctly!!!
- .func readFlashCFI
- STMFD R13!, {R4, PC}
- ldr r1, =0x98 @ read status instruction
- ldr r2, =FLASH_READ @ Load "read array" mode command
- ldr r3, =0x0 @ Boot ROM Flash Base address
- ldr r4, =0x20 @ Boot ROM Flash Base address
- b goReadCFI
-
- @align on cache line so that we fetch the next 8 instructions...
- .align 5
- goReadCFI:
- @ Now program everything into the Flash and SXCNFG registers
- strh r1, [r3] @ Yes, the data is on the bus!
- ldrh r0, [r4] @ read into r0
- strh r2, [r3] @ Place flash back in read mode
- ldrh r2, [r3] @ Create a data dependency stall
- @ to guarantee write
- nop @ go to the end of the cache line
- nop
- nop
- nop
- @ Return to caller
- LDMFD R13!, {R4, PC}
- .endfunc
-
-
@assembly routine to init our MMU
initMMU:
--- 71,74 ----
***************
*** 135,139 ****
MCR P15,0,R0,C1,C0,0 @save it
CPWAIT R0 @wait it
! mov PC, LR @return
.endfunc
--- 89,93 ----
MCR P15,0,R0,C1,C0,0 @save it
CPWAIT R0 @wait it
! MOV PC, LR
.endfunc
***************
*** 167,172 ****
ORR R0, R0, #0x800 @set the btb enable bit
MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR @return
.endfunc
--- 121,126 ----
ORR R0, R0, #0x800 @set the btb enable bit
MCR P15, 0, R0, C1, C0, 0 @save it
! CPWAIT R0 @wait it
! MOV PC, LR
.endfunc
***************
*** 197,201 ****
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
! MOV PC, LR
.endfunc
--- 151,155 ----
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
! MOV PC, LR
.endfunc
***************
*** 204,215 ****
@since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency
@globally unlock the dcache
MCR P15, 0, R0, C9, c2, 1
CPWAIT R0
!
! @invalidate dcache and mini-dcache
! MCR P15, 0, R0, C7, C6, 0
! CPWAIT R0
!
! @ now, enable data cache
MCR P15, 0, R0, C7, C10, 4 @drain write buffer
MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
--- 158,169 ----
@since caching might be WB or WT for a given line, need to invalidate/flush dcache to ensure coherency
@globally unlock the dcache
+ STMFD R13!, {R0, LR}
MCR P15, 0, R0, C9, c2, 1
CPWAIT R0
!
! @globally clean and invalidate the cache
! bl globalCleanAndInvalidateDCache
!
! @ now, disable data cache
MCR P15, 0, R0, C7, C10, 4 @drain write buffer
MRC P15, 0, R0, C1, C0, 0 @get CP15 register 1
***************
*** 217,221 ****
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
! MOV PC, LR
.endfunc
--- 171,175 ----
MCR P15, 0, R0, C1, C0, 0 @save it
CPWAIT R0 @wait it
! LDMFD R13!, {R0, LR}
.endfunc
***************
*** 233,237 ****
ADD R0, R0, #32 @add 32 to the address w/o CPSR update
BGT invalidateDCacheLoop @rerun if subtract is greater than
! MOV PC, LR @return
.endfunc
--- 187,191 ----
ADD R0, R0, #32 @add 32 to the address w/o CPSR update
BGT invalidateDCacheLoop @rerun if subtract is greater than
! MOV PC, LR
.endfunc
***************
*** 252,257 ****
MCR P15, 0, R0, C7, C10, 4 @drain write buffer
CPWAIT R0 @wait it
! MOV PC, LR @return
.endfunc
.end
\ No newline at end of file
--- 206,255 ----
MCR P15, 0, R0, C7, C10, 4 @drain write buffer
CPWAIT R0 @wait it
! MOV PC, LR
! .endfunc
!
!
! @Global Clean/Invalidate THE DATA CACHE
! @R1 contains the virtual address of a region of cacheable memory reserved for
! @this clean operation
! @R0 is the loop count; Iterate 1024 times which is the number of lines in the
! @data cache
!
! globalCleanAndInvalidateDCache:
! .func globalCleanAndInvalidateDCache
! @note, this function assumes that we will NEVER have anything physical at
! @address 0x04000000 corresponds to static chip select 1
! STMFD R13!, {R0 - R3, LR}
! LDR R1, =0x04000000
! MOV R0, #1024
! LOOP1:
!
! ALLOCATE R1 @ Allocate a line at the virtual address
! @ specified by R1.
! SUBS R0, R0, #1 @ Decrement loop count
! ADD R1, R1, #32 @ Increment the address in R1 to the next cache line
! BNE LOOP1
!
! @Clean the Mini-data Cache
! @ Can’t use line-allocate command, so cycle 2KB of unused data through.
! @ R2 contains the virtual address of a region of cacheable memory reserved for
! @ cleaning the Mini-data Cache
! @ R0 is the loop count; Iterate 64 times which is the number of lines in the
! @ Mini-data Cache.
!
! @note, this function assumes that we will NEVER have anything physical at
! @address 0x05000000 corresponds to static chip select 1
! LDR R2, =0x05000000
! MOV R0, #64
! LOOP2:
! SUBS R0, R0, #1 @ Decrement loop count
! LDR R3,[R2],#32 @ Load and increment to next cache line
! BNE LOOP2
!
! @ Invalidate the data cache and mini-data cache
! MCR P15, 0, R0, C7, C6, 0
! LDMFD R13!, {R0 - R3, PC}
.endfunc
+
.end
\ No newline at end of file
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