[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x barecrt.s, 1.2, 1.3

[Robbie Adler]

Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv18576

Modified Files:
	barecrt.s 
Log Message:
added support for hot debug

Index: barecrt.s
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/barecrt.s,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** barecrt.s	6 Sep 2005 17:53:45 -0000	1.2
--- barecrt.s	19 Sep 2005 20:46:14 -0000	1.3
***************
*** 170,178 ****
  	b hplarmv_fiq
  .endif
  	
  	.weak hplarmv_undef, hplarmv_swi, hplarmv_pabort, hplarmv_dabort, hplarmv_reserved, hplarmv_irq, hplarmv_fiq
  
  	.section	.vectors
! 	b	start
  	b	hplarmv_undef
  	b	hplarmv_swi
--- 170,254 ----
  	b hplarmv_fiq
  .endif
+ 
+ reset_handler_start:
+ @ reset handler should first check whether this is a debug exception
+ @ or a real RESET event.
+ @ NOTE: r13 is only safe register to use.
+ @ - For RESET, don’t really care about which register is used
+ @ - For debug exception, r13=DBG_r13, prevents application registers
+ @ - from being corrupted, before debug handler can save.
+ 	mrs r13, cpsr
+ 	and r13, r13, #0x1f
+ 	cmp r13, #0x15			@ are we in DBG mode?
+ 	beq dbg_handler_stub		@ if so, go to the dbg handler stub
+ 	mov r13, #0x8000001c		@ otherwise, enable debug, set MOE bits
+ 	mcr p14, 0, r13, c10, c0, 0	@ and continue with the reset handler
+ @ normal reset handler initialization follows code here,
+ @ or branch to the reset handler.	
+ 	b	start
+ 
+ .align 5 @ align code to a cache line boundary.
+ dbg_handler_stub:
+ @ First save the state of the IC enable/disable bit in DBG_LR[0].
+ 	mrc p15, 0, r13, c1, c0, 0
+ 	and r13, r13, #0x1000
+ 	orr r14, r14, r13, lsr #12
+ @ Next, enable the IC.
+ 	mrc p15, 0, r13, c1, c0, 0
+ 	orr r13, r13, #0x1000
+ 	mcr p15, 0, r13, c1, c0, 0
+ @ do a sync operation to ensure all outstanding instr fetches have
+ @ completed before continuing. The invalidate cache line function
+ @ serves as a synchronization operation, that’s why it is used
+ @ here. The target line is some scratch address in memory.
+ 	adr r13, line2
+ 	mcr p15, 0, r13, c7, c5, 1
+ @ invalidate BTB. make sure downloaded vector table does not hit one of
+ @ the application’s branches cached in the BTB, branch to the wrong place
+ 	mcr p15, 0, r13, c7, c5, 6
+ @ Now, send ‘ready for download’ message to debugger, indicating debugger
+ @ can begin the download. ‘ready for download’ = 0x00B00000.
+ TXloop:
+ 	mrc p14, 0, r15, c14, c0, 0	@ first make sure TX reg. is available
+ 	bvs TXloop
+ 	mov r13, #0x00B00000
+ 	mcr p14, 0, r13, c8, c0, 0	@ now write to TX
+ @ Wait for debugger to indicate that the download is complete.
+ 	RXloop:
+ 	mrc p14, 0, r15, c14, c0, 0	@ spin in loop waiting for data from the
+ 	bpl RXloop			@ debugger in RX.
+ @ before reading the RX register to get the address to branch to, restore
+ @ the state of the IC (saved in DBG_r14[0]) to the value it have at the
+ @ start of the debug handler stub. Also, note it must be restored before	
+ @ reading the RX register because of limited scratch registers (r13)
+ 	mrc p15, 0, r13, c1, c0, 0
+ @ First, check DBG_LR[0] to see if the IC was enabled or disabled
+ 	tst r14, #0x1
+ @ Then, if it was previously disabled, then disable it now, otherwise,
+ @ there’s no need to change the state, because its already enabled.
+ 	biceq r13, r13, #0x1000
+ 	mcr p15, 0, r13, c1, c0, 0
+ @ Restore the link register value
+ 	bic r14, r14, #0x1
+ @ Now r13 can be used to read RX and get the target address to branch to.
+ 	mrc p14, 0, r13, c9, c0, 0	@ Read RX and
+ 	mov pc, r13			@ branch to downloaded address.
+ @ scratch memory space used by the invalidate IC line function above.
+ .align 5 @ make sure it starts at a cache line
+ @ boundary, so nothing else is affected
+ line2:
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word 0	
  	
  	.weak hplarmv_undef, hplarmv_swi, hplarmv_pabort, hplarmv_dabort, hplarmv_reserved, hplarmv_irq, hplarmv_fiq
  
  	.section	.vectors
! 	b	reset_handler_start
  	b	hplarmv_undef
  	b	hplarmv_swi