[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
PXA27XQuickCaptInt.h, NONE, 1.1 PXA27XQuickCaptInt.nc, NONE,
1.1 PXA27XQuickCaptIntC.nc, NONE, 1.1 PXA27XQuickCaptIntM.nc,
NONE, 1.1 PXA27XI2CM.nc, 1.1, 1.2 pxa27x_registers.h, 1.11, 1.12
Konrad Lorincz
konradlorincz at users.sourceforge.net
Mon Sep 19 19:29:00 PDT 2005
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Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x
In directory sc8-pr-cvs1.sourceforge.net:/tmp/cvs-serv28891
Modified Files:
PXA27XI2CM.nc pxa27x_registers.h
Added Files:
PXA27XQuickCaptInt.h PXA27XQuickCaptInt.nc
PXA27XQuickCaptIntC.nc PXA27XQuickCaptIntM.nc
Log Message:
Checked in initial version of the QuickCaptureInterface. Also, updated the I2C module and updated the registers file.
--- NEW FILE: PXA27XQuickCaptInt.h ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2005 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* @author Konrad Lorincz
* @version 1.0, August 15, 2005
*/
#ifndef PXA27XQuickCaptInt_H
#define PXA27XQuickCaptInt_H
/******************************************************************************/
/* Configure the GPIO Alt functions and directions
/* Note:
/* - In Sensor Master-Parallel mode, CIF_FV and CIF_LV are set to INPUTS
/* - In Sensor Slave-Parallel mode, CIF_FV and CIF_LV are set to OUTPUTS
// Configure the GPIO Alt Functions and Directions
// --- Template ----
// _GPIO_setaltfn(PIN, PIN_ALTFN);
// _GPDR(PIN) &= ~_GPIO_bit(PIN); // input
// _GPDR(PIN) |= _GPIO_bit(PIN); // output
// -----------------
/******************************************************************************/
// (1) - Define the Pin mappings (options are listed as <GPIO_PIN#, IN/OUT, ALT_FN#>
#define PIN_CIF_MCLK 23 // <23,O,1> <42,O,3> <53,O,2>
#define PIN_CIF_MCLK_ALTFN 1
#define PIN_CIF_PCLK 26 // <26,I,2> <45,I,3> <54,I,3>
#define PIN_CIF_PCLK_ALTFN 2
#define PIN_CIF_FV 24 // <24,I,1> <24,O,1> <43,I,3> <43,O,3> <84,I,3> <84,O,3>
#define PIN_CIF_FV_ALTFN 1
#define PIN_CIF_LV 25 // <25,I,1> <25,O,1> <44,I,3> <44,O,3> <85,I,3> <85,O,3>
#define PIN_CIF_LV_ALTFN 1
#define PIN_CIF_DD0 81 // <27,I,3> <47,I,1> <81,I,2> <98,I,2>
#define PIN_CIF_DD0_ALTFN 2 // SSPEXTCLK STD_TXD BB_OB_DAT0 FF_RTS
// CIF_DD0 KP_DKIN5
// GPIO27_LED_B
#define PIN_CIF_DD1 55 // <55,I,1> <105,I,1> <114*,I,1>
#define PIN_CIF_DD1_ALTFN 1 // BB_IB_DAT1 KP_MKOUT2 CC2420_FIFO
// NPREG UVS0
#define PIN_CIF_DD2 51 // <51,I,1> <104,I,1> <116*,I,1>
#define PIN_CIF_DD2_ALTFN 1 // BB_OB_DAT3 KP_MKOUT1 CC2420_CCA
// U_DET
#define PIN_CIF_DD3 50 // <50,I,1> <103,I,1> <115*,I,2>
#define PIN_CIF_DD3_ALTFN 1 // BB_OB_DAT2 KP_MKOUT0 CC2420_VREG_EN
// NPIOR U_EN
#define PIN_CIF_DD4 52 // <52,I,1> <83,I,3> <90,I,3> <95,I,2>
#define PIN_CIF_DD4_ALTFN 1 // BB_OB_CLK BB_IB_CLK NURST KP_DKIN2
// GPIO95_LED_R
#define PIN_CIF_DD5 48 // <48,I,1> <82,I,3> <91,I,3> <94,I,2>
#define PIN_CIF_DD5_ALTFN 1 // BB_OB_DAT1 BB_IB_DAT0 UCLK KP_DKIN1
// GPIO94_D_CARD
#define PIN_CIF_DD6 17 // <17,I,2> <93,I,2>
#define PIN_CIF_DD6_ALTFN 2 // CIF_DD6 KP_DKIN0
// PWM_OUT_1 GPIO93_D_CARD
#define PIN_CIF_DD7 12 // <12,I,2> <108,I,1>
#define PIN_CIF_DD7_ALTFN 2 // CIF_DD7 KP_MKOUT5
// 48MHz
#define PIN_CIF_DD8 107 // <107,I,1>
#define PIN_CIF_DD8_ALTFN 1 // CIF_DD8
// KP_MKOUT4
#define PIN_CIF_DD9 106 // <106,I,1>
#define PIN_CIF_DD9_ALTFN 1 // CIF_DD9
// KP_MKOUT3
// ===================================================================
#define CIF_CHAN (11)
#define CIBR0_ADDR (0x50000028)
typedef struct {
uint32_t DDADR;
uint32_t DSADR;
uint32_t DTADR;
uint32_t DCMD;
} DMADescriptor_t;
#define MAX_DESC_TRANSFER 8192
// ----------------------------------------------
#define DescArray_NBR_DESC 8
#define DescArray_BYTE_ALLIGNMENT 16
#define DescArray_BUFFER_SIZE (DescArray_NBR_DESC*sizeof(DMADescriptor_t) + DescArray_BYTE_ALLIGNMENT)
typedef struct DescArray
{
uint8_t data[DescArray_BUFFER_SIZE]; // The data is alligned from data[baseIndex]
} DescArray;
DescArray descArray;
uint32_t DescArray_getBaseIndex(DescArray *DAPtr)
{
uint32_t addr = (uint32_t) (&DAPtr->data[0]);
return DescArray_BYTE_ALLIGNMENT - (addr % DescArray_BYTE_ALLIGNMENT);
}
DMADescriptor_t* DescArray_get(DescArray *DAPtr, uint8_t descIndex)
{
uint32_t baseIndex = DescArray_getBaseIndex(DAPtr);
return &DAPtr->data[baseIndex + descIndex*sizeof(DMADescriptor_t)];
}
#endif
--- NEW FILE: PXA27XQuickCaptInt.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2005 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* Description - PXA27X Quick Capture Interface.
*
* @author Konrad Lorincz
* @version 1.0, August 10, 2005
*/
interface PXA27XQuickCaptInt
{
command void enable();
command void disableQuick();
command result_t setImageSize(uint16_t sizeX, uint16_t sizeY);
command void startDMA();
// Events/Interrupts
command void enableStartOfFrame();
async event void startOfFrame();
command void enableEndOfFrame();
async event void endOfFrame();
command void enableEndOfLine();
async event void endOfLine();
command void enableRecvDataAvailable();
async event void recvDataAvailable(uint8_t channel);
command void enableFIFOOverrun();
async event void fifoOverrun(uint8_t channel);
}
--- NEW FILE: PXA27XQuickCaptIntC.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2005 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* Wiring for the PXA27X Quick Capture Interface.
*
* @author Konrad Lorincz
* @version 1.0 - September 10, 2005
*/
includes pxa27x_registers;
includes PXA27XQuickCaptInt;
configuration PXA27XQuickCaptIntC
{
provides interface StdControl;
provides interface PXA27XQuickCaptInt;
}
implementation
{
components PXA27XQuickCaptIntM;
components PXA27XInterruptM;
components PXA27XHPLDMAM;
StdControl = PXA27XQuickCaptIntM;
PXA27XQuickCaptInt = PXA27XQuickCaptIntM;
PXA27XQuickCaptIntM.PXA27XQuickCaptIntIrq -> PXA27XInterruptM.PXA27XIrq[PPID_CIF];
PXA27XQuickCaptIntM.PXA27XHPLDMA -> PXA27XHPLDMAM.PXA27XHPLDMA;
}
--- NEW FILE: PXA27XQuickCaptIntM.nc ---
/* tab:4
* IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING. By
* downloading, copying, installing or using the software you agree to
* this license. If you do not agree to this license, do not download,
* install, copy or use the software.
*
* Intel Open Source License
*
* Copyright (c) 2005 Intel Corporation
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met:
*
* Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* Neither the name of the Intel Corporation nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE INTEL OR ITS
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/**
* Description - PXA27X Quick Capture Interface module.
*
* @author Konrad Lorincz
* @version 1.0, August 10, 2005
*/
includes pxa27x_registers;
includes PXA27XQuickCaptInt;
module PXA27XQuickCaptIntM
{
provides interface StdControl;
provides interface PXA27XQuickCaptInt;
uses interface PXA27XInterrupt as PXA27XQuickCaptIntIrq;
uses interface PXA27XHPLDMA;
}
implementation
{
// ======================= Data ==================================
uint32_t nbrBytesToTransfer = Image_MAX_ROWS*Image_MAX_COLS*4; // depends on the image size
// ======================= Methods ===============================
// ----------------------- DMA Helper functions ------------------
void DMA_setSourceAddr(DMADescriptor_t* descPtr, uint32_t val)
{
atomic{ descPtr->DSADR = val; }
}
void DMA_setTargetAddr(DMADescriptor_t* descPtr, uint32_t val)
{
atomic{ descPtr->DTADR = val; }
}
void DMA_enableSourceAddrIncrement(DMADescriptor_t* descPtr, bool enable)
{
atomic{ descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_INCSRCADDR : descPtr->DCMD & ~DCMD_INCSRCADDR; }
}
void DMA_enableTargetAddrIncrement(DMADescriptor_t* descPtr, bool enable)
{
atomic{ descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_INCTRGADDR : descPtr->DCMD & ~DCMD_INCTRGADDR; }
}
void DMA_enableSourceFlowControl(DMADescriptor_t* descPtr, bool enable)
{
atomic{descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_FLOWSRC : descPtr->DCMD & ~DCMD_FLOWSRC;}
}
void DMA_enableTargetFlowControl(DMADescriptor_t* descPtr, bool enable)
{
descPtr->DCMD = (enable == TRUE) ? descPtr->DCMD | DCMD_FLOWTRG : descPtr->DCMD & ~DCMD_FLOWTRG;
}
void DMA_setMaxBurstSize(DMADescriptor_t* descPtr, DMAMaxBurstSize_t size)
{
if(size >= DMA_8ByteBurst && size <= DMA_32ByteBurst){
atomic{
//clear it out since otherwise |'ing doesn't work so well
descPtr->DCMD &= ~DCMD_MAXSIZE;
descPtr->DCMD |= DCMD_SIZE(size);
}
}
}
void DMA_setTransferLength(DMADescriptor_t* descPtr, uint16_t length)
{
uint16_t currentLength;
currentLength = (length<8192) ? length: 8190;
atomic{
descPtr->DCMD &= ~DCMD_MAXLEN;
descPtr->DCMD |= DCMD_LEN(currentLength);
}
}
void DMA_setTransferWidth(DMADescriptor_t* descPtr, DMATransferWidth_t width)
{
atomic{
//clear it out since otherwise |'ing doesn't work so well
descPtr->DCMD &= ~DCMD_MAXWIDTH;
descPtr->DCMD |= DCMD_WIDTH(width);
}
}
void DMA_run()
{
atomic{
uint32_t dcsr = call PXA27XHPLDMA.getDCSR(CIF_CHAN);
call PXA27XHPLDMA.mapChannel(CIF_CHAN, DMAREQ_CIF_RECV_0);
call PXA27XHPLDMA.setByteAlignment(CIF_CHAN, TRUE);
dcsr &= ~(DCSR_RUN);
dcsr &= ~(DCSR_NODESCFETCH);
call PXA27XHPLDMA.setDCSR(CIF_CHAN, dcsr);
call PXA27XHPLDMA.setDDADR(CIF_CHAN, DescArray_get(&descArray, 0) );
call PXA27XHPLDMA.setDCSR(CIF_CHAN, (call PXA27XHPLDMA.getDCSR(CIF_CHAN)) | DCSR_RUN );
}
}
// ----------------------- Internal private helper functions -----
void CIF_configurePins()
{
// (1) - Configure the GPIO Alt functions and direction
// --- Template ----
//_GPIO_setaltfn(PIN, PIN_ALTFN);
//_GPDR(PIN) &= ~_GPIO_bit(PIN); // input
//_GPDR(PIN) |= _GPIO_bit(PIN); // output
// -----------------
// CIF_MCLK
_GPIO_setaltfn(PIN_CIF_MCLK, PIN_CIF_MCLK_ALTFN);
//_GPDR(PIN_CIF_MCLK) &= ~_GPIO_bit(PIN_CIF_MCLK); // input
_GPDR(PIN_CIF_MCLK) |= _GPIO_bit(PIN_CIF_MCLK); // output (if sensor is master)
// CIF_PCLK
_GPIO_setaltfn(PIN_CIF_PCLK, PIN_CIF_PCLK_ALTFN);
_GPDR(PIN_CIF_PCLK) &= ~_GPIO_bit(PIN_CIF_PCLK); // input (if sensor is master)
// CIF_FV
_GPIO_setaltfn(PIN_CIF_FV, PIN_CIF_FV_ALTFN);
_GPDR(PIN_CIF_FV) &= ~_GPIO_bit(PIN_CIF_FV); // input (if sensor is master)
//_GPDR(PIN_CIF_FV) |= _GPIO_bit(PIN_CIF_FV); // output (if sensor is slave)
// CIF_LV
_GPIO_setaltfn(PIN_CIF_LV, PIN_CIF_LV_ALTFN);
_GPDR(PIN_CIF_LV) &= ~_GPIO_bit(PIN_CIF_LV); // input (if sensor is master)
//_GPDR(PIN_CIF_LV) |= _GPIO_bit(PIN_CIF_LV); // output (if sensor is slave)
// CIF_DD0 ... CIF_DD9
_GPIO_setaltfn(PIN_CIF_DD0, PIN_CIF_DD0_ALTFN);
_GPDR(PIN_CIF_DD0) &= ~_GPIO_bit(PIN_CIF_DD0); // input
_GPIO_setaltfn(PIN_CIF_DD1, PIN_CIF_DD1_ALTFN);
_GPDR(PIN_CIF_DD1) &= ~_GPIO_bit(PIN_CIF_DD1); // input
_GPIO_setaltfn(PIN_CIF_DD2, PIN_CIF_DD2_ALTFN);
_GPDR(PIN_CIF_DD2) &= ~_GPIO_bit(PIN_CIF_DD2); // input
_GPIO_setaltfn(PIN_CIF_DD3, PIN_CIF_DD3_ALTFN);
_GPDR(PIN_CIF_DD3) &= ~_GPIO_bit(PIN_CIF_DD3); // input
_GPIO_setaltfn(PIN_CIF_DD4, PIN_CIF_DD4_ALTFN);
_GPDR(PIN_CIF_DD4) &= ~_GPIO_bit(PIN_CIF_DD4); // input
_GPIO_setaltfn(PIN_CIF_DD5, PIN_CIF_DD5_ALTFN);
_GPDR(PIN_CIF_DD5) &= ~_GPIO_bit(PIN_CIF_DD5); // input
_GPIO_setaltfn(PIN_CIF_DD6, PIN_CIF_DD6_ALTFN);
_GPDR(PIN_CIF_DD6) &= ~_GPIO_bit(PIN_CIF_DD6); // input
_GPIO_setaltfn(PIN_CIF_DD7, PIN_CIF_DD7_ALTFN);
_GPDR(PIN_CIF_DD7) &= ~_GPIO_bit(PIN_CIF_DD7); // input
_GPIO_setaltfn(PIN_CIF_DD8, PIN_CIF_DD8_ALTFN);
_GPDR(PIN_CIF_DD8) &= ~_GPIO_bit(PIN_CIF_DD8); // input
_GPIO_setaltfn(PIN_CIF_DD9, PIN_CIF_DD9_ALTFN);
_GPDR(PIN_CIF_DD9) &= ~_GPIO_bit(PIN_CIF_DD9); // input
}
void CIF_setAndEnableCICR0(uint32_t data)
{
call PXA27XQuickCaptInt.disableQuick();
CICR0 = (data | CICR0_EN);
}
void CIF_InitDMA()
{
uint8_t i = 0;
DMADescriptor_t* descPtr = NULL;
uint32_t bytesLeftToSchedule = nbrBytesToTransfer;
for (i = 0; bytesLeftToSchedule > 0; ++i) {
descPtr = DescArray_get(&descArray, i);
DMA_setSourceAddr(descPtr, CIBR0_ADDR);
DMA_setTargetAddr(descPtr, &image.data[ i*(MAX_DESC_TRANSFER/4) ]);
DMA_enableSourceAddrIncrement(descPtr, FALSE);
DMA_enableTargetAddrIncrement(descPtr, TRUE);
DMA_enableSourceFlowControl(descPtr, TRUE);
DMA_enableTargetFlowControl(descPtr, FALSE);
DMA_setMaxBurstSize(descPtr, 3); // burst size: can be 8, 16, or 32 bytes
DMA_setTransferWidth(descPtr, 3); // peripheral width for DMA transactions from CIF is always 8-bytes, regardless of DCMD[WIDTH]
if (bytesLeftToSchedule >= MAX_DESC_TRANSFER) {
DMA_setTransferLength(descPtr, MAX_DESC_TRANSFER); // 16*8 *2 =256 bytes // must be an integer multiple of 8-bytes
bytesLeftToSchedule -= MAX_DESC_TRANSFER;
}
else {
DMA_setTransferLength(descPtr, bytesLeftToSchedule);
bytesLeftToSchedule = 0;
}
// continue running the next descriptor
descPtr->DDADR = DescArray_get(&descArray, i+1);
}
// Set the stop bit for the last descriptor
descPtr->DDADR |= DDADR_STOP;
}
void CIF_init()
{
//atomic enabledInterrupts = 0;
CKEN |= CKEN24_CIF; // enable the CIF clock
call PXA27XQuickCaptIntIrq.allocate(); // generate an CIF interrupt
call PXA27XQuickCaptIntIrq.enable(); // enable the CIF interrupt mask
// ------------------------------------------------------
// (1) - Disable the CIF interface
call PXA27XQuickCaptInt.disableQuick();
// (2) - Set the timing/clocks
// a. Have the mote supply the MCLK to the camera sensor
CICR4 = CICR4_DIV(CICR4, 2); // Set the MCLK clock rate to 15 MHz
CICR4 |= CICR4_MCLK_EN;
// b. Have the camera suply the PCLK to the mote
CICR4 |= CICR4_PCLK_EN;
// c. Set the synchronization signals to be active low
CICR4 |= CICR4_HSP;
CICR4 |= CICR4_VSP;
// (3) - Set the data format (nbr pixels, color space, encoding, etc.)
CICR1 = CICR1_DW(CICR1, 4); // Data Width: 10 bits wide data from the sensor
CICR1 = CICR1_COLOR_SP(CICR1, 0); // Color Space: Raw
CICR1 = CICR1_RAW_BPP(CICR1, 2); // Raw bits per pixel: 10
CICR3 = CICR3_LPF(CICR3, (1024-1)); // lines per frame (rows): 1024
CICR1 = CICR1_PPL(CICR1, (1280-1)); // pixels per line (cols): 1280
// (4) - FIFO DMA threshold level
CIFR = CIFR_THL_0(CIFR, 0); // 96 bytes of more in FIFO 0 causea a DMA request
// (5) - Initialize the DMA
CIF_InitDMA();
// (6) - Enable the CIF with DMA
CIF_setAndEnableCICR0(CICR0 | CICR0_DMA_EN);
}
// ----------------------- StdControl interface ------------------
command result_t StdControl.init()
{
CIF_configurePins();
CIF_init();
return SUCCESS;
}
command result_t StdControl.start()
{
return SUCCESS;
}
command result_t StdControl.stop()
{
call PXA27XQuickCaptIntIrq.disable(); // disable the CIF interrupt mask
return SUCCESS;
}
// ----------------------- PXA27XQuickCaptInt ------------------
command void PXA27XQuickCaptInt.enable()
{
uint32_t tempCICR0 = CICR0;
tempCICR0 |= CICR0_EN;
CICR0 = tempCICR0;
}
command void PXA27XQuickCaptInt.disableQuick()
{
CICR0 &= ~(CICR0_EN);
CISR |= CISR_CQD;
}
command void PXA27XQuickCaptInt.startDMA()
{
DMA_run();
}
command result_t PXA27XQuickCaptInt.setImageSize(uint16_t sizeX, uint16_t sizeY)
{
if (sizeX > 2048 || sizeY > 2048)
return FAIL;
else {
// (1) - Set the Quick Capture Interface Size
call PXA27XQuickCaptInt.disableQuick();
CICR1 = CICR1_PPL(CICR1, (sizeX-1));
CICR3 = CICR3_LPF(CICR3, (sizeY-1));
call PXA27XQuickCaptInt.enable();
// (2) - Set the DMA transfer size
nbrBytesToTransfer = sizeX*sizeY*2; // each pixel is 2 bytes
return SUCCESS;
}
}
command void PXA27XQuickCaptInt.enableStartOfFrame() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_SOFM));}
command void PXA27XQuickCaptInt.enableEndOfFrame() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_EOFM));}
command void PXA27XQuickCaptInt.enableEndOfLine() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_EOLM));}
command void PXA27XQuickCaptInt.enableRecvDataAvailable() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_RDAVM));}
command void PXA27XQuickCaptInt.enableFIFOOverrun() {CIF_setAndEnableCICR0(CICR0 & ~(CICR0_FOM));}
uint32_t fifoBuffer[32];
// ---------------------- PXA27XInterrupt interface -------------------------
async event void PXA27XQuickCaptIntIrq.fired()
{
//atomic{printfUART(">>>>>>>>>>>>>>> PXA27XQuickCaptIntIrq.fired() >>>>>>>>>>>\n", "");}
volatile uint32_t tempCISR;
atomic { tempCISR = CISR; }
// Start-Of-Frame
if ((tempCISR & CISR_SOF) && (~(CICR0) & CICR0_SOFM)) {
atomic CISR |= CISR_SOF;
signal PXA27XQuickCaptInt.startOfFrame();
}
// End-Of-Frame
if ((tempCISR & CISR_EOF) && (~(CICR0) & CICR0_EOFM)) {
atomic CISR |= CISR_EOF;
signal PXA27XQuickCaptInt.endOfFrame();
}
// End-Of-Line
if ((tempCISR & CISR_EOL) && (~(CICR0) & CICR0_EOLM)) {
atomic CISR |= CISR_EOL;
signal PXA27XQuickCaptInt.endOfLine();
}
// Receive-Data-Available
if (~(CICR0) & CICR0_RDAVM) {
if (tempCISR & CISR_RDAV_2) { // channel 2
atomic CISR |= CISR_RDAV_2;
signal PXA27XQuickCaptInt.recvDataAvailable(2);
}
if (tempCISR & CISR_RDAV_1) { // channel 1
atomic CISR |= CISR_RDAV_1;
signal PXA27XQuickCaptInt.recvDataAvailable(1);
}
if (tempCISR & CISR_RDAV_0) { // channel 0
atomic CISR |= CISR_RDAV_0;
signal PXA27XQuickCaptInt.recvDataAvailable(0);
}
}
// FIFO Overrun
if (~(CICR0) & CICR0_FOM) {
if (tempCISR & CISR_IFO_2) { // channel 2
atomic CISR |= CISR_IFO_2;
signal PXA27XQuickCaptInt.fifoOverrun(2);
}
if (tempCISR & CISR_IFO_1) { // channel 1
atomic CISR |= CISR_IFO_1;
signal PXA27XQuickCaptInt.fifoOverrun(1);
}
if (tempCISR & CISR_IFO_0) { // channel 0
atomic CISR |= CISR_IFO_0;
signal PXA27XQuickCaptInt.fifoOverrun(0);
}
}
}
}
Index: PXA27XI2CM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/PXA27XI2CM.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** PXA27XI2CM.nc 25 Aug 2005 23:06:55 -0000 1.1
--- PXA27XI2CM.nc 20 Sep 2005 02:28:58 -0000 1.2
***************
*** 54,58 ****
*/
includes pxa27x_registers;
- includes pxa27x_registersI2C;
module PXA27XI2CM
--- 54,57 ----
Index: pxa27x_registers.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/pxa27x/pxa27x_registers.h,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** pxa27x_registers.h 19 Sep 2005 20:45:30 -0000 1.11
--- pxa27x_registers.h 20 Sep 2005 02:28:58 -0000 1.12
***************
*** 42,47 ****
* Authors: Phil Buonadonna
*
! * Edits: Josh Herbach
! * Revised: 09/02/2005
*/
--- 42,47 ----
* Authors: Phil Buonadonna
*
! * Edits: Josh Herbach, Konrad Lorincz
! * Revised: 09/19/2005
*/
***************
*** 199,202 ****
--- 199,264 ----
+ /* Quick Capture Interface - Control Register 0 */
+ #define CICR0_DMA_EN (1 << 31) /* DMA Request Enable */
+ #define CICR0_EN (1 << 28) /* Quick Capture Interface Enable (and Quick Disable) */
+ #define CICR0_TOM (1 << 9) /* Time-Out Interrupt Mask */
+ #define CICR0_RDAVM (1 << 8) /* Receive-Data-Available Interrupt Mask */
+ #define CICR0_FEM (1 << 7) /* FIFO-Empty Interrupt Mask */
+ #define CICR0_EOLM (1 << 6) /* End-of-Line Interrupt Mask */
+ #define CICR0_SOFM (1 << 2) /* Start-of-Frame Interrupt Mask */
+ #define CICR0_EOFM (1 << 1) /* End-of-Frame Interrupt Mask */
+ #define CICR0_FOM (1 << 0) /* FIFO Overrun Interrupt Mask */
+
+
+ /* Quick Capture Interface - Control Register 1 */
+ #define CICR1_TBIT (1 << 31) /* Transparency Bit */
+ #define CICR1_RGBT_CONV(_data,_x) ((_data & ~(0x7 << 29)) | (_x << 29)) /* RGBT Conversion */
+ #define CICR1_PPL(_data,_x) ((_data & ~(0x7ff << 15)) | (_x << 15)) /* Pixels per Line */
+ #define CICR1_RGB_CONV(_data,_x) ((_data & ~(0x7 << 12)) | (_x << 12)) /* RGB Bits per Pixel Conversion */
+ #define CICR1_RGB_F (1 << 11) /* RGB Format */
+ #define CICR1_YCBCR_F (1 << 10) /* YCbCr Format */
+ #define CICR1_RGB_BPP(_data,_x) ((_data & ~(0x7 << 7)) | (_x << 7)) /* RGB Bits per Pixel */
+ #define CICR1_RAW_BPP(_data,_x) ((_data & ~(0x3 << 5)) | (_x << 5)) /* Raw Bits per Pixel */
+ #define CICR1_COLOR_SP(_data,_x) ((_data & ~(0x3 << 3)) | (_x << 3)) /* Color Space */
+ #define CICR1_DW(_data,_x) ((_data & ~(0x7 << 0)) | (_x << 0)) /* Data Width */
+
+
+ /* Quick Capture Interface - Control Register 3 */
+ #define CICR3_LPF(_data,_x) ((_data & ~(0x7ff << 0)) | (_x << 0)) /* Lines per Frame */
+
+ /* Quick Capture Interface - Control Register 4 */
+ #define CICR4_PCLK_EN (1 << 23) /* Pixel Clock Enable */
+ #define CICR4_HSP (1 << 21) /* Horizontal Sync Polarity */
+ #define CICR4_VSP (1 << 20) /* Vertical Sync Polarity */
+ #define CICR4_MCLK_EN (1 << 19) /* MCLK Enable */
+ #define CICR4_DIV(_data,_x) ((_data & ~(0xff << 0)) | (_x << 0)) /* Clock Divisor */
+
+ /* Quick Capture Interface - Status Register */
+ #define CISR_FTO (1 << 15) /* FIFO Time-Out */
+ #define CISR_RDAV_2 (1 << 14) /* Channel 2 Receive Data Available */
+ #define CISR_RDAV_1 (1 << 13) /* Channel 1 Receive Data Available */
+ #define CISR_RDAV_0 (1 << 12) /* Channel 0 Receive Data Available */
+ #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO Empty */
+ #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO Empty */
+ #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO Empty */
+ #define CISR_EOL (1 << 8) /* End-of-Line */
+ #define CISR_PAR_ERR (1 << 7) /* Parity Error */
+ #define CISR_CQD (1 << 6) /* Quick Campture Interface Quick Dissable */
+ #define CISR_CDD (1 << 5) /* Quick Campture Interface Quick Dissable Done */
+ #define CISR_SOF (1 << 4) /* Start-of-Frame */
+ #define CISR_EOF (1 << 3) /* End-of-Frame */
+ #define CISR_IFO_2 (1 << 2) /* FIFO Overrun for Channel 2 */
+ #define CISR_IFO_1 (1 << 1) /* FIFO Overrun for Channel 1 */
+ #define CISR_IFO_0 (1 << 0) /* FIFO Overrun for Channel 0 */
+
+
+ /* Quick Capture Interface - FIFO Control Register */
+ #define CIFR_FLVL0(_data,_x) ((_data & ~(0xff << 8)) | (_x << 8)) /* FIFO 0 Level: value from 0-128 indicates the number of bytes */
+ #define CIFR_THL_0(_data,_x) ((_data & ~(0x3 << 4)) | (_x << 4)) /* Threshold Level for Channel 0 FIFO */
+ #define CIFR_RESETF (1 << 3) /* Reset input FIFOs */
+
+
+
+
/******************************************************************************/
/* DMA Controller */
***************
*** 716,720 ****
#define ICR_GCD (1 << 7) /* General Call Disable */
#define ICR_IUE (1 << 6) /* I2C Unit Enable */
! #define ICR_SCLEA (1 << 5) /* SCL Enable */
#define ICR_MA (1 << 4) /* Master Abort */
#define ICR_TB (1 << 3) /* Transfer Byte */
--- 778,782 ----
#define ICR_GCD (1 << 7) /* General Call Disable */
#define ICR_IUE (1 << 6) /* I2C Unit Enable */
! #define ICR_SCLE (1 << 5) /* SCL Enable */
#define ICR_MA (1 << 4) /* Master Abort */
#define ICR_TB (1 << 3) /* Transfer Byte */
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