[Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2
BluSHC.nc, 1.4, 1.5 BluSHM.nc, 1.8, 1.9 BulkTxRx.nc, 1.2,
1.3 FlashM.nc, 1.12, 1.13 HPLCC2420M.nc, 1.8,
1.9 HPLFFUARTC.nc, 1.1, 1.2 HPLFFUARTM.nc, 1.3,
1.4 HPLSTUARTC.nc, 1.1, 1.2 HPLSTUARTM.nc, 1.3,
1.4 HPLUSBClientGPIOM.nc, 1.4, 1.5 PMIC.nc, 1.2, 1.3 PMICC.nc,
1.1, 1.2 PMICM.nc, 1.3, 1.4 SSP.nc, 1.1, 1.2 SSP1C.nc, 1.2,
1.3 SSP1M.nc, 1.4, 1.5 SettingsC.nc, 1.2, 1.3 SettingsM.nc,
1.2, 1.3 TimerJiffyAsyncC.nc, 1.1, 1.2 hardware.h, 1.8,
1.9 pmic.h, 1.4, 1.5
Lama Nachman
lnachman at users.sourceforge.net
Mon Oct 9 18:57:47 PDT 2006
- Previous message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2
BTUARTC.nc, NONE, 1.1 BTUARTM.nc, NONE, 1.1 BufferedBTUARTC.nc,
NONE, 1.1 BufferedBTUARTM.nc, NONE, 1.1 BufferedFFUARTC.nc,
NONE, 1.1 BufferedFFUARTM.nc, NONE, 1.1 BufferedSTUARTC.nc,
NONE, 1.1 BufferedSTUARTM.nc, NONE, 1.1 BufferedUART.c, NONE,
1.1 BulkTxRx.h, NONE, 1.1 FFUARTC.nc, NONE, 1.1 FFUARTM.nc,
NONE, 1.1 Reset.h, NONE, 1.1 SSP.c, NONE, 1.1 SSP2C.nc, NONE,
1.1 SSP2M.nc, NONE, 1.1 STUARTC.nc, NONE, 1.1 STUARTM.nc, NONE,
1.1 SendData.nc, NONE, 1.1 SendDataAlloc.nc, NONE, 1.1 UART.c,
NONE, 1.1 sched.c, NONE, 1.1
- Next message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
FileList.h, NONE, 1.1 FileStorageUtil.nc, NONE,
1.1 FormatStorageC.nc, NONE, 1.1 FormatStorageM.nc, NONE,
1.1 HALPXA27X.nc, NONE, 1.1 HALPXA27XC.nc, NONE,
1.1 HALPXA27XM.nc, NONE, 1.1 I2CTempC.nc, NONE,
1.1 I2CTempM.nc, NONE, 1.1 PXA27XOneHzClock.nc, NONE,
1.1 PXA27XPowerManagement.nc, NONE,
1.1 PXA27XPowerManagementM.nc, NONE, 1.1 PXA27XRTCC.nc, NONE,
1.1 PXA27XRTCM.nc, NONE, 1.1 PXA27XSysTimeM.nc, NONE,
1.1 PXA27XWallClockM.nc, NONE, 1.1 PXA27xPowerManagement.h,
NONE, 1.1 PXAFlash.h, NONE, 1.1 SectorStorage.nc, NONE,
1.1 StorageManager.nc, NONE, 1.1 StorageManagerC.nc, NONE,
1.1 StorageManagerM.nc, NONE, 1.1 Storage_chip.h, NONE,
1.1 SysTime64.nc, NONE, 1.1 SysTimeC.nc, NONE, 1.1 TimerM.nc,
NONE, 1.1 WallClock.nc, NONE, 1.1 pxa27x_registers_def.h, NONE, 1.1
- Messages sorted by:
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Update of /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv3395
Modified Files:
BluSHC.nc BluSHM.nc BulkTxRx.nc FlashM.nc HPLCC2420M.nc
HPLFFUARTC.nc HPLFFUARTM.nc HPLSTUARTC.nc HPLSTUARTM.nc
HPLUSBClientGPIOM.nc PMIC.nc PMICC.nc PMICM.nc SSP.nc SSP1C.nc
SSP1M.nc SettingsC.nc SettingsM.nc TimerJiffyAsyncC.nc
hardware.h pmic.h
Log Message:
Pushed out a new release OCT/2006
Index: BluSHC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/BluSHC.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** BluSHC.nc 8 Dec 2005 23:13:04 -0000 1.4
--- BluSHC.nc 10 Oct 2006 01:57:44 -0000 1.5
***************
*** 12,16 ****
implementation {
components
! DebugUARTBufferC as UARTBuffer,
//DebugUARTBufferC as UARTBuffer,
#if USE_USB
--- 12,16 ----
implementation {
components
! BufferedSTUARTC as UARTBuffer,
//DebugUARTBufferC as UARTBuffer,
#if USE_USB
***************
*** 22,25 ****
--- 22,26 ----
#if USE_USB
+ //BluSHM.USBSend -> USBClient.SendJTPacket[unique("JTPACKET")];
BluSHM.USBSend -> USBClient.SendJTPacket;
BluSHM.USBReceive -> USBClient.ReceiveData;
***************
*** 27,31 ****
BluSHM.UartControl -> UARTBuffer.Control;
! BluSHM.UartSend -> UARTBuffer.SendVarLenPacket;
BluSHM.UartReceive -> UARTBuffer.ReceiveData;
--- 28,32 ----
BluSHM.UartControl -> UARTBuffer.Control;
! BluSHM.UartSend -> UARTBuffer.SendData;
BluSHM.UartReceive -> UARTBuffer.ReceiveData;
Index: BluSHM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/BluSHM.nc,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** BluSHM.nc 18 Oct 2005 21:11:20 -0000 1.8
--- BluSHM.nc 10 Oct 2006 01:57:44 -0000 1.9
***************
*** 16,20 ****
{
interface StdControl as UartControl;
! interface SendVarLenPacket as UartSend;
interface ReceiveData as UartReceive;
--- 16,20 ----
{
interface StdControl as UartControl;
! interface SendData as UartSend;
interface ReceiveData as UartReceive;
***************
*** 65,70 ****
void trace(TOS_dbg_mode mode, const char *format, ...) __attribute ((C, spontaneous)){
! if (trace_active(mode))
! {
char buf[MAX_PRINTF_LEN+1];
uint16_t buflen;
--- 65,69 ----
void trace(TOS_dbg_mode mode, const char *format, ...) __attribute ((C, spontaneous)){
! if (trace_active(mode)) {
char buf[MAX_PRINTF_LEN+1];
uint16_t buflen;
***************
*** 72,77 ****
va_start(args, format);
! if (!(mode & DBG_SIM))
! {
buflen=vsnprintf(buf,MAX_PRINTF_LEN,format,args);
//make sure that we're properly terminating our string...
--- 71,75 ----
va_start(args, format);
! if (!(mode & DBG_SIM)) {
buflen=vsnprintf(buf,MAX_PRINTF_LEN,format,args);
//make sure that we're properly terminating our string...
***************
*** 82,96 ****
}
}
!
unsigned char trace_active(TOS_dbg_mode mode) __attribute__((C, spontaneous)){
! return (trace_modes & mode) != 0;
}
void trace_unset() __attribute__ ((C,spontaneous)){
! trace_modes = 0;
}
void trace_set(TOS_dbg_mode mode) __attribute__ ((C, spontaneous)){
! trace_modes = mode;
}
--- 80,96 ----
}
}
!
unsigned char trace_active(TOS_dbg_mode mode) __attribute__((C, spontaneous)){
! unsigned char result;
! atomic result = (trace_modes & mode) != 0;
! return result;
}
void trace_unset() __attribute__ ((C,spontaneous)){
! atomic trace_modes = 0;
}
void trace_set(TOS_dbg_mode mode) __attribute__ ((C, spontaneous)){
! atomic trace_modes = mode;
}
***************
*** 206,214 ****
strcpy(blush_history[hist_idx], blush_history[hist_idx - 1]);
blush_history[0][0] = '\0';
!
if(InTaskCount <= 5 && DynQueue_getLength(InQueue) > 0)
post processIn();
else
atomic InTaskCount--;
}
--- 206,218 ----
strcpy(blush_history[hist_idx], blush_history[hist_idx - 1]);
blush_history[0][0] = '\0';
!
if(InTaskCount <= 5 && DynQueue_getLength(InQueue) > 0)
post processIn();
else
atomic InTaskCount--;
+
+ free(data->src);
+ free(data);
+
}
***************
*** 223,229 ****
call UartControl.init();
strncpy( blush_prompt, "BluSH>", BLUSH_PROMPT_LENGTH );
!
! InQueue = DynQueue_new();
! OutQueue = DynQueue_new();
return SUCCESS;
}
--- 227,235 ----
call UartControl.init();
strncpy( blush_prompt, "BluSH>", BLUSH_PROMPT_LENGTH );
!
! atomic{
! InQueue = DynQueue_new();
! OutQueue = DynQueue_new();
! }
return SUCCESS;
}
***************
*** 239,244 ****
command result_t StdControl.stop()
{
! DynQueue_free(InQueue);
! DynQueue_free(OutQueue);
call UartControl.stop();
return SUCCESS;
--- 245,252 ----
command result_t StdControl.stop()
{
! atomic{
! DynQueue_free(InQueue);
! DynQueue_free(OutQueue);
! }
call UartControl.stop();
return SUCCESS;
***************
*** 432,436 ****
#endif
! event result_t UartSend.sendDone(uint8_t* packet, result_t success)
{
// This function does nothing.
--- 440,444 ----
#endif
! event result_t UartSend.sendDone(uint8_t* packet, uint32_t numBytes, result_t success)
{
// This function does nothing.
***************
*** 443,452 ****
DynQueue QueueTemp;
BluSHdata temp;
! atomic QueueTemp = OutQueue;
! temp = (BluSHdata)DynQueue_peek(QueueTemp);
if(temp->src == packet){
free(packet);
free(temp);
! DynQueue_dequeue(QueueTemp);
}
return SUCCESS;
--- 451,463 ----
DynQueue QueueTemp;
BluSHdata temp;
! atomic {
! temp = (BluSHdata)DynQueue_peek(OutQueue);
! }
if(temp->src == packet){
free(packet);
free(temp);
! atomic{
! DynQueue_dequeue(QueueTemp);
! }
}
return SUCCESS;
Index: BulkTxRx.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/BulkTxRx.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** BulkTxRx.nc 18 Oct 2005 21:11:20 -0000 1.2
--- BulkTxRx.nc 10 Oct 2006 01:57:44 -0000 1.3
***************
*** 1,31 ****
/**
! * The BulkTxRx interface is intended to provide the functionality of a DMA
! * controller on both the send and receive sides of a transaction. In order
! * to provide this functionality, the interface provide 2 commands and 2
! * events. Because the DMA interface is intended to supplement a standard
! * byte based interface, there is no init, start, or stop. Instead
! * either of the 2 commands may return fail if for some reason there is
! * something wrong with port when the command is issued
*
* @author Robbie Adler
**/
interface BulkTxRx {
/**
* Begin a BulkReceive. The parameters should be the initial buffer
! * to place data into and the inital number of bytes. DMA receive chaining
! * may be accomplished by returning a new buffer in the associated DMAGetDone
! * event. Return NULL to complete the DMA transaction.
**/
! command result_t BulkReceive(uint8_t *RxBuffer, uint16_t NumBytes) ;
/**
* This command informs the component to send NumBytes
! * using the TxBuffer parameter as the source.
**/
! command result_t BulkTransmit(uint8_t *TxBuffer, uint16_t NumBytes) ;
/**
* This event is signaled to inform the application that NumBytes
* have been received. No assumptions can be made about the
--- 1,50 ----
/**
! * The BulkTxRx interface is intended to provide the functionality required for
! * both the send and the receive sides of a half-duplex or full-duplex
! * communication transaction. In order to provide this functionality,
! * the interface provide 2 commands and 2 events. Because this interface is
! * intended to be generic, there are no explicit configuration or
! * initialization * commands. Instead, it is expected that the port that
! * exposes this interface expose a port-specific set of configuration commands.
! * Additionally, there are no explicit start or stop commands. Instead,
! * "starting" is done implicitly by calling one of the commands. If the
! * command returns SUCCESS, the transaction has been started. Once a
! * transaction has been started, it may be stopped by returning NULL in the
! * corresponding *Done events or by calling the Abort command.
*
* @author Robbie Adler
**/
+ includes BulkTxRx;
interface BulkTxRx {
/**
* Begin a BulkReceive. The parameters should be the initial buffer
! * to place data into and the inital number of bytes. Receive chaining
! * may be accomplished by returning a new buffer in the associated BulkReceiveDone
! * event. Return NULL to complete the transaction.
**/
! command result_t BulkReceive(uint8_t *RxBuffer, uint16_t NumBytes);
/**
* This command informs the component to send NumBytes
! * using the TxBuffer parameter as the source. Transmit chaining
! * may be accomplished by returned a new buffer in the associated BulkTransmitDone
! * event. Return NULL to complete the transaction
**/
! command result_t BulkTransmit(uint8_t *TxBuffer, uint16_t NumBytes);
/**
+ * This command informs the component to send NumBytes
+ * using the TxBuffer parameter as the source while receiving NumBytes
+ * simultaneously into the RxBuffer. The intention of this command is
+ * to allow the interface to be exposed by FULL-DUPLEX protocals such as
+ * SSP and SPI. TxRx chaining may be accomplished by returning 2 NON-NULL
+ * buffers in the associated BulkTxRxDone event
+ **/
+ command result_t BulkTxRx(BulkTxRxBuffer_t *TxRxBuffer, uint16_t NumBytes);
+
+
+ /**
* This event is signaled to inform the application that NumBytes
* have been received. No assumptions can be made about the
***************
*** 42,51 ****
*
**/
! event uint8_t *BulkReceiveDone(uint8_t *data, uint16_t NumBytes);
!
/**
* This event is signaled by the component to indicate
! * that the bytes have been sent out.
**/
! event result_t BulkTransmitDone(uint8_t *data);
}
--- 61,84 ----
*
**/
! async event uint8_t *BulkReceiveDone(uint8_t *RxBuffer, uint16_t NumBytes);
!
/**
* This event is signaled by the component to indicate
! * that the bytes have been sent out. Return NULL to stop the
! * transaction and return to the IDLE state. Return a valid buffer
! * to continue the transaction.
**/
! async event uint8_t *BulkTransmitDone(uint8_t *TxBuffer, uint16_t NumBytes);
!
! /**
! * This event is signaled by the component to indicate
! * that the FULL-DUPLEX operation has been completed. Return NULL
! * to stop the transaction and return to the IDLE state. Return
! * a valid BulkTxRx_t stucture with both fields pointing to valid
! * buffer to continue the transaction. It is a checked run-time
! * error to return a structure with one of it's fields set to NULL.
! **/
!
! async event BulkTxRxBuffer_t *BulkTxRxDone(BulkTxRxBuffer_t *TxRxBuffer, uint16_t NumBytes);
!
}
Index: FlashM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/FlashM.nc,v
retrieving revision 1.12
retrieving revision 1.13
diff -C2 -d -r1.12 -r1.13
*** FlashM.nc 6 Sep 2005 18:36:08 -0000 1.12
--- FlashM.nc 10 Oct 2006 01:57:44 -0000 1.13
***************
*** 142,147 ****
if(addr < FLASH_PROTECTED_REGION)
return FAIL;
!
!
for(i = 0; i < FLASH_PARTITION_COUNT; i++)
if(i != addr / FLASH_PARTITION_SIZE &&
--- 142,147 ----
if(addr < FLASH_PROTECTED_REGION)
return FAIL;
!
!
for(i = 0; i < FLASH_PARTITION_COUNT; i++)
if(i != addr / FLASH_PARTITION_SIZE &&
***************
*** 261,265 ****
return SUCCESS;
}
!
uint16_t unlock(uint32_t addr) __attribute__((noinline)){
//addr <<= 1;
--- 261,305 ----
return SUCCESS;
}
!
! /**
! * read
! *
! * Reads data from the flash and copies to the buffer pointer passed as
! * parameter. The starting address and the size of data required must
! * be specified by the user.
! *
! * @param addr Flash address where the read starts.
! * @param data Pointer to the buffer to which the data will be copied to.
! * @param numBytes Number of bytes to read.
! *
! * @return SUCCESS or FAIL
! */
! command result_t Flash.read (uint32_t addr, uint8_t* data, uint32_t numBytes)
! {
! uint32_t curPtr = 0;
! uint32_t address = addr;
! uint32_t tmpdata = 0;
! while (curPtr < numBytes)
! {
! if (address % 2)
! {
! address = address - 1;
! tmpdata = (*((uint32_t *)address));
! tmpdata = (tmpdata >> 8) & 0xFFFF;
! memcpy ((data + curPtr), &tmpdata, 1);
! curPtr = curPtr + 1;
! }
! else
! {
! tmpdata = (*((uint32_t *)address));
! memcpy ((data + curPtr), &tmpdata, ((numBytes - curPtr) >= 2)? 2 : 1);
! curPtr = curPtr + 2;
! }
! address += 2;
! }
!
! return SUCCESS;
! }
!
uint16_t unlock(uint32_t addr) __attribute__((noinline)){
//addr <<= 1;
Index: HPLCC2420M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLCC2420M.nc,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** HPLCC2420M.nc 8 Dec 2005 23:13:05 -0000 1.8
--- HPLCC2420M.nc 10 Oct 2006 01:57:44 -0000 1.9
***************
*** 42,45 ****
--- 42,46 ----
includes MMU;
+ includes profile;
module HPLCC2420M {
provides {
***************
*** 55,59 ****
uses {
interface StdControl as GPIOControl;
- interface StdControl as DMAControl;
interface PXA27XGPIOInt as FIFOP_GPIOInt;
interface PXA27XGPIOInt as FIFO_GPIOInt;
--- 56,59 ----
***************
*** 69,72 ****
--- 69,74 ----
#define USE_DMA 0
#define DEBUG 0
+ #define TXDEBUG 0
+ #define RXDEBUG 0
uint8_t gbDMAChannelInitDone;
***************
*** 94,110 ****
command result_t StdControl.init() {
! _PXA_setaltfn(SSP3_SCLK,SSP3_SCLK_ALTFN,GPIO_OUT);
! _PXA_setaltfn(SSP3_TXD,SSP3_TXD_ALTFN,GPIO_OUT);
! _PXA_setaltfn(SSP3_RXD,SSP3_RXD_ALTFN,GPIO_IN);
// _PXA_setaltfn(SSP3_SFRM,SSP3_SFRM_ALTFN,GPIOIN);
atomic{
gbDMAChannelInitDone = 2;
gRadioOpInProgress = FALSE;
}
call RxDMAChannel.requestChannel(DMAID_SSP3_RX,DMA_Priority1, TRUE);
call TxDMAChannel.requestChannel(DMAID_SSP3_TX,DMA_Priority1, TRUE);
! call DMAControl.init();
!
call TxDMAChannel.setTargetAddr(0x41900010);
call TxDMAChannel.enableSourceAddrIncrement(TRUE);
--- 96,116 ----
command result_t StdControl.init() {
! GPIO_SET_ALT_FUNC(SSP3_SCLK,SSP3_SCLK_ALTFN,GPIO_OUT);
! GPIO_SET_ALT_FUNC(SSP3_TXD,SSP3_TXD_ALTFN,GPIO_OUT);
! GPIO_SET_ALT_FUNC(SSP3_RXD,SSP3_RXD_ALTFN,GPIO_IN);
// _PXA_setaltfn(SSP3_SFRM,SSP3_SFRM_ALTFN,GPIOIN);
atomic{
+ #if USE_DMA
gbDMAChannelInitDone = 2;
+ #else
+ gbDMAChannelInitDone = 0;
+ #endif
gRadioOpInProgress = FALSE;
}
+ #if USE_DMA
call RxDMAChannel.requestChannel(DMAID_SSP3_RX,DMA_Priority1, TRUE);
call TxDMAChannel.requestChannel(DMAID_SSP3_TX,DMA_Priority1, TRUE);
!
call TxDMAChannel.setTargetAddr(0x41900010);
call TxDMAChannel.enableSourceAddrIncrement(TRUE);
***************
*** 122,126 ****
call RxDMAChannel.setMaxBurstSize(DMA_8ByteBurst);
call RxDMAChannel.setTransferWidth(DMA_1ByteWidth);
!
call GPIOControl.init();
--- 128,132 ----
call RxDMAChannel.setMaxBurstSize(DMA_8ByteBurst);
call RxDMAChannel.setTransferWidth(DMA_1ByteWidth);
! #endif
call GPIOControl.init();
***************
*** 131,135 ****
! CKEN |= (CKEN4_SSP3);
// Serial Clock Rate = 6.5 MHz, Frame Format = SPI, Data Size = 8-bit
--- 137,141 ----
! CKEN |= (CKEN_CKEN4);
// Serial Clock Rate = 6.5 MHz, Frame Format = SPI, Data Size = 8-bit
***************
*** 139,144 ****
SSCR0_3 = (SSCR0_SCR(1) | SSCR0_FRF(0) | SSCR0_DSS(0x7) | SSCR0_SSE);
- call DMAControl.start();
-
call GPIOControl.start();
return SUCCESS;
--- 145,148 ----
***************
*** 147,155 ****
command result_t StdControl.stop() {
- call DMAControl.stop();
call GPIOControl.stop();
SSCR0_3 &= ~(SSCR0_SSE); // Disable SSP3 port
! CKEN &= ~(CKEN4_SSP3);
return SUCCESS;
--- 151,158 ----
command result_t StdControl.stop() {
call GPIOControl.stop();
SSCR0_3 &= ~(SSCR0_SSE); // Disable SSP3 port
! CKEN &= ~(CKEN_CKEN4);
return SUCCESS;
***************
*** 483,488 ****
}
! #if DEBUG
trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 readRXFIFO...length=%d\r\n",length);
#endif
--- 486,492 ----
}
! #if RXDEBUG
trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 readRXFIFO...length=%d\r\n",length);
+ startProfile();
#endif
***************
*** 594,597 ****
--- 598,607 ----
DEASSERT_SPI_CS;
ret = SUCCESS;
+
+ #if RXDEBUG
+ stopProfile();
+ printProfile(profilePrintAll);
+ #endif
+
}
#endif
***************
*** 628,632 ****
async command result_t HPLCC2420FIFO.writeTXFIFO(uint8_t length, uint8_t *data) {
uint8_t OkToUse;
-
if(getSSPPort()==FAIL){
//something else is using the radio, print a message and return;
--- 638,641 ----
***************
*** 635,641 ****
}
! #if DEBUG
trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 writeTXFIFO length=%d\r\n",length);
#endif
atomic {
txbuf = data;
--- 644,652 ----
}
! #if TXDEBUG
trace(HPLCC2420_DBG_LEVEL,"HPLCC2420 writeTXFIFO length=%d\r\n",length);
+ startProfile();
#endif
+
atomic {
txbuf = data;
***************
*** 704,708 ****
return 0;
}
!
return SUCCESS;
}
--- 715,722 ----
return 0;
}
! #if TXDEBUG
! stopProfile();
! printProfile(profilePrintAll);
! #endif
return SUCCESS;
}
Index: HPLFFUARTC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLFFUARTC.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** HPLFFUARTC.nc 26 Jul 2005 01:34:24 -0000 1.1
--- HPLFFUARTC.nc 10 Oct 2006 01:57:44 -0000 1.2
***************
*** 56,59 ****
UART = UARTM;
! UARTM.Interrupt -> PXA27XInterruptM.PXA27XIrq[PPID_FFUART];
}
--- 56,59 ----
UART = UARTM;
! UARTM.Interrupt -> PXA27XInterruptM.PXA27XIrq[IID_FFUART];
}
Index: HPLFFUARTM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLFFUARTM.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** HPLFFUARTM.nc 8 Dec 2005 23:13:06 -0000 1.3
--- HPLFFUARTM.nc 10 Oct 2006 01:57:44 -0000 1.4
***************
*** 61,65 ****
{
uint8_t baudrate = UART_BAUD_115200;
!
async event void Interrupt.fired(){
uint8_t error,intSource = FFIIR;
--- 61,65 ----
{
uint8_t baudrate = UART_BAUD_115200;
!
async event void Interrupt.fired(){
uint8_t error,intSource = FFIIR;
***************
*** 157,164 ****
//configure the GPIO Alt functions and directions
! _PXA_setaltfn(96,3, GPIO_IN);
! _PXA_setaltfn(99,3, GPIO_OUT); //FFTXD
!
FFLCR |=LCR_DLAB; //turn on DLAB so we can change the divisor
#if 0
--- 157,165 ----
//configure the GPIO Alt functions and directions
! GPIO_SET_ALT_FUNC(96,3, GPIO_IN);
! GPIO_SET_ALT_FUNC(99,3, GPIO_OUT); //FFTXD
! call Interrupt.disable();
! atomic{
FFLCR |=LCR_DLAB; //turn on DLAB so we can change the divisor
#if 0
***************
*** 167,174 ****
#else
// USE baudrate variable
! setBaudRate(baudrate);
#endif
FFLCR &= ~(LCR_DLAB); //turn off DLAB
!
FFLCR |= 0x3; //configure to 8 bits
--- 168,176 ----
#else
// USE baudrate variable
!
! setBaudRate(baudrate);
#endif
FFLCR &= ~(LCR_DLAB); //turn off DLAB
! }
FFLCR |= 0x3; //configure to 8 bits
***************
*** 194,198 ****
//__REG(0x40D00004) |= (1<<21);
! CKEN |= CKEN6_FFUART; //enable the UART's clk
// }
return SUCCESS;
--- 196,200 ----
//__REG(0x40D00004) |= (1<<21);
! CKEN |= CKEN_CKEN6; //enable the UART's clk
// }
return SUCCESS;
***************
*** 206,210 ****
async command result_t UART.stop() {
! CKEN &= ~CKEN6_FFUART;
return SUCCESS;
}
--- 208,212 ----
async command result_t UART.stop() {
! CKEN &= ~CKEN_CKEN6;
return SUCCESS;
}
Index: HPLSTUARTC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLSTUARTC.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** HPLSTUARTC.nc 15 Feb 2005 18:09:48 -0000 1.1
--- HPLSTUARTC.nc 10 Oct 2006 01:57:44 -0000 1.2
***************
*** 56,59 ****
UART = UARTM;
! UARTM.Interrupt -> PXA27XInterruptM.PXA27XIrq[PPID_STUART];
}
--- 56,59 ----
UART = UARTM;
! UARTM.Interrupt -> PXA27XInterruptM.PXA27XIrq[IID_STUART];
}
Index: HPLSTUARTM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLSTUARTM.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** HPLSTUARTM.nc 6 Sep 2005 18:13:58 -0000 1.3
--- HPLSTUARTM.nc 10 Oct 2006 01:57:44 -0000 1.4
***************
*** 96,104 ****
//configure the GPIO Alt functions and directions
! _GPIO_setaltfn(46,2);
! _GPIO_setaltfn(47,1);
!
! _GPDR(46) &= ~_GPIO_bit(46);
! _GPDR(47) |= _GPIO_bit(47);
STLCR |=LCR_DLAB; //turn on DLAB so we can change the divisor
--- 96,101 ----
//configure the GPIO Alt functions and directions
! GPIO_SET_ALT_FUNC(46,2,GPIO_IN);
! GPIO_SET_ALT_FUNC(47,1,GPIO_OUT);
STLCR |=LCR_DLAB; //turn on DLAB so we can change the divisor
***************
*** 130,134 ****
//__REG(0x40D00004) |= (1<<21);
! CKEN |= CKEN5_STUART; //enable the UART's clk
// }
return SUCCESS;
--- 127,131 ----
//__REG(0x40D00004) |= (1<<21);
! CKEN |= CKEN_CKEN5; //enable the UART's clk
// }
return SUCCESS;
***************
*** 140,144 ****
async command result_t UART.stop() {
! CKEN &= ~CKEN5_STUART;
return SUCCESS;
}
--- 137,141 ----
async command result_t UART.stop() {
! CKEN &= ~CKEN_CKEN5;
return SUCCESS;
}
Index: HPLUSBClientGPIOM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/HPLUSBClientGPIOM.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** HPLUSBClientGPIOM.nc 2 Sep 2005 23:35:29 -0000 1.4
--- HPLUSBClientGPIOM.nc 10 Oct 2006 01:57:44 -0000 1.5
***************
*** 13,30 ****
async command result_t HPLUSBClientGPIO.init(){
! _GPDR(USBC_GPION_DET) &= ~_GPIO_bit(USBC_GPION_DET);
! _GPDR(USBC_GPIOX_EN) |= _GPIO_bit(USBC_GPIOX_EN);
! _GPSR(USBC_GPIOX_EN) |= _GPIO_bit(USBC_GPIOX_EN);
return SUCCESS;
}
async command result_t HPLUSBClientGPIO.stop(){
! _GPCR(USBC_GPIOX_EN) |= _GPIO_bit(USBC_GPIOX_EN);
return SUCCESS;
}
async command result_t HPLUSBClientGPIO.checkConnection(){
! if(isFlagged(_GPLR(USBC_GPION_DET), _GPIO_bit(USBC_GPION_DET)))
return SUCCESS;
else
--- 13,30 ----
async command result_t HPLUSBClientGPIO.init(){
! GPDR(USBC_GPION_DET) &= ~GPIO_BIT(USBC_GPION_DET);
! GPDR(USBC_GPIOX_EN) |= GPIO_BIT(USBC_GPIOX_EN);
! GPSR(USBC_GPIOX_EN) |= GPIO_BIT(USBC_GPIOX_EN);
return SUCCESS;
}
async command result_t HPLUSBClientGPIO.stop(){
! GPCR(USBC_GPIOX_EN) |= GPIO_BIT(USBC_GPIOX_EN);
return SUCCESS;
}
async command result_t HPLUSBClientGPIO.checkConnection(){
! if(isFlagged(GPLR(USBC_GPION_DET), GPIO_BIT(USBC_GPION_DET)))
return SUCCESS;
else
Index: PMIC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/PMIC.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** PMIC.nc 18 Oct 2005 21:11:20 -0000 1.2
--- PMIC.nc 10 Oct 2006 01:57:44 -0000 1.3
***************
*** 55,58 ****
command result_t enableAutoCharging(bool enable);
command result_t enableManualCharging(bool enable);
! command result_t chargingStatus(uint8_t *vBat, uint8_t *vChg, uint8_t *iChg);
}
--- 55,63 ----
command result_t enableAutoCharging(bool enable);
command result_t enableManualCharging(bool enable);
! command result_t chargingStatus(uint8_t *vBat, uint8_t *vChg, uint8_t *iChg, uint8_t* chargeControl);
! command result_t enable5V(bool enable);
! command result_t enableSBVoltage_High(bool enable, uint8_t value);
! command result_t enableSBVoltage_Low(bool enable, uint8_t value);
! command result_t setIOVoltage(uint8_t value);
!
}
Index: PMICC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/PMICC.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** PMICC.nc 26 Sep 2005 02:22:52 -0000 1.1
--- PMICC.nc 10 Oct 2006 01:57:44 -0000 1.2
***************
*** 57,61 ****
StdControl = PMICM;
PMIC = PMICM;
! PMICM.PI2CInterrupt -> PXA27XInterruptM.PXA27XIrq[PPID_PWR_I2C];
PMICM.PMICInterrupt -> PXA27XGPIOIntC.PXA27XGPIOInt[1];
PMICM.chargeMonitorTimer -> TimerC.Timer[unique("Timer")];
--- 57,61 ----
StdControl = PMICM;
PMIC = PMICM;
! PMICM.PI2CInterrupt -> PXA27XInterruptM.PXA27XIrq[IID_PWR_I2C];
PMICM.PMICInterrupt -> PXA27XGPIOIntC.PXA27XGPIOInt[1];
PMICM.chargeMonitorTimer -> TimerC.Timer[unique("Timer")];
***************
*** 66,68 ****
--- 66,71 ----
BluSHC.BluSH_AppI[unique("BluSH")] -> PMICM.AutoCharging;
BluSHC.BluSH_AppI[unique("BluSH")] -> PMICM.ChargingStatus;
+ BluSHC.BluSH_AppI[unique("BluSH")] -> PMICM.ReadPMIC;
+ BluSHC.BluSH_AppI[unique("BluSH")] -> PMICM.WritePMIC;
+ BluSHC.BluSH_AppI[unique("BluSH")] -> PMICM.SetCoreVoltage;
}
Index: PMICM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/PMICM.nc,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** PMICM.nc 8 Dec 2005 23:13:06 -0000 1.3
--- PMICM.nc 10 Oct 2006 01:57:44 -0000 1.4
***************
*** 42,45 ****
--- 42,47 ----
*/
+ #define MAX_BLOCKING_WAIT_COUNT (1000)
+
#define START_RADIO_LDO 1
#define START_SENSOR_BOARD_LDO 1
***************
*** 53,57 ****
*/
#ifndef ENABLE_BUCK2
! #define ENABLE_BUCK2 1
#endif
--- 55,59 ----
*/
#ifndef ENABLE_BUCK2
! #define ENABLE_BUCK2 0
#endif
***************
*** 65,68 ****
--- 67,74 ----
interface BluSH_AppI as ManualCharging;
interface BluSH_AppI as ChargingStatus;
+ interface BluSH_AppI as ReadPMIC;
+ interface BluSH_AppI as WritePMIC;
+ interface BluSH_AppI as SetCoreVoltage;
+
interface PMIC;
}
***************
*** 79,87 ****
bool gotReset;
!
command result_t StdControl.init(){
! CKEN |= CKEN15_PMI2C;
PCFR |= PCFR_PI2C_EN;
PICR = ICR_IUE | ICR_SCLE;
atomic{
gotReset=FALSE;
--- 85,99 ----
bool gotReset;
!
! TOSH_ASSIGN_PIN(PMIC_TXON, A, 108);
!
command result_t StdControl.init(){
! CKEN |= CKEN_CKEN15;
PCFR |= PCFR_PI2C_EN;
PICR = ICR_IUE | ICR_SCLE;
+
+ TOSH_MAKE_PMIC_TXON_OUTPUT();
+ TOSH_CLR_PMIC_TXON_PIN();
+
atomic{
gotReset=FALSE;
***************
*** 92,101 ****
result_t readPMIC(uint8_t address, uint8_t *value, uint8_t numBytes){
//send the PMIC the address that we want to read
if(numBytes > 0){
PIDBR = PMIC_SLAVE_ADDR<<1;
PICR |= ICR_START;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
!
//actually send the address terminated with a STOP
PIDBR = address;
--- 104,123 ----
result_t readPMIC(uint8_t address, uint8_t *value, uint8_t numBytes){
//send the PMIC the address that we want to read
+
+ uint32_t loopCount;
+
+ #ifdef XDB_SIM
+ return SUCCESS;
+ #endif
+
if(numBytes > 0){
PIDBR = PMIC_SLAVE_ADDR<<1;
PICR |= ICR_START;
PICR |= ICR_TB;
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: readPMIC() Unable to obtain bus\r\n");
! return FAIL;
! }
//actually send the address terminated with a STOP
PIDBR = address;
***************
*** 103,107 ****
PICR |= ICR_STOP;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
PICR &= ~ICR_STOP;
--- 125,134 ----
PICR |= ICR_STOP;
PICR |= ICR_TB;
!
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: readPMIC() Unable to send address\r\n");
! return FAIL;
! }
PICR &= ~ICR_STOP;
***************
*** 111,115 ****
PICR |= ICR_START;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
PICR &= ~ICR_START;
--- 138,148 ----
PICR |= ICR_START;
PICR |= ICR_TB;
!
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: readPMIC() unable to write slave address\r\n");
! return FAIL;
! }
!
PICR &= ~ICR_START;
***************
*** 117,121 ****
while (numBytes > 1){
PICR |= ICR_TB;
! while(PICR & ICR_TB);
*value = PIDBR;
value++;
--- 150,160 ----
while (numBytes > 1){
PICR |= ICR_TB;
!
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: readPMIC() Unable to read byte %d from PMIC\r\n", numBytes);
! return FAIL;
! }
!
*value = PIDBR;
value++;
***************
*** 126,130 ****
PICR |= ICR_ACKNAK;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
*value = PIDBR;
PICR &= ~ICR_STOP;
--- 165,175 ----
PICR |= ICR_ACKNAK;
PICR |= ICR_TB;
!
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: readPMIC() Unable to read final byte from PMIC\r\n");
! return FAIL;
! }
!
*value = PIDBR;
PICR &= ~ICR_STOP;
***************
*** 139,158 ****
result_t writePMIC(uint8_t address, uint8_t value){
PIDBR = PMIC_SLAVE_ADDR<<1;
PICR |= ICR_START;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
PIDBR = address;
PICR &= ~ICR_START;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
PIDBR = value;
PICR |= ICR_STOP;
PICR |= ICR_TB;
! while(PICR & ICR_TB);
PICR &= ~ICR_STOP;
!
return SUCCESS;
}
--- 184,222 ----
result_t writePMIC(uint8_t address, uint8_t value){
+
+ uint32_t loopCount;
+
+ #ifdef XDB_SIM
+ return SUCCESS;
+ #endif
+
PIDBR = PMIC_SLAVE_ADDR<<1;
PICR |= ICR_START;
PICR |= ICR_TB;
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: writePMIC() Unable to write slave address\r\n");
! return FAIL;
! }
PIDBR = address;
PICR &= ~ICR_START;
PICR |= ICR_TB;
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: writePMIC() Unable to write target register address\r\n");
! return FAIL;
! }
PIDBR = value;
PICR |= ICR_STOP;
PICR |= ICR_TB;
! for(loopCount = 0; ((PICR & ICR_TB) && (loopCount < MAX_BLOCKING_WAIT_COUNT)); loopCount++);
! if(loopCount == MAX_BLOCKING_WAIT_COUNT){
! trace(DBG_USR1,"FATAL ERROR: writePMIC() Unable to write value\r\n");
! return FAIL;
! }
PICR &= ~ICR_STOP;
!
return SUCCESS;
}
***************
*** 224,227 ****
--- 288,298 ----
startLDOs();
+
+ // call PMIC.enableSBVoltage_High(TRUE, LDO_TRIM_3P0);
+ //call PMIC.setIOVoltage(LDO_TRIM_3P0);
+
+ //see if the charger is present and start if it is
+ //call PMIC.enableManualCharging(TRUE);
+
return SUCCESS;
}
***************
*** 230,234 ****
call PI2CInterrupt.disable();
call PMICInterrupt.disable();
! CKEN &= ~CKEN15_PMI2C;
PICR = 0;
--- 301,305 ----
call PI2CInterrupt.disable();
call PMICInterrupt.disable();
! CKEN &= ~CKEN_CKEN15;
PICR = 0;
***************
*** 285,288 ****
--- 356,371 ----
* The Buck2 controls the core voltage, set to appropriate trim value
*/
+ command result_t PMIC.enable5V(bool enable){
+ uint8_t oldval;
+ readPMIC(PMIC_USBPUMP,&oldval,1);
+ if(enable){
+ oldval |= USBPUMP_USBVE;
+ }
+ else{
+ oldval &= ~(USBPUMP_USBVE);
+ }
+ writePMIC(PMIC_USBPUMP,oldval);
+ }
+
command result_t PMIC.setCoreVoltage(uint8_t trimValue) {
writePMIC(PMIC_BUCK2_REG1, (trimValue & B2R1_TRIM_MASK) | B2R1_GO);
***************
*** 290,293 ****
--- 373,440 ----
}
+ command result_t PMIC.enableSBVoltage_High(bool enable, uint8_t value){
+ //LDO 11
+ uint8_t oldVal, newVal;
+
+ //enable or disable the LDO
+ readPMIC(PMIC_A_REG_CONTROL_1, &oldVal, 1);
+ newVal = (enable == TRUE)? (oldVal | ARC1_LDO11_EN) : (oldVal & ~ARC1_LDO11_EN);
+ writePMIC(PMIC_A_REG_CONTROL_1, newVal);
+
+ readPMIC(PMIC_B_REG_CONTROL_2, &oldVal, 1);
+ newVal = (enable == TRUE)? (oldVal | BRC2_LDO11_EN) : (oldVal & ~BRC2_LDO11_EN);
+ writePMIC(PMIC_B_REG_CONTROL_2, newVal);
+
+ readPMIC(PMIC_STARTUP_CONTROL, &oldVal, 1);
+ newVal = (enable == TRUE)? (oldVal | STARTUPCONTROL_LDO11START) : (oldVal & ~(STARTUPCONTROL_LDO11START));
+ writePMIC(PMIC_STARTUP_CONTROL, newVal);
+
+ //set the right value
+ if(enable == TRUE){
+ readPMIC(PMIC_LDO10_LDO11,&oldVal, 1);
+ newVal = PMIC_SET_LDOHIGH_TRIM(oldVal, value);
+ writePMIC(PMIC_LDO10_LDO11,newVal);
+ }
+ return SUCCESS;
+ }
+
+ command result_t PMIC.enableSBVoltage_Low(bool enable, uint8_t value){
+ //LDO 10
+ uint8_t oldVal, newVal;
+
+ //enable or disable the LDO
+ readPMIC(PMIC_A_REG_CONTROL_1, &oldVal, 1);
+ newVal = (enable == TRUE)? (oldVal | ARC1_LDO10_EN) : (oldVal & ~ARC1_LDO10_EN);
+ writePMIC(PMIC_A_REG_CONTROL_1, newVal);
+
+ readPMIC(PMIC_B_REG_CONTROL_2, &oldVal, 1);
+ newVal = (enable == TRUE)? (oldVal | BRC2_LDO10_EN) : (oldVal & ~BRC2_LDO10_EN);
+ writePMIC(PMIC_B_REG_CONTROL_2, newVal);
+
+ readPMIC(PMIC_STARTUP_CONTROL, &oldVal, 1);
+ newVal = (enable == TRUE)? (oldVal | STARTUPCONTROL_LDO10START) : (oldVal & ~(STARTUPCONTROL_LDO10START));
+ writePMIC(PMIC_STARTUP_CONTROL, newVal);
+
+
+ //set the right value
+ if(enable == TRUE){
+ readPMIC(PMIC_LDO10_LDO11,&oldVal, 1);
+ newVal = PMIC_SET_LDOLOW_TRIM(oldVal, value);
+ writePMIC(PMIC_LDO10_LDO11,newVal);
+ }
+
+ }
+
+ command result_t PMIC.setIOVoltage(uint8_t value){
+ //LDO 18
+ uint8_t oldVal, newVal;
+
+ readPMIC(PMIC_LDO18_LDO19,&oldVal, 1);
+ newVal = PMIC_SET_LDOLOW_TRIM(oldVal, value);
+ writePMIC(PMIC_LDO18_LDO19,newVal);
+ return SUCCESS;
+ }
+
+
command result_t PMIC.shutDownLDOs() {
uint8_t oldVal, newVal;
***************
*** 324,329 ****
//read out the old value so that we can reset at the end
rval= readPMIC(PMIC_ADC_MAN_CONTROL, &oldval,1);
! rcombine(rval,writePMIC(PMIC_ADC_MAN_CONTROL, PMIC_AMC_ADCMUX(channel) |
! PMIC_AMC_MAN_CONV | PMIC_AMC_LDO_INT_Enable));
rcombine(rval, readPMIC(PMIC_MAN_RES,val,1));
//reset to old state
--- 471,477 ----
//read out the old value so that we can reset at the end
rval= readPMIC(PMIC_ADC_MAN_CONTROL, &oldval,1);
! rcombine(rval,writePMIC(PMIC_ADC_MAN_CONTROL, PMIC_AMC_LDO_INT_Enable));
! TOSH_uwait(20);
! rcombine(rval,writePMIC(PMIC_ADC_MAN_CONTROL, PMIC_AMC_ADCMUX(channel) | PMIC_AMC_MAN_CONV | PMIC_AMC_LDO_INT_Enable));
rcombine(rval, readPMIC(PMIC_MAN_RES,val,1));
//reset to old state
***************
*** 331,335 ****
return rval;
}
!
command result_t PMIC.getBatteryVoltage(uint8_t *val){
//for now, let's use the manual conversion mode
--- 479,483 ----
return rval;
}
!
command result_t PMIC.getBatteryVoltage(uint8_t *val){
//for now, let's use the manual conversion mode
***************
*** 338,346 ****
command result_t PMIC.chargingStatus(uint8_t *vBat, uint8_t *vChg,
! uint8_t *iChg){
! getPMICADCVal(0, vBat);
! getPMICADCVal(2, vChg);
! getPMICADCVal(1, iChg);
! return SUCCESS;
}
--- 486,501 ----
command result_t PMIC.chargingStatus(uint8_t *vBat, uint8_t *vChg,
! uint8_t *iChg, uint8_t *chargeControl){
!
! if(vBat && vChg && iChg && chargeControl){
! readPMIC(PMIC_VBAT_RES,vBat,1);
! readPMIC(PMIC_VCHMIN_RES,vChg,1);
! readPMIC(PMIC_ICHAVERAGE_RES,iChg,1);
! readPMIC(PMIC_CHARGE_CONTROL,chargeControl, 1);
! return SUCCESS;
! }
! else{
! return FAIL;
! }
}
***************
*** 357,368 ****
getPMICADCVal(2, &val);
//if charger is present due some stuff...75 should be 4.65V or so
! if(val > 75 ) {
trace(DBG_USR1,"Charger Voltage is %.3fV...enabling charger...\r\n", ((val*6) * .01035));
//write the total timeout to be 8 hours
writePMIC(PMIC_TCTR_CONTROL,8);
//enable the charger at 100mA and 4.35V
! writePMIC(PMIC_CHARGE_CONTROL,PMIC_CC_CHARGE_ENABLE | PMIC_CC_ISET(1) | PMIC_CC_VSET(7));
//turn on the LED
writePMIC(PMIC_LED1_CONTROL,0x80);
//start a timer to monitor our progress every 5 minutes!
call chargeMonitorTimer.start(TIMER_REPEAT,300000);
--- 512,526 ----
getPMICADCVal(2, &val);
//if charger is present due some stuff...75 should be 4.65V or so
! if(val > 70 ) {
trace(DBG_USR1,"Charger Voltage is %.3fV...enabling charger...\r\n", ((val*6) * .01035));
//write the total timeout to be 8 hours
writePMIC(PMIC_TCTR_CONTROL,8);
//enable the charger at 100mA and 4.35V
! writePMIC(PMIC_CHARGE_CONTROL,PMIC_CC_CHARGE_ENABLE | PMIC_CC_ISET(1) | PMIC_CC_VSET(4));
//turn on the LED
writePMIC(PMIC_LED1_CONTROL,0x80);
+ //turn on the autoADC features that we care about
+ writePMIC(PMIC_ADC_MAN_CONTROL,PMIC_AMC_LDO_INT_Enable);
+ writePMIC(PMIC_ADC_AUTO_CONTROL,0xE);
//start a timer to monitor our progress every 5 minutes!
call chargeMonitorTimer.start(TIMER_REPEAT,300000);
***************
*** 376,383 ****
call PMIC.getBatteryVoltage(&val);
trace(DBG_USR1,"Disabling Charger...Battery Voltage is %.3fV\r\n", (val * .01035) + 2.65);
! //disable everything that we enabled
! writePMIC(PMIC_TCTR_CONTROL,0);
! writePMIC(PMIC_CHARGE_CONTROL,0);
! writePMIC(PMIC_LED1_CONTROL,0x00);
}
return SUCCESS;
--- 534,543 ----
call PMIC.getBatteryVoltage(&val);
trace(DBG_USR1,"Disabling Charger...Battery Voltage is %.3fV\r\n", (val * .01035) + 2.65);
! //disable everything that we enabled
! writePMIC(PMIC_TCTR_CONTROL,0x0);
! writePMIC(PMIC_CHARGE_CONTROL,0x0);
! writePMIC(PMIC_LED1_CONTROL,0x0);
! writePMIC(PMIC_ADC_MAN_CONTROL,0x0);
! writePMIC(PMIC_ADC_AUTO_CONTROL,0x0);
}
return SUCCESS;
***************
*** 423,429 ****
command BluSH_result_t ChargingStatus.callApp(char *cmdBuff, uint8_t cmdLen,
char *resBuff, uint8_t resLen){
! uint8_t vBat, vChg, iChg;
! call PMIC.chargingStatus(&vBat, &vChg, &iChg);
! trace(DBG_USR1,"vBat = %.3fV %vChg = %.3fV iChg = %.3fA\r\n", (vBat * .01035) + 2.65,((vChg*6) * .01035), ((iChg * .01035)/1.656));
return BLUSH_SUCCESS_DONE;
}
--- 583,590 ----
command BluSH_result_t ChargingStatus.callApp(char *cmdBuff, uint8_t cmdLen,
char *resBuff, uint8_t resLen){
! uint8_t vBat, vChg, iChg,chargeControl;
! call PMIC.chargingStatus(&vBat, &vChg, &iChg,&chargeControl);
! trace(DBG_USR1,"vBat = %.3fV %vChg = %.3fV iChg = %.3fA chargeControl =%#x\r\n", (vBat * .01035) + 2.65,((vChg*6) * .01035), ((iChg * .01035)/1.656),chargeControl);
!
return BLUSH_SUCCESS_DONE;
}
***************
*** 463,465 ****
--- 624,699 ----
return BLUSH_SUCCESS_DONE;
}
+
+ command BluSH_result_t ReadPMIC.getName(char *buff, uint8_t len){
+
+ const char name[] = "ReadPMIC";
+ strcpy(buff,name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+
+ command BluSH_result_t ReadPMIC.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen){
+ uint32_t address;
+ uint8_t data;
+ if(strlen(cmdBuff) <strlen("ReadPMIC 22")){
+ sprintf(resBuff,"Please enter an address to read\r\n");
+ }
+ else{
+ sscanf(cmdBuff,"ReadPMIC %x", &address);
+ readPMIC(address, &data,1);
+ trace(DBG_USR1,"read %#x from PMIC address %#x\r\n",data, address);
+ }
+ return BLUSH_SUCCESS_DONE;
+ }
+ command BluSH_result_t WritePMIC.getName(char *buff, uint8_t len){
+
+ const char name[] = "WritePMIC";
+ strcpy(buff,name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+
+ command BluSH_result_t WritePMIC.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen){
+ uint32_t address, data;
+ if(strlen(cmdBuff) <strlen("WritePMIC 22 22")){
+ sprintf(resBuff,"Please enter an address and a value to write\r\n");
+ }
+ else{
+ sscanf(cmdBuff,"WritePMIC %x %x", &address, &data);
+ writePMIC(address, data);
+ trace(DBG_USR1,"Wrote %#x to PMIC address %#x\r\n",data, address);
+ }
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t SetCoreVoltage.getName(char *buff, uint8_t len){
+
+ const char name[] = "SetCoreVoltage";
+ strcpy(buff,name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+
+ command BluSH_result_t SetCoreVoltage.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen){
+ uint32_t voltage;
+ uint32_t trim;
+ if(strlen(cmdBuff) <strlen("SetCoreVoltage 222")){
+ sprintf(resBuff,"Please enter the voltage in mV, range 850 - 1625 in 25mV steps\r\n");
+ }
+ else{
+ sscanf(cmdBuff,"SetCoreVoltage %d", &voltage);
+ if ((voltage < 850) || (voltage > 1625)) {
+ trace(DBG_USR1, "Invalid voltage %d mV", voltage);
+ return BLUSH_SUCCESS_DONE;
+ }
+ // convert to trim value
+ trim = (uint8_t) ((voltage - 850) / 25);
+ call PMIC.setCoreVoltage(trim);
+ trace(DBG_USR1,"Wrote voltage %d, trim %d\r\n",trim*25+850, trim);
+ }
+ return BLUSH_SUCCESS_DONE;
+ }
}
Index: SSP.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SSP.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** SSP.nc 26 Jul 2005 01:36:07 -0000 1.1
--- SSP.nc 10 Oct 2006 01:57:44 -0000 1.2
***************
*** 6,24 ****
interface SSP{
! command result_t init(); //generic command to configure things the way we defintiely need.
command result_t setSSPFormat(SSPFrameFormat_t format);
command result_t setDataWidth(SSPDataWidth_t width);
command result_t enableInvertedSFRM(bool enable);
command result_t setRxFifoLevel(SSPFifoLevel_t level);
command result_t setTxFifoLevel(SSPFifoLevel_t level);
command result_t setMicrowireTxSize(SSPMicrowireTxSize_t size);
! //clk specific configuration routines
command result_t setClkRate(uint16_t clkdivider);
- command result_t setClkMode(SSPClkMode_t);
! //master vs slave configuration routines
! command result_t setMasterSCLK(bool enable);
! command result_t setMasterSFRM(bool enable);
! command result_t setReceiveWithoutTransmit(bool enable);
}
--- 6,146 ----
interface SSP{
!
! /****************************************
! *master vs slave configuration routines
! ****************************************/
!
! /**
! *configure the port to be Master of SCLK
! *
! *@param enable: port is master of SCLK if TRUE, slave if FALSE
! *
! *@return FAIL if error, SUCCESS otherwise
! */
! command result_t setMasterSCLK(bool enable);
!
!
! /**
! *configure the port to be Master of SFRM
! *
! *@param enable: port is master of SFRM if TRUE, slave if FALSE
! *
! *@return FAIL if error, SUCCESS otherwise
! */
! command result_t setMasterSFRM(bool enable);
!
! /**
! *configure the port to be in ReceiveWithoutTransmit mode
! *
! *@param enable: port only receives if TRUE, slave if FALSE
! *
! *@return FAIL if error, SUCCESS otherwise
! */
! command result_t setReceiveWithoutTransmit(bool enable);
!
! /**
! *configure the port to be in SPI, SSP, Microwire, or PSP modes
! *
! *@param format: format to use...see SSP.h for encodings
! *
! *@return FAIL if error, SUCCESS otherwise
! */
command result_t setSSPFormat(SSPFrameFormat_t format);
+
+ /**
+ *configure how many bits wide the port should consider 1 sample
+ *
+ *@param width: bits to use...see SSP.h for encodings
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
command result_t setDataWidth(SSPDataWidth_t width);
+
+ /**
+ *configure the port to invert the SFRM signal
+ *
+ *@param enable: invert the signal if TRUE, don't invert if FALSE
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
command result_t enableInvertedSFRM(bool enable);
+
+ /**
+ *configure the port to set the idle state of the CLK High (only valid in SPI mode)
+ *
+ *@param enable: Clk's resting state is HIGH if TRUE, LOW if FALSE
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
+ command result_t enableSPIClkHigh(bool enable);
+
+ /**
+ *configure the port to shift the SPIClk by 1/2 of a clock (only valid in SPI mode)
+ *
+ *@param enable: Clk's is shifted if enable if TRUE, not shifted if FALSE
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
+ command result_t shiftSPIClk(bool enable);
+
+ /**
+ *configure the depth of the RX FIFO at which point an interrupt is generated
+ *
+ *@param level: fifo level...see SSP.h for encodings
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
command result_t setRxFifoLevel(SSPFifoLevel_t level);
+
+ /**
+ *configure the depth of the TX FIFO at which point an interrupt is generated
+ *
+ *@param level: fifo level...see SSP.h for encodings
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
command result_t setTxFifoLevel(SSPFifoLevel_t level);
+
+ /**
+ *configure the width of microwire commands
+ *
+ *@param size: 8 bit or 16 bit commands...see SSP.h for encodings
+ *
+ *@return FAIL if error, SUCCESS otherwise
+ */
command result_t setMicrowireTxSize(SSPMicrowireTxSize_t size);
!
!
! /************************************
! *clk specific configuration routines
! ************************************/
!
! /**
! *configure the clock divider for the port.
! *
! *@param clkdivider: divider for the port...clk will be 13M/(clkdivider)
! *
! *@return FAIL if error, SUCCESS otherwise
! */
command result_t setClkRate(uint16_t clkdivider);
! /**
! *configure the Clk Mode of the port.
! *
! *@param mode: SSP_normalmode for normal operation, SSP_networkmode for
! * network mode
! *
! *@return FAIL if error, SUCCESS otherwise
! */
! command result_t setClkMode(SSPClkMode_t mode);
+ command result_t enableManualRxPinCtrl(bool enable);
+ command result_t enableManualTxPinCtrl(bool enable);
+ command result_t enableManualSFRMPinCtrl(bool enable);
+ command result_t enableManualSCLKPinCtrl(bool enable);
+
+
+
+
+
}
Index: SSP1C.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SSP1C.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** SSP1C.nc 18 Aug 2005 22:32:21 -0000 1.2
--- SSP1C.nc 10 Oct 2006 01:57:44 -0000 1.3
***************
*** 4,24 ****
provides{
interface BulkTxRx;
- interface SingleTxRx;
interface SSP;
}
}
implementation{
! components SSP1M,
! HPLSSP1M,
PXA27XDMAC,
PXA27XInterruptM;
! BulkTxRx=SSP1M.BulkTxRx;
! SingleTxRx=SSP1M.SingleTxRx;
! SSP=SSP1M.SSP;
! SSP1M.HPLSSP->HPLSSP1M;
! SSP1M.SSPInterrupt -> PXA27XInterruptM.PXA27XIrq[PPID_SSP1];
! SSP1M.RxDMAChannel -> PXA27XDMAC.PXA27XDMAChannel[unique("DMAChannel")];
! SSP1M.TxDMAChannel -> PXA27XDMAC.PXA27XDMAChannel[unique("DMAChannel")];
! SSP1M.DMAControl -> PXA27XDMAC.StdControl;
}
--- 4,19 ----
provides{
interface BulkTxRx;
interface SSP;
}
}
implementation{
! components SSP1M as SSPM,
PXA27XDMAC,
PXA27XInterruptM;
! BulkTxRx=SSPM.BulkTxRx;
! SSP=SSPM.SSP;
! SSPM.SSPInterrupt -> PXA27XInterruptM.PXA27XIrq[IID_SSP1];
! SSPM.RxDMAChannel -> PXA27XDMAC.PXA27XDMAChannel[unique("DMAChannel")];
! SSPM.TxDMAChannel -> PXA27XDMAC.PXA27XDMAChannel[unique("DMAChannel")];
}
Index: SSP1M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SSP1M.nc,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** SSP1M.nc 8 Dec 2005 23:13:06 -0000 1.4
--- SSP1M.nc 10 Oct 2006 01:57:44 -0000 1.5
***************
*** 1,15 ****
! //@author Robbie Adler
includes mmu;
module SSP1M {
provides {
interface BulkTxRx;
- interface SingleTxRx;
interface SSP;
}
uses {
- interface HPLSSP;
interface PXA27XDMAChannel as RxDMAChannel;
interface PXA27XDMAChannel as TxDMAChannel;
- interface StdControl as DMAControl;
interface PXA27XInterrupt as SSPInterrupt;
}
--- 1,15 ----
! /**
! * @author Robbie Adler
! **/
!
includes mmu;
module SSP1M {
provides {
interface BulkTxRx;
interface SSP;
}
uses {
interface PXA27XDMAChannel as RxDMAChannel;
interface PXA27XDMAChannel as TxDMAChannel;
interface PXA27XInterrupt as SSPInterrupt;
}
***************
*** 18,540 ****
implementation {
! //change this value to change the default priority requst for the DMA channel
! #define DEFAULTDMARXPRIORITY (DMA_Priority1|DMA_Priority2|DMA_Priority3|DMA_Priority4)
! #define DEFAULTDMATXPRIORITY (DMA_Priority1|DMA_Priority2|DMA_Priority3|DMA_Priority4)
!
! SSPFrameFormat_t gFrameFormat;
! SSPDataWidth_t gDataWidth;
! bool gEnableInvertedSFRM;
! SSPFifoLevel_t gRxFifoLevel;
! SSPFifoLevel_t gTxFifoLevel;
! SSPMicrowireTxSize_t gMicrowireSize;
! uint16_t gClkdivider;
! SSPClkMode_t gClkMode;
! bool gSlaveClockFreeRunning;
! bool gMasterSCLK;
! bool gMasterSFRM;
! bool gReceiveWithoutTransmit;
! bool gRxFifoOverrun;
! bool gAudioClockSelect;
!
! bool gRxInProgress;
! bool gTxInProgress;
!
! norace uint16_t gNumRxFifoOverruns;
!
! //hack!!!
! norace uint16_t *gRxBuffer;
!
! norace uint16_t gRxNumBytes, gRxBufferPos;
!
! uint32_t createSSCR0();
! uint32_t createSSCR1();
!
! command result_t SSP.init(){
! uint32_t SSCR0, SSCR1;
! //reinitialize global state to allow for reentrancy
! gFrameFormat = SSP_SSP;
! gDataWidth= SSP_16bits;
! gEnableInvertedSFRM= TRUE;
! gRxFifoLevel = SSP_8Samples;
! gTxFifoLevel = SSP_8Samples; //note, this setting will only be used for DMA.. non-DMA will use a value of 1 for simplicity
! gMicrowireSize = SSP_8bitCommands;
! gClkdivider = 1;
! gClkMode = SSP_normalmode;
! gSlaveClockFreeRunning = FALSE;
! gReceiveWithoutTransmit = TRUE;
! gRxFifoOverrun = TRUE;
! gAudioClockSelect = FALSE;
!
! atomic{
! gRxInProgress = FALSE;
! gTxInProgress = FALSE;
! }
! if(gFrameFormat == SSP_PSP){
! call HPLSSP.setSSPSP(SSPSP_SFRMWDTH(0)| SSPSP_SFRMDLY(0) | SSPSP_SCMODE(0));
! }
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1);
!
! SSCR0 = createSSCR0();
! call HPLSSP.setSSCR0(SSCR0);
!
! //hack for now to enable testing of this fuunctionality
! if(gAudioClockSelect == TRUE){
! SSACD_1 = SSACD_ACPS(5) | SSACD_SCDB | SSACD_ACDS(1);
! }
! call SSPInterrupt.allocate();
! call SSPInterrupt.enable();
! call DMAControl.init();
! call DMAControl.start();
! //need to configure SSP pin for correct functionality
! _PXA_setaltfn(SSP1_RXD, SSP1_RXD_ALTFN, GPIO_IN);
! _PXA_setaltfn(SSP1_TXD, SSP1_TXD_ALTFN, GPIO_OUT);
!
! //configure SCLK to run in the correct direction
! if(gMasterSCLK){
! _PXA_setaltfn(SSP1_SCLK, SSP1_SCLK_ALTFN, GPIO_OUT);
! }
! else{
! _PXA_setaltfn(SSP1_SCLK, SSP1_SCLK_ALTFN, GPIO_IN);
! }
!
! //configure SFRM to run in the correct direction
! if(gMasterSFRM){
! _PXA_setaltfn(SSP1_SFRM, SSP1_SFRM_ALTFN, GPIO_OUT);
! }
! else{
! _PXA_setaltfn(SSP1_SFRM, SSP1_SFRM_ALTFN, GPIO_IN);
! }
!
! return SUCCESS;
! }
!
! command result_t SSP.setSSPFormat(SSPFrameFormat_t format){
! gFrameFormat = format;
! return SUCCESS;
! }
!
! command result_t SSP.setDataWidth(SSPDataWidth_t width){
! gDataWidth = width;
! return SUCCESS;
! }
!
! command result_t SSP.enableInvertedSFRM(bool enable){
! gEnableInvertedSFRM= enable;
! return SUCCESS;
! }
!
! command result_t SSP.setRxFifoLevel(SSPFifoLevel_t level){
! gRxFifoLevel = level;
! return SUCCESS;
! }
!
! command result_t SSP.setTxFifoLevel(SSPFifoLevel_t level){
! gTxFifoLevel = level;
! return SUCCESS;
! }
!
! command result_t SSP.setMicrowireTxSize(SSPMicrowireTxSize_t size){
! gMicrowireSize = size;
! return SUCCESS;
! }
! //clk specific configuration routines
!
! command result_t SSP.setClkRate(uint16_t clkdivider){
! gClkdivider = clkdivider;
! return SUCCESS;
! }
!
! command result_t SSP.setClkMode(SSPClkMode_t mode){
! gClkMode = mode;
! return SUCCESS;
! }
!
! command result_t SSP.setMasterSCLK(bool enable){
! gMasterSCLK = enable;
! return SUCCESS;
! }
!
! command result_t SSP.setMasterSFRM(bool enable){
! gMasterSFRM = enable;
! return SUCCESS;
! }
!
! command result_t SSP.setReceiveWithoutTransmit(bool enable){
! gReceiveWithoutTransmit = enable;
! return SUCCESS;
! }
!
! uint32_t createSSCR0(){
!
! uint32_t temp;
! //MOD:
! temp = (gClkMode == SSP_normalmode)? 0 : SSCR0_MOD;
!
! //ACS
! temp |= (gAudioClockSelect == TRUE)? SSCR0_ACS : 0;
!
! //FRDC
! // temp |= FRDC(gFRDC);
!
! //TIM (leave at the default for now)
! // temp |= (gTIM == TRUE)? 0 : SSCR0_TIM;
!
! //RIM (leave at the default for now)
! temp |= (gRxFifoOverrun == TRUE)? 0 : SSCR0_RIM;
!
! //NCS
! // temp |= (gNCS == TRUE)? 0 : SSCR0_NCS;
!
! //EDSS
! temp |= (gDataWidth <= SSP_16bits)? 0 : SSCR0_EDSS;
!
! //SCR
! temp |= SSCR0_SCR(gClkdivider);
!
! //SSE--> don't set it here in order to allow us to be a little more flexible
! //temp |= SSCR0_SSE;
!
! //ECS--> always 0 for iMote2
!
! //FRF
! temp |= SSCR0_FRF(gFrameFormat);
!
! //DSS
! temp |= SSCR0_DSS(gDataWidth);
!
! return temp;
! }
!
! uint32_t createSSCR1(){
!
! uint32_t temp;
!
! //TTELP:
! //temp = (gClkMode == SSP_normalmode)? 0 : SSCR0_MOD;
! temp = 0;
!
! //TTE
! // temp |= (gTTE == SSP_ACS)? 0 : SSCR1_TTE;
!
! //EBCEI
! // temp |= (gEBCEI == SSP_ACS)? 0 : SSCR1_EBCEI;
!
! //SCFR
! temp |= (gSlaveClockFreeRunning == TRUE) ? 0: SSCR1_SCFR;
!
! //ECRA
! // temp |= (gECRA == TRUE)? 0 : SSCR1_ECRA;
! //ECRB
! // temp |= (gECRB == TRUE)? 0 : SSCR1_ECRB;
!
! //SCLKDIR
! temp |= (gMasterSCLK == TRUE)? 0: SSCR1_SCLKDIR;
!
! //SFRMDIR
! temp |= (gMasterSFRM == TRUE)? 0: SSCR1_SFRMDIR;
!
! //RWOT
! temp |= (gReceiveWithoutTransmit == TRUE)? SSCR1_RWOT : 0;
!
! //TRAIL
! // temp |= (gTRAIL == TRUE)? 0 : SSCR1_TRAIL;
!
! //TSRE
! //RSRE
! //TINTE
! //PINTE
! // temp |= (gNCS == TRUE)? 0 : SSCR0_NCS;
!
! //IFS
! temp |= (gEnableInvertedSFRM == TRUE)? SSCR1_IFS : 0;
!
! //STRF
! //EFWR
!
! //RFT
! temp |= SSCR1_RFT(gRxFifoLevel);
!
! //TFT
! temp |= SSCR1_TFT(gTxFifoLevel);
!
! //MWDS
! temp |= (gMicrowireSize == SSP_8bitCommands)? 0 : SSCR1_MWDS;
!
! //SPH
! //SPO
! //LBM
! //TIE
! //RIE
!
! return temp;
! }
!
! void enableRxDMAInterrupt(){
!
! }
!
! void enableTxDMAInterrupt(){
! }
!
! void enableErrorInterrupts(){
!
! }
!
! void enableRxInterrupt(){
! }
! void enableTxInterrupt(){
!
! }
! command result_t BulkTxRx.BulkReceive(uint8_t *RxBuffer, uint16_t NumBytes){
! //need to fake the dma transaction until we get DMA working...
! bool RxInProgress, TxInProgress;
!
! gRxBuffer = (uint16_t *)RxBuffer;
! gRxNumBytes = NumBytes;
! gRxBufferPos = 0;
! gNumRxFifoOverruns=0;
! call SSPInterrupt.disable();
!
! atomic{
! RxInProgress = gRxInProgress;
! TxInProgress = gTxInProgress;
! }
!
!
! if(!RxInProgress){
! if(!TxInProgress){
! //if we're neither transmitting nor receiving, setup the port how we want it be setup
! CKEN |= (CKEN23_SSP1);
! call HPLSSP.setSSCR1(createSSCR1() | SSCR1_TRAIL | SSCR1_RSRE);
! call HPLSSP.setSSTO(512);
!
! call RxDMAChannel.setSourceAddr(0x41000010);
! call RxDMAChannel.setTargetAddr((uint32_t)RxBuffer);
! call RxDMAChannel.enableSourceAddrIncrement(FALSE);
! call RxDMAChannel.enableTargetAddrIncrement(TRUE);
! call RxDMAChannel.enableSourceFlowControl(TRUE);
! call RxDMAChannel.enableTargetFlowControl(FALSE);
! call RxDMAChannel.setTransferLength(NumBytes);
! //need to fix to guarantee that this is generic
! call RxDMAChannel.setMaxBurstSize( ((gRxFifoLevel+1) * (gDataWidth + 1)>>3)>>4);
! call RxDMAChannel.setTransferWidth((gDataWidth+1)>>3);
!
! //request a non-permanent channel
! call RxDMAChannel.requestChannel(DMAID_SSP1_RX,DEFAULTDMARXPRIORITY, FALSE);
! //go
! atomic{
! gRxInProgress = TRUE;
! }
! return SUCCESS;
! }
! }
! else{
! //transaction is in progress...return FAIL...(equivalent to the port being already opened)
! }
! return FAIL;
! }
!
! command result_t BulkTxRx.BulkTransmit(uint8_t *TxBuffer, uint16_t NumBytes){
!
! }
! command result_t SingleTxRx.startReceive(){
! uint32_t SSCR0, SSCR1;
! bool RxInProgress, TxInProgress;
!
! atomic{
! RxInProgress = gRxInProgress;
! TxInProgress = gTxInProgress;
! }
! if(!RxInProgress){
! if(!TxInProgress){
! //if we're neither transmitting nor receiving, setup the port how we want it be setup
!
! TOSH_SET_YELLOW_LED_PIN();
! gNumRxFifoOverruns=0;
! SSCR0 = createSSCR0() | SSCR0_SSE;
!
! //create SSCR1 and enable the RX fifo interrupt only!!
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1 | SSCR1_RIE);
! atomic gRxInProgress = TRUE;
! call SSPInterrupt.enable();
! //go
! CKEN |= (CKEN23_SSP1);
! call HPLSSP.setSSCR0(SSCR0);
! if(gMasterSFRM == TRUE){
! while((call HPLSSP.getSSSR()) & SSSR_CSS); //wait for the clock synchonization
! }
! return SUCCESS;
! }
! else{//tx is in progress but RX is not..just turn on the RX interrupt
! SSCR1= createSSCR1();
! call HPLSSP.setSSCR1(SSCR1 | SSCR1_RIE);
! atomic gRxInProgress = TRUE;
! return SUCCESS;
! }
! }
! else{
! //transaction is in progress...return FAIL...(equivalent to the port being already opened)
! return FAIL;
! }
!
! }
! command result_t SingleTxRx.stopReceive(){
! uint32_t SSCR1, SSCR0;
! atomic gRxInProgress = FALSE;
! if(!gTxInProgress){
! //if we're neither transmitting nor receiving, kill everything
! //stop the port
! SSCR0 = call HPLSSP.getSSCR0();
! SSCR0 &= ~SSCR0_SSE;
! call HPLSSP.setSSCR0(SSCR0);
!
! //create SSCR1 and enable the RX fifo interrupt only!!
! SSCR1= call HPLSSP.getSSCR1();
! SSCR1 &= ~SSCR1_RIE;
! call HPLSSP.setSSCR1(SSCR1);
! call SSPInterrupt.disable();
! }
! else{
! //NOTE: SSP does not quite work in the way that we're currently representing it. Need to decide how to
! //properly deal with the fact that Tx and Rx are typically coupled
!
! //we're still transmitting....only kill the receive interrupt
! SSCR1= call HPLSSP.getSSCR1();
! SSCR1 &= ~SSCR1_RIE;
! call HPLSSP.setSSCR1(SSCR1);
! }
! return SUCCESS;
! }
!
! command result_t SingleTxRx.transmit(uint32_t data){
- }
! task void signalSingleTxRxTransmitDone(){
! //signal in a task so that we can get out of interrupt context
! //signal SingleTxRx.transmitDone();
! //for now, hack in a large number of samples so that we can get data out....pos
! }
!
! async event void SSPInterrupt.fired(){
! uint32_t temp;
! //get the status register
! temp = call HPLSSP.getSSSR();
!
! if(temp & SSSR_BCE){
! //bit count interrupt
! call HPLSSP.setSSSR(SSSR_BCE);
! }
!
! if(temp & SSSR_TUR){
! //transmit underrun
! call HPLSSP.setSSSR(SSSR_TUR);
! }
!
! if(temp & SSSR_EOC){
! //end of DMA Chain interrupt
! call HPLSSP.setSSSR(SSSR_EOC);
! }
!
! if(temp & SSSR_TINT){
! //Rx timeout interrupt
! call HPLSSP.setSSSR(SSSR_TINT);
! }
!
! if(temp & SSSR_PINT){
! //peripheral trailing byte interrupt
! call HPLSSP.setSSSR(SSSR_PINT);
! }
!
! if(temp & SSSR_ROR){
! //Rx FIFO overrrun
! TOSH_CLR_YELLOW_LED_PIN();
! TOSH_SET_GREEN_LED_PIN();
! TOSH_SET_RED_LED_PIN();
! //while(1);
! gNumRxFifoOverruns++;
! //gRxBufferPos=0;
! call HPLSSP.setSSSR(SSSR_ROR);
! }
!
! if(temp & SSSR_RFS){
! //atomic
! //uint16_t data;
! {
! while(SSSR_1 & SSSR_RNE){
! //while fifo not empty
! //uint32_t data = call HPLSSP.getSSDR();
! //data = SSDR_1;
! //*gRxBuffer++ =(uint16_t)~data;
! *gRxBuffer++ = SSDR_1;
! gRxBufferPos++;
! //gRxBuffer[gRxBufferPos++] = (call HPLSSP.getSSDR());
! if(gRxBufferPos == gRxNumBytes){
! //got all the data that we want....turn things off for now
! call SingleTxRx.stopReceive();
! //post signalBulkTxRxReceiveDone();
! }
! }
! } //have data to read...let's read it out!!
! }
!
! if(temp & SSSR_TFS){
! post signalSingleTxRxTransmitDone();
! //stupid thing wants data to send out...i.e the last set of sends are done!
! }
! }
! event result_t RxDMAChannel.requestChannelDone(){
! //so we've successfully been cleared to start doing something with our port...go!!
! uint32_t SSCR0;
- call RxDMAChannel.run(TRUE);
- SSCR0 = createSSCR0() | SSCR0_SSE;
- call HPLSSP.setSSCR0(SSCR0);
-
- return SUCCESS;
- }
-
- async event void RxDMAChannel.Interrupt(){
- uint32_t SSCR0;
-
- //invlidate the DCache so that we can bring our data in
- invalidateDCache((uint8_t *)gRxBuffer, gRxNumBytes);
- gRxBuffer = (uint16_t *)signal BulkTxRx.BulkReceiveDone((uint8_t *)gRxBuffer,
- gRxNumBytes);
- if(gRxBuffer){
- //we want to do another read of gRxNumBytes)
- //we should still have our DMA channel, so just all set size and run!
- call RxDMAChannel.setTargetAddr((uint32_t)gRxBuffer);
- call RxDMAChannel.setTransferLength(gRxNumBytes);
- call RxDMAChannel.run(TRUE);
- }
- else{
- if(gNumRxFifoOverruns>0){
- trace(DBG_USR1,"Num ROR's = %d\r\n",gNumRxFifoOverruns);
- }
-
- atomic gRxInProgress = FALSE;
- SSCR0 = call HPLSSP.getSSCR0();
- SSCR0 &= ~SSCR0_SSE;
- call HPLSSP.setSSCR0(SSCR0);
- }
- return;
- }
-
- event result_t TxDMAChannel.requestChannelDone(){
- return SUCCESS;
- }
-
- async event void TxDMAChannel.Interrupt(){
- return;
- }
- }
--- 18,56 ----
implementation {
! #define _SSCR0 SSCR0_1
! #define _SSCR1 SSCR1_1
! #define _SSPSP SSPSP_1
! #define _SSTO SSTO_1
! #define _SSITR SSITR_1
! #define _SSSR SSSR_1
! #define _SSDR SSDR_1
! #define _SSACD SSACD_1
! #define MYCKEN (CKEN_CKEN23)
! #define MYFIFOADDR (0x41000010)
! #define MYSSP_RXD SSP1_RXD
! #define MYSSP_RXD_ALTFN SSP1_RXD_ALTFN
! #define MYSSP_TXD SSP1_TXD
! #define MYSSP_TXD_ALTFN SSP1_TXD_ALTFN
! #define MYSSP_SCLK SSP1_SCLK
! #define MYSSP_SCLK_ALTFN SSP1_SCLK_ALTFN
! #define MYSSP_SFRM SSP1_SFRM
! #define MYSSP_SFRM_ALTFN SSP1_SFRM_ALTFN
! #define DMAID_MYSSP_TX DMAID_SSP1_TX
! #define DMAID_MYSSP_RX DMAID_SSP1_RX
! //change this value to change the default priority requst for the DMA channel
! #define DEFAULTDMARXPRIORITY (DMA_Priority1|DMA_Priority2|DMA_Priority3|DMA_Priority4)
! #define DEFAULTDMATXPRIORITY (DMA_Priority1|DMA_Priority2|DMA_Priority3|DMA_Priority4)
! #include "SSP.c"
!
! }
!
Index: SettingsC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SettingsC.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** SettingsC.nc 8 Dec 2005 23:13:06 -0000 1.2
--- SettingsC.nc 10 Oct 2006 01:57:44 -0000 1.3
***************
*** 44,59 ****
provides{
interface StdControl;
}
}
implementation{
! components SettingsM, BluSHC, UIDC, CC2420ControlM, SleepC;
StdControl = SettingsM;
SettingsM.UID->UIDC;
#ifdef RADIO_DEBUG
SettingsM.CC2420Control->CC2420ControlM;
#endif
SettingsM.Sleep->SleepC;
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.NodeID;
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.TestTaskQueue;
#ifdef RADIO_DEBUG
--- 44,67 ----
provides{
interface StdControl;
+ command uint8_t ReadResetCause();
}
}
implementation{
! components SettingsM, BluSHC, UIDC, CC2420ControlM, SleepC, TimerC, ResetC;
StdControl = SettingsM;
+ ReadResetCause = SettingsM.ReadResetCause;
+
SettingsM.UID->UIDC;
+ SettingsM.Reset->ResetC;
#ifdef RADIO_DEBUG
SettingsM.CC2420Control->CC2420ControlM;
#endif
+ #ifdef TASK_QUEUE_DEBUG
+ SettingsM.Timer->TimerC.Timer[unique("Timer")];
+ #endif
SettingsM.Sleep->SleepC;
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.NodeID;
+ BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.ResetNode;
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.TestTaskQueue;
#ifdef RADIO_DEBUG
***************
*** 62,64 ****
--- 70,73 ----
#endif
BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.GoToSleep;
+ BluSHC.BluSH_AppI[unique("BluSH")] -> SettingsM.GetResetCause;
}
Index: SettingsM.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/SettingsM.nc,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** SettingsM.nc 8 Dec 2005 23:13:06 -0000 1.2
--- SettingsM.nc 10 Oct 2006 01:57:44 -0000 1.3
***************
*** 57,68 ****
--- 57,75 ----
interface BluSH_AppI as GetRadioChannel;
#endif
+ interface BluSH_AppI as ResetNode;
interface BluSH_AppI as GoToSleep;
+ interface BluSH_AppI as GetResetCause;
+ command uint8_t ReadResetCause();
}
uses {
interface UID;
+ interface Reset;
#ifdef RADIO_DEBUG
interface CC2420Control;
#endif
interface Sleep;
+ #ifdef TASK_QUEUE_DEBUG
+ interface Timer;
+ #endif
}
}
***************
*** 70,73 ****
--- 77,82 ----
implementation {
+ uint32_t ResetCause;
+
command result_t StdControl.init(){
return SUCCESS;
***************
*** 80,87 ****
--- 89,108 ----
TOS_LOCAL_ADDRESS = (uint16_t) (call UID.getUID() & 0xff);
#endif
+
+ #ifdef TASK_QUEUE_DEBUG
+ call Timer.start(TIMER_REPEAT, 10000);
+ #endif
+
+ // Figure out the cause of reset, store the info and clear the register
+ ResetCause = RCSR;
+ RCSR = 0xf;
+
return SUCCESS;
}
command result_t StdControl.stop(){
+ #ifdef TASK_QUEUE_DEBUG
+ call Timer.stop();
+ #endif
return SUCCESS;
}
***************
*** 91,94 ****
--- 112,119 ----
}
+ task void doReset() {
+ call Reset.reset();
+ }
+
command BluSH_result_t NodeID.getName(char *buff, uint8_t len) {
const char name[] = "NodeID";
***************
*** 185,188 ****
--- 210,260 ----
return BLUSH_SUCCESS_DONE;
}
+
+ command BluSH_result_t ResetNode.getName(char *buff, uint8_t len) {
+ const char name[] = "ResetNode";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t ResetNode.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ trace(DBG_USR1,"Resetting\r\n");
+ post doReset();
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t GetResetCause.getName(char *buff, uint8_t len) {
+ const char name[] = "GetResetCause";
+ strcpy(buff, name);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+ command BluSH_result_t GetResetCause.callApp(char *cmdBuff, uint8_t cmdLen,
+ char *resBuff, uint8_t resLen) {
+ uint8_t gpio_rst, sleep_rst, wdt_rst, hw_rst;
+ gpio_rst = (ResetCause & RCSR_GPR) == RCSR_GPR;
+ sleep_rst = (ResetCause & RCSR_SMR) == RCSR_SMR;
+ wdt_rst = (ResetCause & RCSR_WDR) == RCSR_WDR;
+ hw_rst = (ResetCause & RCSR_HWR) == RCSR_HWR;
+ trace(DBG_USR1, "GPIO %d, Sleep %d, WDT %d, Power On %d\r\n",
+ gpio_rst, sleep_rst, wdt_rst, hw_rst);
+ return BLUSH_SUCCESS_DONE;
+ }
+
+
+ #ifdef TASK_QUEUE_DEBUG
+ event result_t Timer.fired() {
+ uint8_t mo;
+ uint32_t fp;
+ TOSH_get_debug_counters(&mo, &fp);
+ trace(DBG_USR1, "Task Queue : Max Occ = %d, Failed Post = %d\r\n", mo, fp);
+ TOSH_reset_debug_counters();
+ return SUCCESS;
+ }
+ #endif
+ command uint8_t ReadResetCause() {
+ return ResetCause;
+ }
+
}
Index: TimerJiffyAsyncC.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/TimerJiffyAsyncC.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** TimerJiffyAsyncC.nc 13 Nov 2004 01:11:44 -0000 1.1
--- TimerJiffyAsyncC.nc 10 Oct 2006 01:57:44 -0000 1.2
***************
*** 14,18 ****
TimerJiffyAsync = TimerJiffyAsyncM;
! TimerJiffyAsyncM.OSTIrq -> PXA27XInterruptM.PXA27XIrq[PPID_OST_4_11];
--- 14,18 ----
TimerJiffyAsync = TimerJiffyAsyncM;
! TimerJiffyAsyncM.OSTIrq -> PXA27XInterruptM.PXA27XIrq[IID_OST_4_11];
Index: hardware.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/hardware.h,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** hardware.h 28 Aug 2005 22:31:46 -0000 1.8
--- hardware.h 10 Oct 2006 01:57:44 -0000 1.9
***************
*** 157,160 ****
--- 157,169 ----
#define SSP3_SCLK_ALTFN (3)
+ #define SSP2_RXD (11)
+ #define SSP2_RXD_ALTFN (2 )
+ #define SSP2_TXD (38)
+ #define SSP2_TXD_ALTFN (2 )
+ #define SSP2_SCLK (36)
+ #define SSP2_SCLK_ALTFN (2 )
+ #define SSP2_SFRM (37)
+ #define SSP2_SFRM_ALTFN (2 )
+
#define SSP1_RXD (26)
#define SSP1_RXD_ALTFN (1 )
Index: pmic.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/beta/platform/imote2/pmic.h,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** pmic.h 18 Oct 2005 21:11:20 -0000 1.4
--- pmic.h 10 Oct 2006 01:57:44 -0000 1.5
***************
*** 74,86 ****
#define PMIC_SLAVE_ADDR 0x49
- // Register BUCK2 with DVC1
- #define PMIC_BUCK2_REG1 0x15
- // Register BUCK2 with DVC2
- #define PMIC_BUCK2_REG2 0x16
- // LDO on/off control in App Reg space
- #define PMIC_A_REG_CONTROL_1 0x17
- #define PMIC_A_REG_CONTROL_2 0x18
#define PMIC_EVENTS (0x01) // 3 byte array
--- 74,79 ----
***************
*** 93,98 ****
#define PMIC_IRQ_MASK_C (0x07)
#define PMIC_SYS_CONTROL_A (0x08)
! #define PMIC_SYS_CONTROL_C (0x80)
#define PMIC_CHARGE_CONTROL (0x28)
#define PMIC_CC_CHARGE_ENABLE (1<<7)
--- 86,103 ----
#define PMIC_IRQ_MASK_C (0x07)
#define PMIC_SYS_CONTROL_A (0x08)
! #define PMIC_LDO10_LDO11 (0x10)
! #define PMIC_LDO18_LDO19 (0x13)
+ // Register BUCK2 with DVC1
+ #define PMIC_BUCK2_REG1 (0x15)
+ // Register BUCK2 with DVC2
+ #define PMIC_BUCK2_REG2 (0x16)
+ // LDO on/off control in App Reg space
+ #define PMIC_A_REG_CONTROL_1 (0x17)
+ #define PMIC_A_REG_CONTROL_2 (0x18)
+
+ #define PMIC_USBPUMP (0x19)
+ #define PMIC_STARTUP_CONTROL (0x1B)
+ #define PMIC_LED1_CONTROL (0x20)
#define PMIC_CHARGE_CONTROL (0x28)
#define PMIC_CC_CHARGE_ENABLE (1<<7)
***************
*** 107,112 ****
#define PMIC_AMC_LDO_INT_Enable (1<<4)
#define PMIC_MAN_RES (0x40)
! #define PMIC_LED1_CONTROL (0x20)
// LDO on/off control in Baseband Reg space
--- 112,131 ----
#define PMIC_AMC_LDO_INT_Enable (1<<4)
+ #define PMIC_ADC_AUTO_CONTROL (0x31)
+
#define PMIC_MAN_RES (0x40)
! #define PMIC_VBAT_RES (0x41)
! #define PMIC_VBATMIN_RES (0x42)
! #define PMIC_VBATMINTXON_RES (0x43)
! #define PMIC_ICHMAX_RES (0x44)
! #define PMIC_ICHMIN_RES (0x45)
! #define PMIC_ICHAVERAGE_RES (0x46)
! #define PMIC_VCHMAX_RES (0x47)
! #define PMIC_VCHMIN_RES (0x48)
! #define PMIC_TBAT_RES (0x49)
! #define PMIC_ADC_IN4_RES (0x4A)
! #define PMIC_ADC_IN5_RES (0x4B)
! #define PMIC_SYS_CONTROL_C (0x80)
!
// LDO on/off control in Baseband Reg space
***************
*** 159,162 ****
--- 178,202 ----
#define EVENTS_C_OFFSET 2
+ //LDO Trim values
+ #define LDO_TRIM_1P8 (0)
+ #define LDO_TRIM_1P9 (1)
+ #define LDO_TRIM_2P0 (2)
+ #define LDO_TRIM_2P1 (3)
+ #define LDO_TRIM_2P2 (4)
+ #define LDO_TRIM_2P3 (5)
+ #define LDO_TRIM_2P4 (6)
+ #define LDO_TRIM_2P5 (7)
+ #define LDO_TRIM_2P6 (8)
+ #define LDO_TRIM_2P7 (9)
+ #define LDO_TRIM_2P8 (10)
+ #define LDO_TRIM_2P9 (11)
+ #define LDO_TRIM_3P0 (12)
+ #define LDO_TRIM_3P1 (13)
+ #define LDO_TRIM_3P2 (14)
+
+ #define PMIC_SET_LDOLOW_TRIM(original, x) (((original) & ~0xF) | (x & 0xF))
+ #define PMIC_SET_LDOHIGH_TRIM(original, x) (((original) & ~0xF0) | ((x & 0xF)<<4))
+
+
// BUCK2 Reg 1
#define B2R1_TRIM_MASK 0x1f
***************
*** 168,176 ****
--- 208,242 ----
#define B2R1_TRIM_P975_V 0x5
#define B2R1_TRIM_1_V 0x6
+ #define B2R1_TRIM_1_025_V 0x7
+ #define B2R1_TRIM_1_05_V 0x8
+ #define B2R1_TRIM_1_075_V 0x9
+ #define B2R1_TRIM_1_1_V 0xA
#define B2R1_TRIM_1_125_V 0xB
+ #define B2R1_TRIM_1_15_V 0xC
+ #define B2R1_TRIM_1_175_V 0xD
+ #define B2R1_TRIM_1_2_V 0xE
+ #define B2R1_TRIM_1_225_V 0xF
#define B2R1_TRIM_1_25_V 0x10
+ #define B2R1_TRIM_1_275_V 0x11
+ #define B2R1_TRIM_1_3_V 0x12
+ #define B2R1_TRIM_1_325_V 0x13
+ #define B2R1_TRIM_1_35_V 0x14
+ #define B2R1_TRIM_1_375_V 0x15
+ #define B2R1_TRIM_1_4_V 0x16
+ #define B2R1_TRIM_1_425_V 0x17
+ #define B2R1_TRIM_1_45_V 0x18
+ #define B2R1_TRIM_1_475_V 0x19
+ #define B2R1_TRIM_1_5_V 0x1A
#define B2R1_SLEEP 0x40
#define B2R1_GO 0x80
+ // USBPUMP
+ #define USBPUMP_USBVE 0x1
+
+ //STARTUP CONTROL
+ #define STARTUPCONTROL_LDO10START 0x1
+ #define STARTUPCONTROL_LDO11START 0x2
+
+
// Reg Control 1 for App processor reg space: Enable/Disable LDOs
#define ARC1_BUCK2_EN 0x1 // on
- Previous message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/imote2
BTUARTC.nc, NONE, 1.1 BTUARTM.nc, NONE, 1.1 BufferedBTUARTC.nc,
NONE, 1.1 BufferedBTUARTM.nc, NONE, 1.1 BufferedFFUARTC.nc,
NONE, 1.1 BufferedFFUARTM.nc, NONE, 1.1 BufferedSTUARTC.nc,
NONE, 1.1 BufferedSTUARTM.nc, NONE, 1.1 BufferedUART.c, NONE,
1.1 BulkTxRx.h, NONE, 1.1 FFUARTC.nc, NONE, 1.1 FFUARTM.nc,
NONE, 1.1 Reset.h, NONE, 1.1 SSP.c, NONE, 1.1 SSP2C.nc, NONE,
1.1 SSP2M.nc, NONE, 1.1 STUARTC.nc, NONE, 1.1 STUARTM.nc, NONE,
1.1 SendData.nc, NONE, 1.1 SendDataAlloc.nc, NONE, 1.1 UART.c,
NONE, 1.1 sched.c, NONE, 1.1
- Next message: [Tinyos-beta-commits] CVS: tinyos-1.x/beta/platform/pxa27x
FileList.h, NONE, 1.1 FileStorageUtil.nc, NONE,
1.1 FormatStorageC.nc, NONE, 1.1 FormatStorageM.nc, NONE,
1.1 HALPXA27X.nc, NONE, 1.1 HALPXA27XC.nc, NONE,
1.1 HALPXA27XM.nc, NONE, 1.1 I2CTempC.nc, NONE,
1.1 I2CTempM.nc, NONE, 1.1 PXA27XOneHzClock.nc, NONE,
1.1 PXA27XPowerManagement.nc, NONE,
1.1 PXA27XPowerManagementM.nc, NONE, 1.1 PXA27XRTCC.nc, NONE,
1.1 PXA27XRTCM.nc, NONE, 1.1 PXA27XSysTimeM.nc, NONE,
1.1 PXA27XWallClockM.nc, NONE, 1.1 PXA27xPowerManagement.h,
NONE, 1.1 PXAFlash.h, NONE, 1.1 SectorStorage.nc, NONE,
1.1 StorageManager.nc, NONE, 1.1 StorageManagerC.nc, NONE,
1.1 StorageManagerM.nc, NONE, 1.1 Storage_chip.h, NONE,
1.1 SysTime64.nc, NONE, 1.1 SysTimeC.nc, NONE, 1.1 TimerM.nc,
NONE, 1.1 WallClock.nc, NONE, 1.1 pxa27x_registers_def.h, NONE, 1.1
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