[Tinyos-contrib-commits] CVS: tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base HPLUSARTControl.nc, NONE, 1.1 DMA_M.nc, 1.1, 1.2 HPLUSART0M.nc, 1.1, 1.2 HPLUSART1M.nc, 1.1, 1.2

steve ayer ayer1 at users.sourceforge.net
Thu Aug 3 12:16:52 PDT 2006 

Update of /cvsroot/tinyos/tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv16969/tos/platform/msp430_crl_base

Modified Files:
	DMA_M.nc HPLUSART0M.nc HPLUSART1M.nc 
Added Files:
	HPLUSARTControl.nc 
Log Message:

added shimmer platform, including programming mods to bsl.py
interface and lib updates to DMA->ADC machinery, test code
added SD lib module, test code
updates telos_ap.c/Makefile to handle old (pre-2.6.15) and new kernel ip api 
commented out interrupt flag clearing in setmodespi in hplusart[0-1]m.nc, because this breaks some spi comm initializations
added telosb platform to handle interface skew between new (shimmer) and old (telosb) platforms


--- NEW FILE: HPLUSARTControl.nc ---
/*
 * Copyright (c) 2004-2005, Technische Universität Berlin
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without 
 * modification, are permitted provided that the following conditions 
 * are met:
 * - Redistributions of source code must retain the above copyright notice,
 *   this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright 
 *   notice, this list of conditions and the following disclaimer in the 
 *   documentation and/or other materials provided with the distribution.
 * - Neither the name of the Technische Universität Berlin nor the names 
 *   of its contributors may be used to endorse or promote products derived
 *   from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 
 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY 
 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 
 * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 * - Description ----------------------------------------------------------
 * Byte-level interface to control a USART. 
 * <p>The USART can be switched to SPI- or UART-mode. The interface follows
 * the convention of being stateless, thus a higher layer has to maintain
 * state information. I.e. calling <code>tx</done> will transmit a byte of
 * data in the mode (SPI or UART) the USART has been set to before.
 * - Revision -------------------------------------------------------------
 * $Revision: 1.1 $
 * $Date: 2006/08/03 19:16:50 $
 * @author Jan Hauer (hauer at tkn.tu-berlin.de)
 * @author Joe Polastre
 * ========================================================================
 */
 
includes msp430usart;

interface HPLUSARTControl {

  /**
   * Returns an enum value corresponding to the current mode of the USART
   * module.  Allows one to read the module mode, change it, and then
   * reset it back to its original state after use.
   */
  async command msp430_usartmode_t getMode();

  /**
   * Sets the USART mode to one of the options from msp430_usartmode_t
   * defined in MSP430USART.h
   *
   * @return SUCCESS if the mode was changed
   */
  async command void setMode(msp430_usartmode_t mode);

  /**
   * Returns TRUE if the USART has UART TX mode enabled
   */
  async command bool isUARTtx();

  /**
   * Returns TRUE if the USART has UART RX mode enabled
   */
  async command bool isUARTrx();

  /**
   * Returns TRUE if the USART is set to UART mode (both RX and TX)
   */
  async command bool isUART();

 /**
   * Enables both the Rx and the Tx UART modules.
   */
  async command void enableUART();
  
 /**
   * Disables both the Rx and the Tx UART modules.
   */
  async command void disableUART();
 
 /**
   * Enables the UART TX functionality of the USART module.
   */
  async command void enableUARTTx();

 /**
   * Disables the UART TX module.
   */
  async command void disableUARTTx();

 /**
   * Enables the UART RX functionality of the USART module.
   */
  async command void enableUARTRx();

 /**
   * Disables the UART RX module.
   */
  async command void disableUARTRx();
  
 /**
   * Enables the USART when in SPI mode.
   */
  async command void enableSPI();
  
 /**
   * Disables the USART when in SPI mode.
   */
  async command void disableSPI();
  
  /**
   * Enables the I2C module (register flags)
   */
  async command void enableI2C();

  /**
   * Disables the I2C module
   */
  async command void disableI2C();

  /**
   * Returns TRUE if the USART is set to SPI mode
   */
  async command bool isSPI();

 /**
   * Switches USART to SPI mode.
   */
  async command void setModeSPI();

 /**
   * Switches USART to SPI mode as a slave.
   */
  async command void setSlaveModeSPI();
	
 /**
   * Switches USART to UART TX mode (RX pins disabled).
   * Interrupts disabled by default.
   */	
  async command void setModeUART_TX();
	
 /**
   * Switches USART to UART RX mode (TX pins disabled)..
   * Interrupts disabled by default.
   */	
  async command void setModeUART_RX();

 /**
   * Switches USART to UART mode (RX and TX enabled)
   * Interrupts disabled by default.
   */	
  async command void setModeUART();

  /**
   * Returns TRUE if the module is set to I2C mode for MSP430 parts that
   * support hardware I2C.
   */
  async command bool isI2C();

  /**
   * Switches USART to I2C mode for MSP430 parts that support
   * hardware I2C. Interrupts disabled by default.
   */
  async command void setModeI2C();
 
  async command void setClockSource(uint8_t source);

  async command void setClockRate(uint16_t baudrate, uint8_t mctl);

  /* Dis/enabling of UTXIFG / URXIFG */
  async command result_t disableRxIntr();
  async command result_t disableTxIntr();
  async command result_t enableRxIntr();
  async command result_t enableTxIntr();
 
  /**
   * SUCCESS if TX interrupt pending, flag is cleared automatically 
   */
  async command result_t isTxIntrPending();

  /**
   * SUCCESS if RX interrupt pending, flag is cleared automatically 
   */
  async command result_t isRxIntrPending();

  /** 
   * SUCCESS if the TX buffer is empty and all of the bits have been
   * shifted out 
   */
  async command result_t isTxEmpty();

 /**
   * Transmit a byte of data. When the transmission is completed,
   * <code>txDone</done> is generated. Only then a new byte may be
   * transmitted, otherwise the previous byte will be overwritten.
   * The mode of transmission (UART or SPI) depends on the current state
   * of the USART, which must be managed by a higher layer.
   *
   * @return SUCCESS always.
   */
  async command result_t tx(uint8_t data);

  /**
   * Get current value from RX-buffer.
   *
   * @return SUCCESS always.
   */
  async command uint8_t rx();

}


Index: DMA_M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base/DMA_M.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** DMA_M.nc	29 Jul 2005 18:29:28 -0000	1.1
--- DMA_M.nc	3 Aug 2006 19:16:50 -0000	1.2
***************
*** 37,262 ****
   */
  
- /* api hint:  see msp430/include/msp430/dma.h for register flags */
  includes DMA;
  
- /* definition in dma.h
- typedef struct {
-     uint16_t *dma_N_ctl;
-     uint16_t *dma_N_sa;
-     uint16_t *dma_N_da;
-     uint16_t *dma_N_sz;
- } DMA_Regs;
- */
- 
  module DMA_M {
!     provides interface DMA[uint8_t id];
  }
  implementation {
!     MSP430REG_NORACE(DMACTL0);
!     MSP430REG_NORACE(DMACTL1);
! 
!     MSP430REG_NORACE(DMA0CTL);
!     MSP430REG_NORACE(DMA1CTL);
!     MSP430REG_NORACE(DMA2CTL);
  
!     MSP430REG_NORACE(DMA0SA);
!     MSP430REG_NORACE(DMA1SA);
!     MSP430REG_NORACE(DMA2SA);
  
!     MSP430REG_NORACE(DMA0DA);
!     MSP430REG_NORACE(DMA1DA);
!     MSP430REG_NORACE(DMA2DA);
  
!     MSP430REG_NORACE(DMA0SZ);
!     MSP430REG_NORACE(DMA1SZ);
!     MSP430REG_NORACE(DMA2SZ);
  
  
!     DMA_Regs dma_regs[3] = {
! 	{ (uint16_t *)DMA0CTL_, (uint16_t *)DMA0SA_, (uint16_t *)DMA0DA_, (uint16_t *)DMA0SZ_ },
! 	{ (uint16_t *)DMA1CTL_, (uint16_t *)DMA1SA_, (uint16_t *)DMA1DA_, (uint16_t *)DMA1SZ_ },
! 	{ (uint16_t *)DMA2CTL_, (uint16_t *)DMA2SA_, (uint16_t *)DMA2DA_, (uint16_t *)DMA2SZ_ }
!     };
  
!     command void DMA.ADCinit() {
! 	atomic {
! 	    // set up adc
! 	    ADC12CTL0 = ADC12ON;  
  
! 	    ADC12CTL0 |= REFON;               // internal source for above
! 	    ADC12CTL0 |= SHT0_12 + SHT1_12;   // set 1024 ticks for s&h ( so, 1MHz / 1024 = 1kHz)
! 	    ADC12CTL0 |= MSC;                 // multiple conversions without more triggers
  
! 	    ADC12CTL1 = SHS_0 + SHP + CONSEQ_2;     // s&h from adc12sc bit, repeat single-channel conversion
! 	    ADC12CTL1 |= ADC12SSEL_3;         // clk from smclk
  	
! 	    ADC12MCTL0 |= INCH_1;             // use input channel 1 for all mem regs
! 	    ADC12MCTL0 |= SREF_0;             // Vref = Vref+ and Vr-
! 	}
      }
  	
!     command void DMA.ADCbeginConversion() {
! 	uint16_t c;
! 	atomic{
! 	    ADC12CTL0 |= ENC + ADC12SC;   // start conversion
! 	    c = ADC12MEM0;                // start with a read
! 	}
      }
  
!     command void DMA.ADCstopConversion() {
! 	ADC12CTL0 &= ~(ENC + ADC12SC);
!     }
  
!     // s & hold clock ticks for mem register 8-15, range 4 - 1024
!     command void DMA.ADCsetUpperMemRegClockCycles(uint8_t clk_cycles) {
! 	clk_cycles = clk_cycles >> 3;
! 	ADC12CTL0 |= (clk_cycles << 12);   
!     } 
  
!     // s & hold clock ticks for mem register 0-7, range 4 - 1024
!     command void DMA.ADCsetLowerMemRegClockCycles(uint8_t multiplier) {
! 	clk_cycles = clk_cycles >> 3;
! 	ADC12CTL0 |= (clk_cycles << 8);   
!     }
  
!     /**
!      * each of 16 mem registers selects its own input channel, 8 external, 4 internal
!      * 
!      **/
!     command void DMA.ADCsetMemRegisterInputChannel(uint8_t reg_num, uint8_t ch) {
! 	uint16_t mreg = ADC12MCTL0;
! 	mreg += reg_num;
! 	
! 	mreg |= ch;
!     }
  
!     command void DMA.init[uint8_t id]() {
! 	atomic {
!  	    dma_regs[id].dma_N_sa = ADC12MEM0_;               // src first adc buf register
! 	    dma_regs[id].dma_N_da = inbuf;                  // static ram variable
! 	    dma_regs[id].dma_N_sz = sizeof(inbuf) >> 1;      // in words
  
! 	    DMACTL0 = DMA0TSEL_6;                     // trigger from ADC12IFGx
  
! 	    DMA0CTL = DMADT_4 + DMADSTINCR_3 + DMASRCINCR_0;    // repeat single transfer (no ie reset), increment dest addr, static src addr
! 	    DMA0CTL &= ~DMADSTBYTE;           // src and dest word-size transfers, implicit as zero (why these are unnecessary)
! 	    DMA0CTL &= ~DMASRCBYTE;           
! 	}
!     }
  
!     command void DMA.beginTransfer[uint8_t id]() {
! 	DMA0CTL |= DMAEN + DMAIE;      // enabled and interrupt enabled
      }
  
!     command void DMA.stopTransfer[uint8_t id]() {}
  
!     command void DMA.setSourceAddress[uint8_t id](uint16_t src){
! 	*dma_regs[id].dma_N_sa = src;
!     }
  
!     command void DMA.setDestinationAddress[uint8_t id](uint16_t dest){
! 	*dma_regs[id].dma_N_da = dest;
!     }
      
!     // size is bytes or words, depending upon dmaxctl
!     command void DMA.setBlockSize[uint8_t id](uint16_t size){
! 	*dma_regs[id].dma_N_sz = size;
!     }
  
!     /**
!      * DMAnTSELx, n = channel, x = trigger
!      * DMAnTSEL_0  transfer select 0:  DMA_REQ  (software)
!      * DMAnTSEL_1  transfer select 1:  Timer_A CCRIFG.2 
!      * DMAnTSEL_2  transfer select 2:  Timer_B CCRIFG.2 
!      * DMAnTSEL_3  transfer select 3:  I2C receive 
!      * DMAnTSEL_4  transfer select 4:  I2C transmit 
!      * DMAnTSEL_5  transfer select 5:  DAC12.0IFG 
!      * DMAnTSEL_6  transfer select 6:  ADC12IFGx 
!      * DMAnTSEL_15 transfer select 15: DMAE0 (external)
!      **/
!     command void DMA.setTrigger[uint8_t id](uint16_t trigger){
! 	SET_FLAG(DMACTL0, trigger);
      }
  
!     /**
!      * DMADT_0 transfer mode 0: single
!      * DMADT_1 transfer mode 1: block 
!      * DMADT_2 transfer mode 2: interleaved 
!      * DMADT_3 transfer mode 3: interleaved 
!      * DMADT_4 transfer mode 4: single, repeat 
!      * DMADT_5 transfer mode 5: block, repeat 
!      * DMADT_6 transfer mode 6: interleaved, repeat 
!      * DMADT_7 transfer mode 7: interleaved, repeat 
!      **/
!     command void DMA.setTransferMode[uint8_t id](uint16_t mode){
! 	//clear old mode first
! 	CLR_FLAG(*dma_regs[id].dma_N_ctl, DMADT_7);
  
! 	SET_FLAG(*dma_regs[id].dma_N_ctl, mode);
      }
! 
!     // sets round-robin bit
!     command void DMA.setChannelPriority[uint8_t id](bool roundrobin){
! 	if(roundrobin)
! 	    SET_FLAG(DMACTL1, ROUNDROBIN);
! 	else
! 	    CLR_FLAG(DMACTL1, ROUNDROBIN);
      }
! 
!     command void DMA.setDestinationAddressIncrement[uint8_t id](enum addressIncrement ai){
! 	SET_FLAG(*dma_regs[id].dma_N_ctl, ai << 8);
      }
  
!     command void DMA.setSourceAddressIncrement[uint8_t id](enum addressIncrement ai) {
! 	SET_FLAG(*dma_regs[id].dma_N_ctl, ai << 10);
      }
      
!     // alternative is word
!     command void DMA.setSourceByteSize[uint8_t id](bool byteSize){
! 	if(byteSize)
! 	    SET_FLAG(*dma_regs[id].dma_N_ctl, DMASRCBYTE);
! 	else
! 	    CLR_FLAG(*dma_regs[id].dma_N_ctl, DMASRCBYTE);
      }
  
!     command void DMA.setDestinationByteSize[uint8_t id](bool byteSize) {
! 	if(byteSize)
! 	    SET_FLAG(*dma_regs[id].dma_N_ctl, DMADSTBYTE);
! 	else
! 	    CLR_FLAG(*dma_regs[id].dma_N_ctl, DMADSTBYTE);
      }
  
!     async default event void DMA.transferComplete[uint8_t id](){}
!     
!     TOSH_SIGNAL(DACDMA_VECTOR) {
! 	volatile int v;
! 	switch (id) {
! 	case 0:
! 	    v = DMA0CTL;
! 	    break;
! 	case 1:
! 	    v = DMA1CTL;
! 	    break;
! 	case 2:
! 	    v = DMA2CTL;
! 	    break;
! 	}
  	
! 	if(v & DMAIFG) { 
! 	    v &= ~DMAIFG;
! 	    signal DMA.transferComplete[id]();
! 	}
      }
  
!     async default event void DMA.ADCInterrupt[uint8_t id]() {} ;
!     TOSH_SIGNAL(ADC_VECTOR) {
! 	volatile uint16_t vec = ADC12IV;
  	
! 	if( vec ) { 
! 	    vec = vec >> 1;
  	     
! 	    if( vec >= 3 )
! 		signal DMA.ADCInterrupt[id]();
! 	}
      }
  }
--- 37,336 ----
   */
  
  includes DMA;
  
  module DMA_M {
!   provides interface DMA[uint8_t id];
  }
  implementation {
!   MSP430REG_NORACE(DMACTL0);
!   MSP430REG_NORACE(DMACTL1);
  
!   MSP430REG_NORACE(DMA0CTL);
!   MSP430REG_NORACE(DMA1CTL);
!   MSP430REG_NORACE(DMA2CTL);
  
!   MSP430REG_NORACE(DMA0SA);
!   MSP430REG_NORACE(DMA1SA);
!   MSP430REG_NORACE(DMA2SA);
  
!   MSP430REG_NORACE(DMA0DA);
!   MSP430REG_NORACE(DMA1DA);
!   MSP430REG_NORACE(DMA2DA);
  
+   MSP430REG_NORACE(DMA0SZ);
+   MSP430REG_NORACE(DMA1SZ);
+   MSP430REG_NORACE(DMA2SZ);
  
!   uint8_t ch_id;
!   command void DMA.ADCinit[uint8_t id]() {
!     atomic {
!       ADC12CTL0 = ADC12ON;       // self-explanatory
  
!       ADC12CTL0 |= REFON;               // reference generator on
  
!       ADC12CTL0 |= MSC;                 // multiple conversions without more triggers
  
!       ADC12CTL1 = SHS_0 + SHP + CONSEQ_2;     // s&h from adc12sc bit; sample from sampling timer;  repeat single-channel conversion
!       ADC12CTL1 |= ADC12SSEL_3;         // clk from smclk
  	
!       ADC12MCTL0 |= INCH_0;             // use input channel 1 for all mem regs
!       ADC12MCTL0 |= SREF_0;             // Vref = Vref+ and Vr-
      }
+   }
  	
!   command void DMA.ADCbeginConversion[uint8_t id]() {
!     uint16_t c;
!     atomic{
!       ADC12CTL0 |= ENC + ADC12SC;   // start conversion
!       c = ADC12MEM0;                // start with a read
!       c = ADC12MEM1;                // start with a read
!       c = ADC12MEM2;                // start with a read
      }
+   }
  
!   command void DMA.ADCstopConversion[uint8_t id]() {
!     atomic ADC12CTL0 &= ~(ENC + ADC12SC);
!   }
!   /**
!    * each of 16 mem registers selects its own input channel, 8 external, 4 internal
!    * 
!    **/
!   command void DMA.ADCsetMemRegisterInputChannel[uint8_t id](uint8_t reg_num, uint8_t ch) {
!     uint16_t mreg = ADC12MCTL0;
!     mreg += reg_num;
! 	
!     mreg |= ch;
!   }
  
!   command void DMA.init[uint8_t id]() {
!     uint16_t inbuf[256];
  
!     switch (id) {
!     case 0:
!       atomic {
! 	DMA0SA = ADC12MEM0_;               // src first adc buf register
  
! 	DMA0SZ = sizeof(inbuf) >> 1;       // oddly, setting this to 1 breaks code;  this is nominal word block
! 	// default is word transfer, set in DMA0CTL with DMASRCBYTE and DMADSTBYTE == 0
  
! 	DMACTL0 = DMA0TSEL_3 << 1;         // trigger from ADC12IFGx
  
! 	// repeat single transfer (no ie reset), increment dest addr, static src addr
! 	DMA0CTL = DMADT_4 + DMADSTINCR_3 + DMASRCINCR_0;    
!       }
!       break;
!     case 1:
!       atomic{
! 	DMA1SA = ADC12MEM1_;               // src next adc buf register
! 	//	  DMA1DA = inbuf1;           // set dest thus in app.
! 	DMA1SZ = sizeof(inbuf) >> 1;       // see dma0sz
  
! 	DMACTL0 |= DMA1TSEL_3 << 1;                     // trigger from ADC12IFGx
! 	DMA1CTL = DMADT_4 + DMADSTINCR_3 + DMASRCINCR_0;    
!       }
!       break;
!     case 2:
!       atomic{
! 	DMA2SA = ADC12MEM2_;               // src next adc buf register
! 	//   DMA2DA = inbuf2;                  // set dest thus in application
! 	DMA2SZ = sizeof(inbuf) >> 1;                        // see dma0sz
  
! 	DMACTL0 |= DMA2TSEL_3 << 1;
! 	DMA2CTL = DMADT_4 + DMADSTINCR_3 + DMASRCINCR_0;    
!       }
!       break;
      }
+   }
  
!   command void DMA.beginTransfer[uint8_t id]() {
!     if(id == 0)
!       SET_FLAG(DMA0CTL, DMAEN + DMAIE);      // enabled and interrupt enabled
!     else if(id == 1)
!       SET_FLAG(DMA1CTL, DMAEN + DMAIE);      // enabled and interrupt enabled
!     else if(id == 2)
!       SET_FLAG(DMA2CTL, DMAEN + DMAIE);      // enabled and interrupt enabled
  
!   }
  
!   // this one requires some interrupt manipulation if in progress; use after transfer completes
!   command void DMA.stopTransfer[uint8_t id]() {
!     if(id == 0)
!       CLR_FLAG(DMA0CTL, DMAEN + DMAIE);      // enable and interrupt enable
!     else if(id == 1)
!       CLR_FLAG(DMA1CTL, DMAEN + DMAIE);      // enable and interrupt enable
!     else if(id == 2)
!       CLR_FLAG(DMA2CTL, DMAEN + DMAIE);      // enable and interrupt enable
!   }
! 
!   command void DMA.setSourceAddress[uint8_t id](uint16_t src){
!     if(id == 0)
!       DMA0SA = src;
!     else if(id == 1)
!       DMA1SA = src;
!     else if(id == 2)
!       DMA2SA = src;
!   }
! 
!   command void DMA.setDestinationAddress[uint8_t id](uint16_t dest){
!     if(id == 0)
!       DMA0DA = dest;
!     else if(id == 1)
!       DMA1DA = dest;
!     else if(id == 2)
!       DMA2DA = dest;
!   }
      
!   // size is number of bytes or words, depending upon dmaxctl; 
!   command void DMA.setBlockSize[uint8_t id](uint16_t size){
!     if(id == 0)
!       DMA0SZ = size;
!     else if(id == 1)
!       DMA1SZ = size;
!     else if(id == 2)
!       DMA2SZ = size;
!   }
  
!   /**
!    * DMADT_0 transfer mode 0: single
!    * DMADT_1 transfer mode 1: block 
!    * DMADT_2 transfer mode 2: interleaved 
!    * DMADT_3 transfer mode 3: interleaved 
!    * DMADT_4 transfer mode 4: single, repeat 
!    * DMADT_5 transfer mode 5: block, repeat 
!    * DMADT_6 transfer mode 6: interleaved, repeat 
!    * DMADT_7 transfer mode 7: interleaved, repeat 
!    **/
!   command void DMA.setTransferMode[uint8_t id](uint16_t mode){
!     if(id == 0){
!       CLR_FLAG(DMA0CTL, DMADT_7);
!       SET_FLAG(DMA0CTL, mode);
!     }
!     else if(id == 1){
!       CLR_FLAG(DMA1CTL, DMADT_7);
!       SET_FLAG(DMA1CTL, mode);
      }
+     else if(id == 2){
+       CLR_FLAG(DMA2CTL, DMADT_7);
+       SET_FLAG(DMA2CTL, mode);
+     }
+   }
  
!   // sets round-robin bit
!   command void DMA.setChannelPriority[uint8_t id](bool roundrobin){
!     if(roundrobin)
!       SET_FLAG(DMACTL1, ROUNDROBIN);
!     else
!       CLR_FLAG(DMACTL1, ROUNDROBIN);
!   }
  
!   command void DMA.setDestinationAddressIncrement[uint8_t id](enum addressIncrement ai){
!     if(id == 0){
!       SET_FLAG(DMA0CTL, ai << 8);
      }
!     else if(id == 1){
!       SET_FLAG(DMA1CTL, ai << 8);
      }
!     else if(id == 2){
!       SET_FLAG(DMA2CTL, ai << 8);
      }
+   }
  
!   command void DMA.setSourceAddressIncrement[uint8_t id](enum addressIncrement ai) {
!     if(id == 0){
!       SET_FLAG(DMA0CTL, ai << 10);
!     }
!     else if(id == 1){
!       SET_FLAG(DMA1CTL, ai << 10);
      }
+     else if(id == 2){
+       SET_FLAG(DMA2CTL, ai << 10);
+     }
+   }
      
!   // alternative is word
!   command void DMA.setSourceByteSize[uint8_t id](bool byteSize){
!     if(byteSize){
!       if(id == 0){
! 	SET_FLAG(DMA0CTL, DMASRCBYTE);
!       }
!       else if(id == 1){
! 	SET_FLAG(DMA1CTL, DMASRCBYTE);
!       }
!       else if(id == 2){
! 	SET_FLAG(DMA2CTL, DMASRCBYTE);
!       }
      }
+     else{
+       if(id == 0){
+ 	CLR_FLAG(DMA0CTL, DMASRCBYTE);
+       }
+       else if(id == 1){
+ 	CLR_FLAG(DMA1CTL, DMASRCBYTE);
+       }
+       else if(id == 2){
+ 	CLR_FLAG(DMA2CTL, DMASRCBYTE);
+       }
+     }
+   }
  
!   command void DMA.setDestinationByteSize[uint8_t id](bool byteSize) {
!     if(byteSize){
!       if(id == 0){
! 	SET_FLAG(DMA0CTL, DMADSTBYTE);
!       }
!       else if(id == 1){
! 	SET_FLAG(DMA1CTL, DMADSTBYTE);
!       }
!       else if(id == 2){
! 	SET_FLAG(DMA2CTL, DMADSTBYTE);
!       }
!     }
!     else{
!       if(id == 0){
! 	CLR_FLAG(DMA0CTL, DMADSTBYTE);
!       }
!       else if(id == 1){
! 	CLR_FLAG(DMA1CTL, DMADSTBYTE);
!       }
!       else if(id == 2){
! 	CLR_FLAG(DMA2CTL, DMADSTBYTE);
!       }
      }
+   }
  
!   async default event void DMA.transferComplete[uint8_t id](){}
! 
! 
!   TOSH_SIGNAL(DACDMA_VECTOR) {
!     volatile int v  = DMA0CTL;
  	
!     if(v & DMAIFG) { 
!       DMA0CTL &= ~DMAIFG;
!       signal DMA.transferComplete[0]();
!     }
!     v = DMA1CTL;
!     if(v & DMAIFG) { 
!       DMA1CTL &= ~DMAIFG;
!       signal DMA.transferComplete[1]();
!     }
!     v = DMA2CTL;
!     if(v & DMAIFG) { 
!       DMA2CTL &= ~DMAIFG;
!       signal DMA.transferComplete[2]();
      }
+   }
  
! 
!   async default event void DMA.ADCInterrupt[uint8_t id]() {} ;
!   TOSH_SIGNAL(ADC_VECTOR) {
!     volatile uint16_t vec = ADC12IV;
  	
!     if( vec ) { 
!       vec = vec >> 1;
  	     
!       if( vec >= 3 )
! 	signal DMA.ADCInterrupt[0]();
! 
      }
+   } 
  }

Index: HPLUSART0M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base/HPLUSART0M.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** HPLUSART0M.nc	29 Jul 2005 18:29:28 -0000	1.1
--- HPLUSART0M.nc	3 Aug 2006 19:16:50 -0000	1.2
***************
*** 40,45 ****
  module HPLUSART0M {
    provides interface HPLUSARTControl as USARTControl;
-   provides interface HPLUSARTFeedback as USARTData;
    provides interface HPLI2CInterrupt;
  }
  implementation
--- 40,45 ----
  module HPLUSART0M {
    provides interface HPLUSARTControl as USARTControl;
    provides interface HPLI2CInterrupt;
+   provides interface HPLUSARTFeedback as USARTData;
  }
  implementation
***************
*** 266,271 ****
--- 266,309 ----
        U0CTL &= ~SWRST;  
  
+       //      IFG1 &= ~(UTXIFG0 | URXIFG0);
+       IE1 &= ~(UTXIE0 | URXIE0);  // interrupt disabled    
+     }
+     return;
+   }
+ 
+   async command void USARTControl.setSlaveModeSPI() {
+       
+     call USARTControl.disableUART();
+     call USARTControl.disableI2C();
+ 
+     atomic {
+       TOSH_MAKE_SIMO0_INPUT();
+       TOSH_MAKE_UCLK0_INPUT();
+       TOSH_MAKE_SOMI0_OUTPUT();
+       TOSH_SEL_SIMO0_MODFUNC();
+       TOSH_SEL_SOMI0_MODFUNC();
+       TOSH_SEL_UCLK0_MODFUNC();
+ 
+       IE1 &= ~(UTXIE0 | URXIE0);  // interrupt disable    
+ 
+       U0CTL = SWRST;
+       U0CTL |= CHAR | SYNC ;  // 8-bit char, SPI-mode, USART as slave
+       U0CTL &= ~(0x20); // Clear up I2C mode
+ 
+       U0TCTL = STC ;     // 3-pin
+       U0TCTL |= CKPH;    // half-cycle delayed UCLK
+       U0TCTL &= ~(SSEL_0 | SSEL_1 | SSEL_2 | SSEL_3); // Slave hence external clock
+ 
+ 
+       // U0BR0 and U0BR1 not touched since we receive and clock is external
+       U0MCTL = 0;       // Not relevant to slave mode
+ 
+       ME1 &= ~(UTXE0 | URXE0); //USART UART module disable
+       ME1 |= USPIE0;   // USART SPI module enable
+       U0CTL &= ~SWRST;  
+ 
        IFG1 &= ~(UTXIFG0 | URXIFG0);
        IE1 &= ~(UTXIE0 | URXIE0);  // interrupt disabled    
+       IE1 |= URXIE0; // Generate an interrupt 
      }
      return;

Index: HPLUSART1M.nc
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base/HPLUSART1M.nc,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** HPLUSART1M.nc	29 Jul 2005 18:29:28 -0000	1.1
--- HPLUSART1M.nc	3 Aug 2006 19:16:50 -0000	1.2
***************
*** 203,207 ****
      if (call USARTControl.getMode() == USART_SPI) 
        return;
!       
      call USARTControl.disableUART();
      call USARTControl.disableI2C();
--- 203,207 ----
      if (call USARTControl.getMode() == USART_SPI) 
        return;
! 
      call USARTControl.disableUART();
      call USARTControl.disableI2C();
***************
*** 210,213 ****
--- 210,214 ----
        TOSH_SEL_SIMO1_MODFUNC();
        TOSH_SEL_SOMI1_MODFUNC();
+ 
        TOSH_SEL_UCLK1_MODFUNC();
  
***************
*** 216,220 ****
        U1CTL |= SWRST;  
        U1CTL |= CHAR | SYNC | MM;  // 8-bit char, spi-mode, USART as master
!       U1CTL &= ~(0x20); 
  
        U1TCTL = STC ;     // 3-pin
--- 217,221 ----
        U1CTL |= SWRST;  
        U1CTL |= CHAR | SYNC | MM;  // 8-bit char, spi-mode, USART as master
!       U1CTL &= ~(0x20);           // clears i2c bit
  
        U1TCTL = STC ;     // 3-pin
***************
*** 229,233 ****
          U1TCTL |= SSEL_SMCLK; // use SMCLK, assuming 1MHz
        }
! 
        if (l_br != 0) {
          U1BR0 = l_br & 0x0FF;
--- 230,234 ----
          U1TCTL |= SSEL_SMCLK; // use SMCLK, assuming 1MHz
        }
!       
        if (l_br != 0) {
          U1BR0 = l_br & 0x0FF;
***************
*** 244,253 ****
        U1CTL &= ~SWRST;  
  
        IFG2 &= ~(UTXIFG1 | URXIFG1);
        IE2 &= ~(UTXIE1 | URXIE1);  // interrupt disabled    
      }
      return;
    }
!   
    void setUARTModeCommon() {
      atomic {
--- 245,290 ----
        U1CTL &= ~SWRST;  
  
+       //      IFG2 &= ~(UTXIFG1 | URXIFG1);
+       IE2 &= ~(UTXIE1 | URXIE1);  // interrupt disabled    
+     }
+     return;
+   }
+ 
+   async command void USARTControl.setSlaveModeSPI() {
+       
+     call USARTControl.disableUART();
+     call USARTControl.disableI2C();
+     /* Disable SPI mode as well in case we were in master mode */
+     call USARTControl.disableSPI();
+ 
+     atomic {
+       TOSH_SEL_SIMO1_MODFUNC();
+       TOSH_SEL_SOMI1_MODFUNC();
+       TOSH_SEL_UCLK1_MODFUNC();
+ 
+       IE2 &= ~(UTXIE1 | URXIE1);  // interrupt disable    
+ 
+       U1CTL = SWRST;
+       U1CTL |= CHAR | SYNC ;  // 8-bit char, SPI-mode, USART as slave
+       U1CTL &= ~(0x20); // Clear up I2C mode
+ 
+       U1TCTL = STC ;     // 3-pin
+       U1TCTL |= CKPH;    // half-cycle delayed UCLK
+ 
+       // U0BR0 and U0BR1 not touched since we receive and clock is external
+       U1RCTL = 0;       // Not relevant to slave mode
+       U1MCTL = 0;       // Not relevant to slave mode
+ 
+       ME2 &= ~(UTXE1 | URXE1); //USART UART module disable
+       ME2 |= USPIE1;   // USART SPI module enable
+       U1CTL &= ~SWRST;  
+ 
        IFG2 &= ~(UTXIFG1 | URXIFG1);
        IE2 &= ~(UTXIE1 | URXIE1);  // interrupt disabled    
+       //      IE2 |= URXIE1; // Generate an interrupt 
      }
      return;
    }
! 
    void setUARTModeCommon() {
      atomic {

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