[Tinyos-contrib-commits] CVS: tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base msp430hardware.h, 1.1, 1.2

[steve ayer]

Update of /cvsroot/tinyos/tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base
In directory sc8-pr-cvs10.sourceforge.net:/tmp/cvs-serv18052

Modified Files:
	msp430hardware.h 
Log Message:

updated macro definitions for finding i2c channels; these affect the
definition of norace registers that are used in nesc_atomic_sleep.
(~line 145 and ~line 260).

why?

newer builds of the mspgcc toolchain have replaced the
__msp430_have_usart0_with_i2c macro with __MSP430_HAS_I2C__, so a
toolchain upgrade will break the tinyos build environment.  we'll
accept either one.


Index: msp430hardware.h
===================================================================
RCS file: /cvsroot/tinyos/tinyos-1.x/contrib/handhelds/tos/platform/msp430_crl_base/msp430hardware.h,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** msp430hardware.h	29 Jul 2005 18:29:28 -0000	1.1
--- msp430hardware.h	11 Mar 2008 14:04:28 -0000	1.2
***************
*** 143,147 ****
  
  // I2CBusy flag is not defined by current MSP430-GCC
! #ifdef __msp430_have_usart0_with_i2c
  #ifndef I2CBUSY
  #define I2CBUSY   (0x01 << 5)
--- 143,147 ----
  
  // I2CBusy flag is not defined by current MSP430-GCC
! #if defined (__msp430_have_usart0_with_i2c) || defined (__MSP430_HAS_I2C__)
  #ifndef I2CBUSY
  #define I2CBUSY   (0x01 << 5)
***************
*** 250,266 ****
      __nesc_enable_interrupt();
      return;
!   } else {
      LPMode_bits = LPM3_bits;
      // TimerA, USART0, USART1 check
!     if ( (((TACCTL0 & CCIE) || (TACCTL1 & CCIE) || (TACCTL2 & CCIE))
!          && ((TACTL & TASSEL_3) == TASSEL_2))
!       || ((ME1 & (UTXE0 | URXE0)) && (U0TCTL & SSEL1))
!       || ((ME2 & (UTXE1 | URXE1)) && (U1TCTL & SSEL1)) 
! #ifdef __msp430_have_usart0_with_i2c
!       // registers end in "nr" to prevent nesC race condition detection
!       || ((U0CTLnr & I2CEN) && (I2CTCTLnr & SSEL1) &&
! 	  (I2CDCTLnr & I2CBUSY) && (U0CTLnr & SYNC) && (U0CTLnr & I2C))
  #endif	
!       )
        LPMode_bits = LPM1_bits;
  #ifdef __msp430_have_adc12
--- 250,268 ----
      __nesc_enable_interrupt();
      return;
!   } 
!   else {
      LPMode_bits = LPM3_bits;
      // TimerA, USART0, USART1 check
!     if ( (((TACCTL0 & CCIE) || (TACCTL1 & CCIE) || (TACCTL2 & CCIE)) && ((TACTL & TASSEL_3) == TASSEL_2)) ||
! 	 ((ME1 & (UTXE0 | URXE0)) && (U0TCTL & SSEL1)) ||
! 	 ((ME2 & (UTXE1 | URXE1)) && (U1TCTL & SSEL1))
! 	 // #ifdef __msp430_have_usart0_with_i2c
! #if defined (__msp430_have_usart0_with_i2c) || defined ( __MSP430_HAS_I2C__)
! 	 // registers end in "nr" to prevent nesC race condition detection
! 	 || ((U0CTLnr & I2CEN) && (I2CTCTLnr & SSEL1) &&
! 	     (I2CDCTLnr & I2CBUSY) && (U0CTLnr & SYNC) && 
! 	     (U0CTLnr & I2C))
  #endif	
! 	 )
        LPMode_bits = LPM1_bits;
  #ifdef __msp430_have_adc12
***************
*** 268,276 ****
      if (ADC12CTL1 & ADC12BUSY){
        if (!(ADC12CTL0 & MSC) && ((TACTL & TASSEL_3) == TASSEL_2))
!          LPMode_bits = LPM1_bits; // TimerA for ADC12 
        else
          switch (ADC12CTL1 & ADC12SSEL_3){
!           case ADC12SSEL_2: LPMode_bits = 0; break;
!           case ADC12SSEL_3: LPMode_bits = LPM1_bits; break;
          }
      }
--- 270,278 ----
      if (ADC12CTL1 & ADC12BUSY){
        if (!(ADC12CTL0 & MSC) && ((TACTL & TASSEL_3) == TASSEL_2))
! 	LPMode_bits = LPM1_bits; // TimerA for ADC12 
        else
          switch (ADC12CTL1 & ADC12SSEL_3){
! 	case ADC12SSEL_2: LPMode_bits = 0; break;
! 	case ADC12SSEL_3: LPMode_bits = LPM1_bits; break;
          }
      }