[Tinyos-contrib-commits] CVS: tinyos-1.x/contrib/imote2/tos/sensorboards/AVboard Audio.nc, NONE, 1.1 intel16.h, NONE, 1.1 WM8940.h, NONE, 1.1 WM8940C.nc, NONE, 1.1 WM8940M.nc, NONE, 1.1
Robbie Adler
radler at users.sourceforge.net
Sat Nov 22 16:35:08 PST 2008
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Update of /cvsroot/tinyos/tinyos-1.x/contrib/imote2/tos/sensorboards/AVboard
In directory ddv4jf1.ch3.sourceforge.com:/tmp/cvs-serv8342
Added Files:
Audio.nc intel16.h WM8940.h WM8940C.nc WM8940M.nc
Log Message:
initial revision of Wolfson WM8940 driver files for AVboard
--- NEW FILE: Audio.nc ---
/**
*@author Robbie Adler
**/
interface Audio{
/****************************************
*platform audio interface
****************************************/
/**
*mute playback on the port
*
*@param enable: port is muted if TRUE, disabled if FALSE
*
*@return FAIL if error, SUCCESS otherwise
**/
command result_t mute(bool enable);
event result_t muteDone(result_t success);
/**
*set playback volume
*
*@param volumeInDecibels: signed integer denoting the requested volume in decibels
*
*@return FAIL if error, SUCCESS otherwise
**/
command result_t setVolume(int8_t volumeInDecibels);
event void setVolumeDone(result_t success);
/**
*set sampling rate
*
*@param Fs: Sampling rate of the codec (rounded to the nearest integer). Note that the sampling rate cannot be changed while the interface is being used. Thus, this interface will change the sampling rate for the next call to play/record.
*
*@return FAIL if error, SUCCESS otherwise
**/
command result_t setSamplingRate(uint32_t Fs);
event void setSamplingRateDone(result_t success);
/**
*start the playback of stereo data.
*
*@param buffer: samples to playback. Samples are 16bit stereo samples packed into a 32-bit word. Left samples are in the low 16 bits. Right samples are in the high 16 bits
*@param numSamples: total number of samples to play
*
*@return FAIL if error, SUCCESS otherwise
**/
command result_t audioPlay(uint32_t *buffer, uint32_t numSamples);
event void audioPlayDone(uint32_t *buffer, uint32_t numSamples);
}
--- NEW FILE: intel16.h ---
#ifndef __INTEL16_WAV_H__
#define __INTEL16_WAV_H__
#define pcmdatalen (0x00017ac8)
int32_t pcmdata[] = {0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
[...24210 lines suppressed...]
0x0,
0x0,
0x0,
0x0,
0x1000100,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0};
#endif //__INTEL16_WAV_H__k
--- NEW FILE: WM8940.h ---
#ifndef __WM8940_H__
#define __WM8940_H__
#define SOFTWARERESET (0)
#define POWERMANAGEMENT1 (1)
//writing of POWERMANAGEMENT1
#define POWERMANAGEMENT1_VMID_OP_EN (1<<8)
#define POWERMANAGEMENT1_LVLSHIFT_EN (1<<7)
#define POWERMANAGEMENT1_AUXEN (1<<6)
#define POWERMANAGEMENT1_PLLEN (1<<5)
#define POWERMANAGEMENT1_MICBEN (1<<4)
#define POWERMANAGEMENT1_BIASEN (1<<3)
#define POWERMANAGEMENT1_BUFIOEN (1<<2)
#define POWERMANAGEMENT1_VMIDSEL(_x) ( (_x) & 0x3)
//reading of POWERMANAGEMENT1
#define POWERMANAGEMENT1_DEVICE_REVISION(_x) ( ((_x) & 0x7)
#define POWERMANAGEMENT2 (2)
#define POWERMANAGEMENT3 (3)
#define POWERMANAGEMENT3_MONOEN (1<<7)
#define POWERMANAGEMENT3_SPKNEN (1<<6)
#define POWERMANAGEMENT3_SPKPEN (1<<5)
#define POWERMANAGEMENT3_MONOMIXEN (1<<3)
#define POWERMANAGEMENT3_SPKMIXEN (1<<2)
#define POWERMANAGEMENT3_DACEN (1)
#define AUDIOINTERFACE (4)
#define AUDIOINTERFACE_LOUTR (1<<9)
#define AUDIOINTERFACE_BCP (1<<8)
#define AUDIOINTERFACE_FRAMEP (1<<7)
#define AUDIOINTERFACE_WL(_x) ( ((_x) & 0x3) << 5)
#define AUDIOINTERFACE_FMT(_x) ( ((_x) & 0x3) << 3)
#define AUDIOINTERFACE_DLRSWAP (1<<2)
#define AUDIOINTERFACE_ALRSWAP (1<<1)
#define COMPANDINGCONTROL (5)
#define CLOCKGENCONTROL (6)
#define CLOCKGENCONTROL_CLKSEL (1<<8)
#define CLOCKGENCONTROL_MCLKDIV(_x) ( ((_x) & 0x7) << 5)
#define CLOCKGENCONTROL_BCLKDIV(_x) ( ((_x) & 0x7) << 2)
#define CLOCKGENCONTROL_MS (1)
#define ADDITIONALCONTROL (7)
#define ADDITIONALCONTROL_POB_CTRL (1<<6)
#define ADDITIONALCONTROL_SOFT_START (1<<5)
#define ADDITIONALCONTROL_TOGGLE (1<<4)
#define ADDITIONALCONTROL_SR(_x) ( ((_x) & 0x7) << 1)
#define ADDITIONALCONTROL_SLOWCLKEN (1)
#define GPIOSTUFF (8)
#define CONTROLINTERFACE (9)
#define DACCONTROL (10)
#define DACCONTROL_DACMU (1<<6)
#define DACCONTROL_AMUTE (1<<2)
#define DACCONTROL_DACPOL (1)
#define DACDIGITALVOLUME (11)
#define DACDIGITALVOLUME_DACVOL(_x) ( (_x) & 0x8)
#define ADCCONTROL (14)
#define ADCDIGITALVOLUME (15)
#define NOTCHFILTER1 (16)
#define NOTCHFILTER2 (17)
#define NOTCHFILTER3 (18)
#define NOTCHFILTER4 (19)
#define NOTCHFILTER5 (20)
#define NOTCHFILTER6 (21)
#define NOTCHFILTER7 (22)
#define NOTCHFILTER8 (23)
#define DACLIMITER1 (24)
#define DACLIMITER2 (25)
#define ALCCONTROL1 (32)
#define ALCCONTROL2 (33)
#define ALCCONTROL3 (34)
#define NOISEGATE (35)
#define PLLN (36)
#define PLL1 (37)
#define PLL2 (38)
#define PLL3 (39)
#define ALCCONTROL4 (42)
#define INPUTCTRL (44)
#define INPPGAGAINCTROL (45)
#define OUTPUTCTRL (49)
#define SPKMIXERCONTROL (50)
#define SPKMIXERCONTROL_AUX2SPK (1<<5)
#define SPKMIXERCONTROL_BYP2SPK (1<<1)
#define SPKMIXERCONTROL_DAC2SPK (1)
#define SPKVOLUMECONTROL (54)
#define SPKVOLUMECONTROL_SPKATTN (1<<8)
#define SPKVOLUMECONTROL_SPKZC (1<<7)
#define SPKVOLUMECONTROL_SPKMUTE (1<<6)
#define SPKVOLUMECONTROL_SPKVOL(_x) ( (_x) & 0x3F)
#define MONOMIXERCONTROL (56)
#endif // __WM8940_H__
--- NEW FILE: WM8940C.nc ---
configuration WM8940C{
provides{
interface StdControl;
}
}
implementation{
components WM8940M,
PXA27XI2SC as I2SC,
I2CBusSequenceC;
StdControl = WM8940M.StdControl;
WM8940M.I2S -> I2SC.I2S;
WM8940M.BulkTxRx -> I2SC.BulkTxRx;
WM8940M.I2CBusSequence -> I2CBusSequenceC;
WM8940M.I2CSequenceControl -> I2CBusSequenceC;
}
--- NEW FILE: WM8940M.nc ---
/**
* @author Robbie Adler
**/
module WM8940M{
provides{
interface StdControl;
interface Audio;
}
uses{
interface I2S;
interface BulkTxRx;
interface I2CBusSequence;
interface StdControl as I2CSequenceControl;
}
}
implementation{
#include "WM8940.h"
#include "intel16.h"
#include "math.h"
#define SLAVE_WRITE_ADDR (0x1A)
#ifndef SAMPLINGRATE
#define SAMPLINGRATE (8)
//WM8940_SR configured WM8940's digital filters for the the right sampling rate
#define WM8940_SR (5)
#define PXA_SYSCLK (I2S_SYSCLK_2p053M)
#endif
#define TEST_LEN (2000)
typedef enum
{
I2CState_IDLE,
I2CState_PowerOn,
I2CState_PowerOff
} I2CState_t;
uint8_t gI2CInProgress = FALSE;
uint8_t gPowerOnState = 0;
I2CState_t gI2CState = I2CState_IDLE;
norace uint32_t *gRxBuffer;
norace uint16_t gRxNumBytes, gRxBufferPos;
uint32_t gTxBuffer[TEST_LEN] __attribute__((aligned(32)));
uint32_t gTxNumBytes, gTxBufferPos;
i2c_op_t I2CRegisterSequence[] = {
{I2C_START,0,0},
{I2C_WRITE, SLAVE_WRITE_ADDR<<1, 0},
{I2C_WRITE, 0x3, 0}, //placeholder for register address to write
{I2C_WRITE, 0x3, 0}, //placeholder for high order-byte of data to write
{I2C_END, 0x0, 0}, //after next write, send stop bit
{I2C_WRITE, 0x0, 0}, //placeholder for low-order byte of data to write
};
#define I2CREGISTERSEQUENCELEN (sizeof(I2CRegisterSequence)/sizeof(*I2CRegisterSequence))
task void continuePowerOnSequence();
result_t writeRegister(uint8_t address, uint16_t data){
uint8_t localI2CInProgress;
atomic{
if(gI2CInProgress == TRUE){
localI2CInProgress = FALSE;
}
else{
localI2CInProgress = TRUE;
}
}
if(localI2CInProgress == FALSE){
return FAIL;
}
I2CRegisterSequence[2].param = address;
I2CRegisterSequence[3].param = (uint8_t) ((data >> 8) & 0xFF);
I2CRegisterSequence[5].param = (uint8_t) ((data ) & 0xFF);
return call I2CBusSequence.runI2CBusSequence(I2CRegisterSequence, I2CREGISTERSEQUENCELEN);
}
result_t issuePowerOnSequence(){
if(gI2CState != I2CState_IDLE){
return FAIL;
}
if(gPowerOnState != 0){
return FAIL;
}
gI2CState = I2CState_PowerOn;
return post continuePowerOnSequence();
}
task void issuePowerOnSequenceDone(){
trace(DBG_USR1,"Completed WM8940 PowerOn Sequence\r\n");
call I2S.enableRecord(FALSE);
call I2S.enablePlayback(TRUE);
call I2S.enableI2S(TRUE);
gTxBufferPos = 0;
call BulkTxRx.BulkTransmit((uint8_t *)pcmdata, (pcmdatalen > 8188)? 8188: pcmdatalen);
}
task void continuePowerOnSequence(){
uint8_t address = 0;
uint16_t data = 0;
bool doWrite = TRUE;
/**
* Power on Sequence from datasheet page 64
* 1.) turn on power supplies and wait for supply voltages to settle
* 2.) Reset internal registers with SW reset command
* 3.) enable non-VMID derived bias generator (VMID_OP_EN=1) and level shifters (LVLSHIFT_EN = 1)
* 4.) enable DAC soft mute (DACMU = 1)
* 5.) select clk source to MCLK (CLKSEL = 0) and audio mode (master or slave)
* 6.) enable power on Bias Conrtrol (POB_CTRL = 1) and wait for outputs to settle
* 7.) enable speaker outputs (SPKPEN = 1, and SPKNEN = 1) and wait for outputs to settle
* 8.) set VMIDSEL[1:0] bits for 50kohm reference string impedance
* 9.) wait for VMID supply to settle (choose the value of VMIDSEL bits based on startup time
* VMIDSEL = 10 for the slowest startup time, VMIDSEL = 11 for the fastest startup). Startup
* time is defined by the value of the VMIDSEL bits (the reference impedance) and the external
* decoupling capacitor on VMID.
*10.) enable analogue amplifier bias control (BIASEN = 1) and VMID buffer (BUFIOEN = 1)
*11.) disable power on Bias Control (POB_CTRL = 1) and VMID soft start (SOFT_START = 1)
*12.) Enable DAC (DACEN=1) and speaker Mixer (SPKMIXEN = 1).
*13.) enable output of DAC to speaker mixer (DAC2SPK = 1).
*14.) disable speaker mute (SPKMUTE = 0) and set SPKVOL = -57dB.
*15.) Ramp up SPKVOL using the following values: -27dB, -15dB, -13dB, -11dB, -9dB, -8dB, -7dB
* -6dB, -5dB, -4dB, -3dB, -2dB, -1dB, 0dB.
*16.) Disable DAC soft mute (DACMU = 0)
*
*
**/
switch(gPowerOnState){
case 0:
//Reset internal registers with SW reset command
address = SOFTWARERESET;
data = 0;//norace hack!!!
break;
case 1:
//enable non-VMID derived bias generator (VMID_OP_EN=1) and level shifters (LVLSHIFT_EN = 1)
address = POWERMANAGEMENT1;
data = POWERMANAGEMENT1_VMID_OP_EN | POWERMANAGEMENT1_LVLSHIFT_EN;
break;
case 2:
//enable DAC soft mute (DACMU = 1)
address = DACCONTROL;
data = DACCONTROL_DACMU;
break;
case 3:
//select clk source to MCLK (CLKSEL = 0) and audio mode (master or slave)
address = CLOCKGENCONTROL;
data = CLOCKGENCONTROL_MCLKDIV(0) | CLOCKGENCONTROL_BCLKDIV(0); //MS = 0 and CLKSEL = MCLK
break;
case 4:
//enable power on Bias Conrtrol (POB_CTRL = 1) and VMID soft start (SOFT_START = 1)
address = ADDITIONALCONTROL;
data = ADDITIONALCONTROL_POB_CTRL | ADDITIONALCONTROL_SOFT_START | ADDITIONALCONTROL_SR(WM8940_SR);
break;
case 5:
//enable speaker outputs (SPKPEN = 1, and SPKNEN = 1) and wait for outputs to settle
address = POWERMANAGEMENT3;
data = POWERMANAGEMENT3_SPKPEN | POWERMANAGEMENT3_SPKNEN;
break;
case 6:
//set VMIDSEL[1:0] bits for 50kohm reference string impedance
address = POWERMANAGEMENT1;
data = POWERMANAGEMENT1_VMID_OP_EN | POWERMANAGEMENT1_LVLSHIFT_EN | POWERMANAGEMENT1_VMIDSEL(1);
break;
case 7:
// wait for VMID supply to settle (choose the value of VMIDSEL bits based on startup time
// VMIDSEL = 10 for the slowest startup time, VMIDSEL = 11 for the fastest startup). Startup
// time is defined by the value of the VMIDSEL bits (the reference impedance) and the external
// decoupling capacitor on VMID.
TOSH_uwait(1000);
doWrite = FALSE;
break;
case 8:
// enable analogue amplifier bias control (BIASEN = 1) and VMID buffer (BUFIOEN = 1)
address = POWERMANAGEMENT1;
data = POWERMANAGEMENT1_VMID_OP_EN | POWERMANAGEMENT1_LVLSHIFT_EN | POWERMANAGEMENT1_VMIDSEL(1) | POWERMANAGEMENT1_BIASEN | POWERMANAGEMENT1_BUFIOEN;
break;
case 9:
// disable power on Bias Cont(int16_t)rol (POB_CTRL = 0) and VMID soft start (SOFT_START = 0)
address = ADDITIONALCONTROL;
data = ADDITIONALCONTROL_SR(WM8940_SR);
break;
case 10:
// Enable DAC (DACEN=1) and speaker Mixer (SPKMIXEN = 1).
address = POWERMANAGEMENT3;
data = POWERMANAGEMENT3_SPKPEN | POWERMANAGEMENT3_SPKNEN | POWERMANAGEMENT3_DACEN | POWERMANAGEMENT3_SPKMIXEN;
break;
case 11:
// enable output of DAC to speaker mixer (DAC2SPK = 1).
address = SPKMIXERCONTROL;
data = SPKMIXERCONTROL_DAC2SPK;
break;
case 12:
// disable speaker mute (SPKMUTE = 0) and set SPKVOL = -57dB.
address = SPKVOLUMECONTROL;
data = 0; //mute and spkvol = -57dB
break;
case 13:
// set SPKVOL to -27dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-27) - (-57));
break;
case 14:
// set SPKVOL to -15dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-25) - (-57));
break;
case 15:
// set SPKVOL to -13dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-13) - (-57));
break;
case 16:
// set SPKVOL to -11dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-11) - (-57));
break;
case 17:
// set SPKVOL to -9dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-9) - (-57));
break;
case 18:
// set SPKVOL to -8dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-8) - (-57));
break;
case 19:
// set SPKVOL to -7dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-7) - (-57));
break;
case 20:
// set SPKVOL to -6dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-6) - (-57));
break;
case 21:
// set SPKVOL to -5dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-5) - (-57));
break;
case 22:
// set SPKVOL to -4dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-4) - (-57));
break;
case 23:
// set SPKVOL to -3dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-3) - (-57));
break;
case 24:
// set SPKVOL to -2dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-2) - (-57));
break;
case 25:
// set SPKVOL to -1dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((-1) - (-57));
break;
case 26:
// set SPKVOL to -0dB,
address = SPKVOLUMECONTROL;
data = SPKVOLUMECONTROL_SPKVOL((0) - (-57));
break;
case 27:
//Disable DAC soft mute (DACMU = 0)
address = DACCONTROL;
data = 0;
break;
case 28:
//set the Codec's audio interface to the correct mode
address = AUDIOINTERFACE;
data = AUDIOINTERFACE_LOUTR | AUDIOINTERFACE_WL(0) | AUDIOINTERFACE_FMT(2);
//data for DAC and ADC are in left phase. This should put data in lower 16 bits of I2S FIFO
break;
case 29:
//we're done!
gPowerOnState = 0;
gI2CState = I2CState_IDLE;
post issuePowerOnSequenceDone();
doWrite = FALSE;
return;
default:
doWrite = FALSE;
trace(DBG_USR1,"WM8940 found invalid state %d in Powerup Sequence\r\n", gPowerOnState);
}
if(doWrite == TRUE){
if(writeRegister(address, data) == FAIL){
post continuePowerOnSequence();
}
else{
gPowerOnState++;
}
}
else{
//if we're not writing it's because we did something (mostly likely just waited some time for something to settle) and that it's time to move on
gPowerOnState++;
post continuePowerOnSequence();
}
}
command result_t StdControl.init(){
int i;
/**
*
* I2S_SYSCLK = K4 (113)
* I2S_SYNC = J4 (31)
* I2S_BITCLK = K1 (28)
* I2S_DATA_IN = K2 (29)
* I2S_DATA_OUT = G6 (30)
*
*
*
* From section 14.4.1 of the PXA27X developer's manual, the step to init are:
* 1.) set I2S_BITCLK direction
* 2.) choose between I2S or MSB-justified modes. WM8940 uses normal I2S mode
* 3.) optionally use programmed I/O to prime the tx fifo
* 4.) Set the SACRO to enable (set ENB bit) and to set tx and rx fifo thresholds
*
*
**/
for(i =0; i< TEST_LEN; i++){
//make our data signal...just a 100Hz sin
//values should be in lower 16 bits, but should be stored as 32 bits
#if 0
int16_t data = (int16_t)(32767.0*sin(2*3.14159265*100*i/TEST_LEN));
gTxBuffer[i] = (data & 0xFFFF) | ((data & 0xFFFF)<<16);
#else
gTxBuffer[i] = 0xFFFF0000;
#endif
}
gTxNumBytes = TEST_LEN*4;
//cleanDCache((uint8_t *)gTxBuffer, gTxNumBytes);
call I2CSequenceControl.init();
call I2S.setAudioClkDivider(PXA_SYSCLK);
call I2S.setBitClkDir(FALSE);
call I2S.enableMSBJustifiedMode(FALSE);
call I2S.setRxFifoLevel(I2S_8Samples);
call I2S.setTxFifoLevel(I2S_8Samples);
return SUCCESS;
}
task void initI2S(){
call I2S.initI2S();
}
command result_t StdControl.start(){
/**
*To actually have data played out the codec, the following must occur
*
* the audio interface for the PXA27x must be configured
* the codec output must be turned on
* the code must be placed into slave mode (default)
* the audio interface should be enabled
*
* Other notes: codec default sampling rate is 48KHz
*
* see page 64 for suggested power on order
*
*
*
**/
call I2CSequenceControl.start();
post initI2S();
return SUCCESS;
}
command result_t StdControl.stop(){
/**
* See page 65 for suggested power down order
*
*
*
**/
call I2S.enableI2S(FALSE);
call I2S.enablePlayback(FALSE);
return SUCCESS;
}
event void I2S.initI2SDone(){
//host interface to codec is initialized. now initialize the actual codec
#if 1
if(issuePowerOnSequence() == FAIL){
trace(DBG_USR1,"WM8940.issuePowerOnSequence() failed\r\n");
}
#else
call I2S.enableRecord(FALSE);
call I2S.enablePlayback(TRUE);
call I2S.enableI2S(TRUE);
gTxBufferPos = 0;
call BulkTxRx.BulkTransmit((uint8_t *)pcmdata, (pcmdatalen > 8188)? 8188: pcmdatalen);
#endif
}
task void BulkReceiveDone(){
//needs to be protected....but needs to be rewritten anyway to use more than one buffer
//this is only here as a reminder that invalidateDCache must be called on the buffer after
//it's been received
invalidateDCache((uint8_t *)gRxBuffer, gRxNumBytes);
}
async event uint8_t *BulkTxRx.BulkReceiveDone(uint8_t *RxBuffer, uint16_t NumBytes){
gRxBuffer = (uint32_t*)RxBuffer;
gRxNumBytes = NumBytes;
return NULL;
}
task void transmitDone(){
uint32_t pos;
atomic{
pos = gTxBufferPos;
}
trace(DBG_USR1,"transmitDone..pos = %d!\r\n", pos);
}
async event uint8_t *BulkTxRx.BulkTransmitDone(uint8_t *TxBuffer, uint16_t NumBytes){
post transmitDone();
gTxBufferPos += NumBytes;
if(gTxBufferPos >= pcmdatalen){
return NULL;
}
else{
//call BulkTxRx.BulkTransmit((uint8_t *)(pcmdata+gTxBufferPos), ((pcmdatalen-gTxBufferPos) > 8188)? 8188: (pcmdatalen-gTxBufferPos));
return ((uint8_t *)pcmdata) + gTxBufferPos;
}
}
async event BulkTxRxBuffer_t *BulkTxRx.BulkTxRxDone(BulkTxRxBuffer_t *TxRxBuffer, uint16_t NumBytes){
return NULL;
}
task void unknownI2CSequence(){
trace(DBG_USR1,"received runI2CBusSequenceDone for unknown I2C Sequence %d\r\n", gI2CState);
return;
}
task void failedI2CSequence(){
trace(DBG_USR1,"runI2CBusSequence failed for I2C Sequence %d\r\n", gI2CState);
return;
}
task void IDLEI2CSequence(){
trace(DBG_USR1,"received runI2CBusSequenceDone for IDLE I2C State\r\n");
return;
}
event void I2CBusSequence.runI2CBusSequenceDone(i2c_op_t *pOpsExecuted, uint8_t numOpsExecuted, result_t success){
if(success == SUCCESS){
switch(gI2CState){
case I2CState_IDLE:
post IDLEI2CSequence();
break;
case I2CState_PowerOn:
post continuePowerOnSequence();
break;
case I2CState_PowerOff:
break;
default:
post unknownI2CSequence();
}
}
else{
post unknownI2CSequence();
}
return;
}
command result_t Audio.mute(bool enable){
return FAIL;
}
default event result_t Audio.muteDone(result_t success){
return success;
}
command result_t Audio.setVolume(int8_t volumeInDecibels){
uint8_t value;
if((volumeInDecibels > 0) || (volumeInDecibels < -127)){
return FAIL;
}
value = ((volumeInDecibels + 127) * 2) + 1;
return writeRegister(DACDIGITALVOLUME, DACDIGITALVOLUME_DACVOL(value));
}
default event void Audio.setVolumeDone(result_t success){
return;
}
command result_t Audio.setSamplingRate(uint32_t Fs){
return FAIL;
}
default event void Audio.setSamplingRateDone(result_t success){
return;
}
command result_t Audio.audioPlay(uint32_t *buffer, uint32_t numSamples){
return FAIL;
}
default event void Audio.audioPlayDone(uint32_t *buffer, uint32_t numSamples){
return;
}
}
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