[Tinyos-host-mote-wg] [Tinyos-2.0wg] Re: [Tinyos-2-commits] CVS: tinyos-2.x/tos/chips/cc2420 CC2420Command.nc, NONE, 1.1.2.1 CC2420ControlP.nc, NONE, 1.1.2.1 CC2420RadioP.nc, NONE, 1.1.2.1 CC2420Ram.nc, NONE, 1.1.2.1 CC2420ActiveMessageC.nc, 1.1.2.1, 1.1.2.2 CC2420ActiveMessageP.nc, 1.1

[Joe Polastre]

>   3) Adjusted backoff timers for greater throughput and fairness.
>      The 1.x stack had the congestion timer be 4x the initial
>      backoff timer: this creates a capture effect, where a node
>      who just transmitted is more likely to be able to transmit
>      again. I observed this behavior with my slamming test app: one
>      node would transmit a lot, then the other node would transmit
>      a lot. I reversed the relationship and cut the timers in half:
>      initial is now 32us-1ms and congestion is 32us-256us. Now, with
>      two nodes slamming each other, I observe 330-340 pps in each
>      direction, and the tx/rx counts are within 3-4% of each other
>      (reasonable fairness). Given that CCA is being done with
>      a timer in the micaZ, I suspect that Telos throughput would
>      be higher.

The original stack was as per the 802.15.4 backoff timer specification.

>   5) Added another platform component, CC2420PlatformAlarmC, which
>      represents the async timer the platform must supply for the
>      TX backoff/abort logic.

This can be handled with the Timer system, there is no longer a need
for a CC2420 Alarm but rather just an Alarm<T32khz>

>   1) Currently, for sanity in CC2420RadioP, all register commands
>      and accesses are synchronous (blocking). This is fine
>      when you want to do 1 or 2, but could be a serious issue once the
>      Resource interface comes into play and bus access is split-phase.
>      However, making every register access split-phase would make
>      CC2420RadioP have a ridiculously intricate state machine which
>      would take us years to find all of the bugs in. Therefore,
>      the register interfaces also have a mechanism for putting a
>      register command into a RAM buffer. The idea is that if you need
>      to do 10 register ops, you put all of them in a buffer and just send
>      it as one big SPI packet, which would then be a single split-phase
>      op.

We had this debate back in April 04.  Basically the split phase makes
it impossible to deal with from a logic perspective.

-Joe

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